1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL8723BE__FW__H__ 5*4882a593Smuzhiyun #define __RTL8723BE__FW__H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define FW_8192C_SIZE 0x8000 8*4882a593Smuzhiyun #define FW_8192C_START_ADDRESS 0x1000 9*4882a593Smuzhiyun #define FW_8192C_END_ADDRESS 0x5FFF 10*4882a593Smuzhiyun #define FW_8192C_PAGE_SIZE 4096 11*4882a593Smuzhiyun #define FW_8192C_POLLING_DELAY 5 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define USE_OLD_WOWLAN_DEBUG_FW 0 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define H2C_PWEMODE_LENGTH 7 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Fw PS state for RPWM. 18*4882a593Smuzhiyun *BIT[2:0] = HW state 19*4882a593Smuzhiyun *BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state 20*4882a593Smuzhiyun *BIT[4] = sub-state 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define FW_PS_RF_ON BIT(2) 23*4882a593Smuzhiyun #define FW_PS_REGISTER_ACTIVE BIT(3) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define FW_PS_ACK BIT(6) 26*4882a593Smuzhiyun #define FW_PS_TOGGLE BIT(7) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 8723BE RPWM value*/ 29*4882a593Smuzhiyun /* BIT[0] = 1: 32k, 0: 40M*/ 30*4882a593Smuzhiyun #define FW_PS_CLOCK_OFF BIT(0) /* 32k*/ 31*4882a593Smuzhiyun #define FW_PS_CLOCK_ON 0 /*40M*/ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define FW_PS_STATE_MASK (0x0F) 34*4882a593Smuzhiyun #define FW_PS_STATE_HW_MASK (0x07) 35*4882a593Smuzhiyun /*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/ 36*4882a593Smuzhiyun #define FW_PS_STATE_INT_MASK (0x3F) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/ 41*4882a593Smuzhiyun #define FW_PS_STATE_ALL_ON (FW_PS_CLOCK_ON) 42*4882a593Smuzhiyun /* (FW_PS_RF_ON)*/ 43*4882a593Smuzhiyun #define FW_PS_STATE_RF_ON (FW_PS_CLOCK_ON) 44*4882a593Smuzhiyun /* 0x0*/ 45*4882a593Smuzhiyun #define FW_PS_STATE_RF_OFF (FW_PS_CLOCK_ON) 46*4882a593Smuzhiyun /* (FW_PS_STATE_RF_OFF)*/ 47*4882a593Smuzhiyun #define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* For 8723BE H2C PwrMode Cmd ID 5.*/ 51*4882a593Smuzhiyun #define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE)) 52*4882a593Smuzhiyun #define FW_PWR_STATE_RF_OFF 0 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define IS_IN_LOW_POWER_STATE(__fwpsstate) \ 57*4882a593Smuzhiyun (FW_PS_STATE(__fwpsstate) == FW_PS_CLOCK_OFF) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE)) 60*4882a593Smuzhiyun #define FW_PWR_STATE_RF_OFF 0 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun enum rtl8723b_h2c_cmd { 63*4882a593Smuzhiyun H2C_8723B_RSVDPAGE = 0, 64*4882a593Smuzhiyun H2C_8723B_MSRRPT = 1, 65*4882a593Smuzhiyun H2C_8723B_SCAN = 2, 66*4882a593Smuzhiyun H2C_8723B_KEEP_ALIVE_CTRL = 3, 67*4882a593Smuzhiyun H2C_8723B_DISCONNECT_DECISION = 4, 68*4882a593Smuzhiyun H2C_8723B_BCN_RSVDPAGE = 9, 69*4882a593Smuzhiyun H2C_8723B_PROBERSP_RSVDPAGE = 10, 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun H2C_8723B_SETPWRMODE = 0x20, 72*4882a593Smuzhiyun H2C_8723B_PS_LPS_PARA = 0x23, 73*4882a593Smuzhiyun H2C_8723B_P2P_PS_OFFLOAD = 0x24, 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun H2C_8723B_RA_MASK = 0x40, 76*4882a593Smuzhiyun H2C_RSSIBE_REPORT = 0x42, 77*4882a593Smuzhiyun /*Not defined CTW CMD for P2P yet*/ 78*4882a593Smuzhiyun H2C_8723B_P2P_PS_CTW_CMD, 79*4882a593Smuzhiyun MAX_8723B_H2CCMD 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0)) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \ 86*4882a593Smuzhiyun *(u8 *)__ph2ccmd = __val 87*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_RLBM(__ph2ccmd, __val) \ 88*4882a593Smuzhiyun u8p_replace_bits(__ph2ccmd + 1, __val, GENMASK(3, 0)) 89*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \ 90*4882a593Smuzhiyun u8p_replace_bits(__ph2ccmd + 1, __val, GENMASK(7, 4)) 91*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__ph2ccmd, __val) \ 92*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 2) = __val 93*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__ph2ccmd, __val) \ 94*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 3) = __val 95*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__ph2ccmd, __val) \ 96*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 4) = __val 97*4882a593Smuzhiyun #define SET_H2CCMD_PWRMODE_PARM_BYTE5(__ph2ccmd, __val) \ 98*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 5) = __val 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define SET_H2CCMD_MSRRPT_PARM_OPMODE(__ph2ccmd, __val) \ 101*4882a593Smuzhiyun u8p_replace_bits(__ph2ccmd, __val, BIT(0)) 102*4882a593Smuzhiyun #define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__ph2ccmd, __val) \ 103*4882a593Smuzhiyun u8p_replace_bits(__ph2ccmd, __val, BIT(1)) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \ 106*4882a593Smuzhiyun *(u8 *)(__ph2ccmd) = __val 107*4882a593Smuzhiyun #define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \ 108*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 1) = __val 109*4882a593Smuzhiyun #define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \ 110*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 2) = __val 111*4882a593Smuzhiyun #define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__ph2ccmd, __val) \ 112*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 3) = __val 113*4882a593Smuzhiyun #define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__ph2ccmd, __val) \ 114*4882a593Smuzhiyun *(u8 *)(__ph2ccmd + 4) = __val 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, 118*4882a593Smuzhiyun u32 cmd_len, u8 *p_cmdbuffer); 119*4882a593Smuzhiyun void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode); 120*4882a593Smuzhiyun void rtl8723be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus); 121*4882a593Smuzhiyun void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished); 122*4882a593Smuzhiyun void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state); 123*4882a593Smuzhiyun #endif 124