1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL8723BE_DEF_H__ 5*4882a593Smuzhiyun #define __RTL8723BE_DEF_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 8*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_LOWER 1 9*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_UPPER 2 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define RX_MPDU_QUEUE 0 13*4882a593Smuzhiyun #define CHIP_8723B (BIT(1) | BIT(2)) 14*4882a593Smuzhiyun #define NORMAL_CHIP BIT(3) 15*4882a593Smuzhiyun #define CHIP_VENDOR_SMIC BIT(8) 16*4882a593Smuzhiyun /* Currently only for RTL8723B */ 17*4882a593Smuzhiyun #define EXT_VENDOR_ID (BIT(18) | BIT(19)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum rtl_desc_qsel { 20*4882a593Smuzhiyun QSLT_BK = 0x2, 21*4882a593Smuzhiyun QSLT_BE = 0x0, 22*4882a593Smuzhiyun QSLT_VI = 0x5, 23*4882a593Smuzhiyun QSLT_VO = 0x7, 24*4882a593Smuzhiyun QSLT_BEACON = 0x10, 25*4882a593Smuzhiyun QSLT_HIGH = 0x11, 26*4882a593Smuzhiyun QSLT_MGNT = 0x12, 27*4882a593Smuzhiyun QSLT_CMD = 0x13, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum rtl_desc8723e_rate { 31*4882a593Smuzhiyun DESC92C_RATE1M = 0x00, 32*4882a593Smuzhiyun DESC92C_RATE2M = 0x01, 33*4882a593Smuzhiyun DESC92C_RATE5_5M = 0x02, 34*4882a593Smuzhiyun DESC92C_RATE11M = 0x03, 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun DESC92C_RATE6M = 0x04, 37*4882a593Smuzhiyun DESC92C_RATE9M = 0x05, 38*4882a593Smuzhiyun DESC92C_RATE12M = 0x06, 39*4882a593Smuzhiyun DESC92C_RATE18M = 0x07, 40*4882a593Smuzhiyun DESC92C_RATE24M = 0x08, 41*4882a593Smuzhiyun DESC92C_RATE36M = 0x09, 42*4882a593Smuzhiyun DESC92C_RATE48M = 0x0a, 43*4882a593Smuzhiyun DESC92C_RATE54M = 0x0b, 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun DESC92C_RATEMCS0 = 0x0c, 46*4882a593Smuzhiyun DESC92C_RATEMCS1 = 0x0d, 47*4882a593Smuzhiyun DESC92C_RATEMCS2 = 0x0e, 48*4882a593Smuzhiyun DESC92C_RATEMCS3 = 0x0f, 49*4882a593Smuzhiyun DESC92C_RATEMCS4 = 0x10, 50*4882a593Smuzhiyun DESC92C_RATEMCS5 = 0x11, 51*4882a593Smuzhiyun DESC92C_RATEMCS6 = 0x12, 52*4882a593Smuzhiyun DESC92C_RATEMCS7 = 0x13, 53*4882a593Smuzhiyun DESC92C_RATEMCS8 = 0x14, 54*4882a593Smuzhiyun DESC92C_RATEMCS9 = 0x15, 55*4882a593Smuzhiyun DESC92C_RATEMCS10 = 0x16, 56*4882a593Smuzhiyun DESC92C_RATEMCS11 = 0x17, 57*4882a593Smuzhiyun DESC92C_RATEMCS12 = 0x18, 58*4882a593Smuzhiyun DESC92C_RATEMCS13 = 0x19, 59*4882a593Smuzhiyun DESC92C_RATEMCS14 = 0x1a, 60*4882a593Smuzhiyun DESC92C_RATEMCS15 = 0x1b, 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun #endif 63