1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92C_PHY_H__ 5*4882a593Smuzhiyun #define __RTL92C_PHY_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define MAX_PRECMD_CNT 16 8*4882a593Smuzhiyun #define MAX_RFDEPENDCMD_CNT 16 9*4882a593Smuzhiyun #define MAX_POSTCMD_CNT 16 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MAX_DOZE_WAITING_TIMES_9x 64 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define RT_CANNOT_IO(hw) false 14*4882a593Smuzhiyun #define HIGHPOWER_RADIOA_ARRAYLEN 22 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define IQK_ADDA_REG_NUM 16 17*4882a593Smuzhiyun #define MAX_TOLERANCE 5 18*4882a593Smuzhiyun #define IQK_DELAY_TIME 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define APK_BB_REG_NUM 5 21*4882a593Smuzhiyun #define APK_AFE_REG_NUM 16 22*4882a593Smuzhiyun #define APK_CURVE_REG_NUM 4 23*4882a593Smuzhiyun #define PATH_NUM 2 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define LOOP_LIMIT 5 26*4882a593Smuzhiyun #define MAX_STALL_TIME 50 27*4882a593Smuzhiyun #define ANTENNADIVERSITYVALUE 0x80 28*4882a593Smuzhiyun #define MAX_TXPWR_IDX_NMODE_92S 63 29*4882a593Smuzhiyun #define reset_cnt_limit 3 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define IQK_ADDA_REG_NUM 16 32*4882a593Smuzhiyun #define IQK_MAC_REG_NUM 4 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define IQK_DELAY_TIME 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define RF6052_MAX_PATH 2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CT_OFFSET_MAC_ADDR 0X16 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A 41*4882a593Smuzhiyun #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60 42*4882a593Smuzhiyun #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66 43*4882a593Smuzhiyun #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69 44*4882a593Smuzhiyun #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F 47*4882a593Smuzhiyun #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CT_OFFSET_CHANNEL_PLAH 0x75 50*4882a593Smuzhiyun #define CT_OFFSET_THERMAL_METER 0x78 51*4882a593Smuzhiyun #define CT_OFFSET_RF_OPTION 0x79 52*4882a593Smuzhiyun #define CT_OFFSET_VERSION 0x7E 53*4882a593Smuzhiyun #define CT_OFFSET_CUSTOMER_ID 0x7F 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define RTL92C_MAX_PATH_NUM 2 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun enum hw90_block_e { 58*4882a593Smuzhiyun HW90_BLOCK_MAC = 0, 59*4882a593Smuzhiyun HW90_BLOCK_PHY0 = 1, 60*4882a593Smuzhiyun HW90_BLOCK_PHY1 = 2, 61*4882a593Smuzhiyun HW90_BLOCK_RF = 3, 62*4882a593Smuzhiyun HW90_BLOCK_MAXIMUM = 4, 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun enum baseband_config_type { 66*4882a593Smuzhiyun BASEBAND_CONFIG_PHY_REG = 0, 67*4882a593Smuzhiyun BASEBAND_CONFIG_AGC_TAB = 1, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun enum ra_offset_area { 71*4882a593Smuzhiyun RA_OFFSET_LEGACY_OFDM1, 72*4882a593Smuzhiyun RA_OFFSET_LEGACY_OFDM2, 73*4882a593Smuzhiyun RA_OFFSET_HT_OFDM1, 74*4882a593Smuzhiyun RA_OFFSET_HT_OFDM2, 75*4882a593Smuzhiyun RA_OFFSET_HT_OFDM3, 76*4882a593Smuzhiyun RA_OFFSET_HT_OFDM4, 77*4882a593Smuzhiyun RA_OFFSET_HT_CCK, 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun enum antenna_path { 81*4882a593Smuzhiyun ANTENNA_NONE, 82*4882a593Smuzhiyun ANTENNA_D, 83*4882a593Smuzhiyun ANTENNA_C, 84*4882a593Smuzhiyun ANTENNA_CD, 85*4882a593Smuzhiyun ANTENNA_B, 86*4882a593Smuzhiyun ANTENNA_BD, 87*4882a593Smuzhiyun ANTENNA_BC, 88*4882a593Smuzhiyun ANTENNA_BCD, 89*4882a593Smuzhiyun ANTENNA_A, 90*4882a593Smuzhiyun ANTENNA_AD, 91*4882a593Smuzhiyun ANTENNA_AC, 92*4882a593Smuzhiyun ANTENNA_ACD, 93*4882a593Smuzhiyun ANTENNA_AB, 94*4882a593Smuzhiyun ANTENNA_ABD, 95*4882a593Smuzhiyun ANTENNA_ABC, 96*4882a593Smuzhiyun ANTENNA_ABCD 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct r_antenna_select_ofdm { 100*4882a593Smuzhiyun u32 r_tx_antenna:4; 101*4882a593Smuzhiyun u32 r_ant_l:4; 102*4882a593Smuzhiyun u32 r_ant_non_ht:4; 103*4882a593Smuzhiyun u32 r_ant_ht1:4; 104*4882a593Smuzhiyun u32 r_ant_ht2:4; 105*4882a593Smuzhiyun u32 r_ant_ht_s1:4; 106*4882a593Smuzhiyun u32 r_ant_non_ht_s1:4; 107*4882a593Smuzhiyun u32 ofdm_txsc:2; 108*4882a593Smuzhiyun u32 reserved:2; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct r_antenna_select_cck { 112*4882a593Smuzhiyun u8 r_cckrx_enable_2:2; 113*4882a593Smuzhiyun u8 r_cckrx_enable:2; 114*4882a593Smuzhiyun u8 r_ccktx_enable:4; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun struct efuse_contents { 118*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 119*4882a593Smuzhiyun u8 cck_tx_power_idx[6]; 120*4882a593Smuzhiyun u8 ht40_1s_tx_power_idx[6]; 121*4882a593Smuzhiyun u8 ht40_2s_tx_power_idx_diff[3]; 122*4882a593Smuzhiyun u8 ht20_tx_power_idx_diff[3]; 123*4882a593Smuzhiyun u8 ofdm_tx_power_idx_diff[3]; 124*4882a593Smuzhiyun u8 ht40_max_power_offset[3]; 125*4882a593Smuzhiyun u8 ht20_max_power_offset[3]; 126*4882a593Smuzhiyun u8 channel_plan; 127*4882a593Smuzhiyun u8 thermal_meter; 128*4882a593Smuzhiyun u8 rf_option[5]; 129*4882a593Smuzhiyun u8 version; 130*4882a593Smuzhiyun u8 oem_id; 131*4882a593Smuzhiyun u8 regulatory; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct tx_power_struct { 135*4882a593Smuzhiyun u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 136*4882a593Smuzhiyun u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 137*4882a593Smuzhiyun u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 138*4882a593Smuzhiyun u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 139*4882a593Smuzhiyun u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 140*4882a593Smuzhiyun u8 legacy_ht_txpowerdiff; 141*4882a593Smuzhiyun u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 142*4882a593Smuzhiyun u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER]; 143*4882a593Smuzhiyun u8 pwrgroup_cnt; 144*4882a593Smuzhiyun u32 mcs_original_offset[4][16]; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw, 148*4882a593Smuzhiyun enum radio_path rfpath, u32 regaddr, 149*4882a593Smuzhiyun u32 bitmask); 150*4882a593Smuzhiyun void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw, 151*4882a593Smuzhiyun enum radio_path rfpath, u32 regaddr, 152*4882a593Smuzhiyun u32 bitmask, u32 data); 153*4882a593Smuzhiyun bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw); 154*4882a593Smuzhiyun bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw); 155*4882a593Smuzhiyun bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw); 156*4882a593Smuzhiyun bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw, 157*4882a593Smuzhiyun enum radio_path rfpath); 158*4882a593Smuzhiyun void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 159*4882a593Smuzhiyun void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, 160*4882a593Smuzhiyun long *powerlevel); 161*4882a593Smuzhiyun void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); 162*4882a593Smuzhiyun bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, 163*4882a593Smuzhiyun long power_indbm); 164*4882a593Smuzhiyun void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, 165*4882a593Smuzhiyun u8 operation); 166*4882a593Smuzhiyun void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 167*4882a593Smuzhiyun void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw, 168*4882a593Smuzhiyun enum nl80211_channel_type ch_type); 169*4882a593Smuzhiyun void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw); 170*4882a593Smuzhiyun u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw); 171*4882a593Smuzhiyun void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery); 172*4882a593Smuzhiyun void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw); 173*4882a593Smuzhiyun void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 174*4882a593Smuzhiyun bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 175*4882a593Smuzhiyun enum radio_path rfpath); 176*4882a593Smuzhiyun bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 177*4882a593Smuzhiyun bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw, 178*4882a593Smuzhiyun enum rf_pwrstate rfpwr_state); 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #endif 181