1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92S_PHY_H__ 5*4882a593Smuzhiyun #define __RTL92S_PHY_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define MAX_TXPWR_IDX_NMODE_92S 63 8*4882a593Smuzhiyun #define MAX_DOZE_WAITING_TIMES_9x 64 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Channel switch:The size of 11*4882a593Smuzhiyun * command tables for switch channel */ 12*4882a593Smuzhiyun #define MAX_PRECMD_CNT 16 13*4882a593Smuzhiyun #define MAX_RFDEPENDCMD_CNT 16 14*4882a593Smuzhiyun #define MAX_POSTCMD_CNT 16 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define RF90_PATH_MAX 4 17*4882a593Smuzhiyun #define RF6052_MAX_PATH 2 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum version_8192s { 20*4882a593Smuzhiyun VERSION_8192S_ACUT, 21*4882a593Smuzhiyun VERSION_8192S_BCUT, 22*4882a593Smuzhiyun VERSION_8192S_CCUT 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum swchnlcmd_id { 26*4882a593Smuzhiyun CMDID_END, 27*4882a593Smuzhiyun CMDID_SET_TXPOWEROWER_LEVEL, 28*4882a593Smuzhiyun CMDID_BBREGWRITE10, 29*4882a593Smuzhiyun CMDID_WRITEPORT_ULONG, 30*4882a593Smuzhiyun CMDID_WRITEPORT_USHORT, 31*4882a593Smuzhiyun CMDID_WRITEPORT_UCHAR, 32*4882a593Smuzhiyun CMDID_RF_WRITEREG, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct swchnlcmd { 36*4882a593Smuzhiyun enum swchnlcmd_id cmdid; 37*4882a593Smuzhiyun u32 para1; 38*4882a593Smuzhiyun u32 para2; 39*4882a593Smuzhiyun u32 msdelay; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun enum baseband_config_type { 43*4882a593Smuzhiyun /* Radio Path A */ 44*4882a593Smuzhiyun BASEBAND_CONFIG_PHY_REG = 0, 45*4882a593Smuzhiyun /* Radio Path B */ 46*4882a593Smuzhiyun BASEBAND_CONFIG_AGC_TAB = 1, 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define hal_get_firmwareversion(rtlpriv) \ 50*4882a593Smuzhiyun (((struct rt_firmware *)(rtlpriv->rtlhal.pfirmware))->firmwareversion) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 53*4882a593Smuzhiyun void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 54*4882a593Smuzhiyun u32 data); 55*4882a593Smuzhiyun void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation); 56*4882a593Smuzhiyun u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 57*4882a593Smuzhiyun u32 regaddr, u32 bitmask); 58*4882a593Smuzhiyun void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 59*4882a593Smuzhiyun u32 regaddr, u32 bitmask, u32 data); 60*4882a593Smuzhiyun void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw, 61*4882a593Smuzhiyun enum nl80211_channel_type ch_type); 62*4882a593Smuzhiyun u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw); 63*4882a593Smuzhiyun bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw, 64*4882a593Smuzhiyun enum rf_pwrstate rfpower_state); 65*4882a593Smuzhiyun bool rtl92s_phy_mac_config(struct ieee80211_hw *hw); 66*4882a593Smuzhiyun void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw); 67*4882a593Smuzhiyun bool rtl92s_phy_bb_config(struct ieee80211_hw *hw); 68*4882a593Smuzhiyun bool rtl92s_phy_rf_config(struct ieee80211_hw *hw); 69*4882a593Smuzhiyun void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 70*4882a593Smuzhiyun void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel); 71*4882a593Smuzhiyun bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fwcmd_io); 72*4882a593Smuzhiyun void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw); 73*4882a593Smuzhiyun void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval); 74*4882a593Smuzhiyun u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) ; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78