1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL_92S_DM_H__ 5*4882a593Smuzhiyun #define __RTL_92S_DM_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun enum dm_dig_alg { 8*4882a593Smuzhiyun DIG_ALGO_BY_FALSE_ALARM = 0, 9*4882a593Smuzhiyun DIG_ALGO_BY_RSSI = 1, 10*4882a593Smuzhiyun DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2, 11*4882a593Smuzhiyun DIG_ALGO_BY_TOW_PORT = 3, 12*4882a593Smuzhiyun DIG_ALGO_MAX 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum dm_dig_two_port_alg { 16*4882a593Smuzhiyun DIG_TWO_PORT_ALGO_RSSI = 0, 17*4882a593Smuzhiyun DIG_TWO_PORT_ALGO_FALSE_ALARM = 1, 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum dm_dig_dbg { 21*4882a593Smuzhiyun DM_DBG_OFF = 0, 22*4882a593Smuzhiyun DM_DBG_ON = 1, 23*4882a593Smuzhiyun DM_DBG_MAX 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum dm_dig_sta { 27*4882a593Smuzhiyun DM_STA_DIG_OFF = 0, 28*4882a593Smuzhiyun DM_STA_DIG_ON, 29*4882a593Smuzhiyun DM_STA_DIG_MAX 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun enum dm_ratr_sta { 33*4882a593Smuzhiyun DM_RATR_STA_HIGH = 0, 34*4882a593Smuzhiyun DM_RATR_STA_MIDDLEHIGH = 1, 35*4882a593Smuzhiyun DM_RATR_STA_MIDDLE = 2, 36*4882a593Smuzhiyun DM_RATR_STA_MIDDLELOW = 3, 37*4882a593Smuzhiyun DM_RATR_STA_LOW = 4, 38*4882a593Smuzhiyun DM_RATR_STA_ULTRALOW = 5, 39*4882a593Smuzhiyun DM_RATR_STA_MAX 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define DM_TYPE_BYFW 0 43*4882a593Smuzhiyun #define DM_TYPE_BYDRIVER 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define TX_HIGH_PWR_LEVEL_NORMAL 0 46*4882a593Smuzhiyun #define TX_HIGH_PWR_LEVEL_LEVEL1 1 47*4882a593Smuzhiyun #define TX_HIGH_PWR_LEVEL_LEVEL2 2 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define HAL_DM_DIG_DISABLE BIT(0) /* Disable Dig */ 50*4882a593Smuzhiyun #define HAL_DM_HIPWR_DISABLE BIT(1) /* Disable High Power */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TX_HIGHPWR_LEVEL_NORMAL 0 53*4882a593Smuzhiyun #define TX_HIGHPWR_LEVEL_NORMAL1 1 54*4882a593Smuzhiyun #define TX_HIGHPWR_LEVEL_NORMAL2 2 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 57*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define DM_DIG_HIGH_PWR_THRESH_HIGH 75 60*4882a593Smuzhiyun #define DM_DIG_HIGH_PWR_THRESH_LOW 70 61*4882a593Smuzhiyun #define DM_DIG_MIN_NETCORE 0x12 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun void rtl92s_dm_watchdog(struct ieee80211_hw *hw); 64*4882a593Smuzhiyun void rtl92s_dm_init(struct ieee80211_hw *hw); 65*4882a593Smuzhiyun void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68