1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include "../wifi.h"
5*4882a593Smuzhiyun #include "../core.h"
6*4882a593Smuzhiyun #include "../pci.h"
7*4882a593Smuzhiyun #include "reg.h"
8*4882a593Smuzhiyun #include "def.h"
9*4882a593Smuzhiyun #include "phy.h"
10*4882a593Smuzhiyun #include "dm.h"
11*4882a593Smuzhiyun #include "hw.h"
12*4882a593Smuzhiyun #include "fw.h"
13*4882a593Smuzhiyun #include "trx.h"
14*4882a593Smuzhiyun #include "led.h"
15*4882a593Smuzhiyun #include "table.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "../btcoexist/rtl_btc.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/vmalloc.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun
rtl92ee_init_aspm_vars(struct ieee80211_hw * hw)22*4882a593Smuzhiyun static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
25*4882a593Smuzhiyun struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*close ASPM for AMD defaultly */
28*4882a593Smuzhiyun rtlpci->const_amdpci_aspm = 0;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /**
31*4882a593Smuzhiyun * ASPM PS mode.
32*4882a593Smuzhiyun * 0 - Disable ASPM,
33*4882a593Smuzhiyun * 1 - Enable ASPM without Clock Req,
34*4882a593Smuzhiyun * 2 - Enable ASPM with Clock Req,
35*4882a593Smuzhiyun * 3 - Alwyas Enable ASPM with Clock Req,
36*4882a593Smuzhiyun * 4 - Always Enable ASPM without Clock Req.
37*4882a593Smuzhiyun * set defult to RTL8192CE:3 RTL8192E:2
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun rtlpci->const_pci_aspm = 3;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*Setting for PCI-E device */
42*4882a593Smuzhiyun rtlpci->const_devicepci_aspm_setting = 0x03;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*Setting for PCI-E bridge */
45*4882a593Smuzhiyun rtlpci->const_hostpci_aspm_setting = 0x02;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /**
48*4882a593Smuzhiyun * In Hw/Sw Radio Off situation.
49*4882a593Smuzhiyun * 0 - Default,
50*4882a593Smuzhiyun * 1 - From ASPM setting without low Mac Pwr,
51*4882a593Smuzhiyun * 2 - From ASPM setting with low Mac Pwr,
52*4882a593Smuzhiyun * 3 - Bus D3
53*4882a593Smuzhiyun * set default to RTL8192CE:0 RTL8192SE:2
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun rtlpci->const_hwsw_rfoff_d3 = 0;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /**
58*4882a593Smuzhiyun * This setting works for those device with
59*4882a593Smuzhiyun * backdoor ASPM setting such as EPHY setting.
60*4882a593Smuzhiyun * 0 - Not support ASPM,
61*4882a593Smuzhiyun * 1 - Support ASPM,
62*4882a593Smuzhiyun * 2 - According to chipset.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
rtl92ee_init_sw_vars(struct ieee80211_hw * hw)67*4882a593Smuzhiyun static int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
70*4882a593Smuzhiyun struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
71*4882a593Smuzhiyun int err = 0;
72*4882a593Smuzhiyun char *fw_name;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun rtl92ee_bt_reg_init(hw);
75*4882a593Smuzhiyun rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
76*4882a593Smuzhiyun rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun rtlpriv->dm.dm_initialgain_enable = true;
79*4882a593Smuzhiyun rtlpriv->dm.dm_flag = 0;
80*4882a593Smuzhiyun rtlpriv->dm.disable_framebursting = false;
81*4882a593Smuzhiyun rtlpci->transmit_config = CFENDFORM | BIT(15);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /*just 2.4G band*/
84*4882a593Smuzhiyun rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
85*4882a593Smuzhiyun rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
86*4882a593Smuzhiyun rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun rtlpci->receive_config = (RCR_APPFCS |
89*4882a593Smuzhiyun RCR_APP_MIC |
90*4882a593Smuzhiyun RCR_APP_ICV |
91*4882a593Smuzhiyun RCR_APP_PHYST_RXFF |
92*4882a593Smuzhiyun RCR_HTC_LOC_CTRL |
93*4882a593Smuzhiyun RCR_AMF |
94*4882a593Smuzhiyun RCR_ACF |
95*4882a593Smuzhiyun RCR_ACRC32 |
96*4882a593Smuzhiyun RCR_AB |
97*4882a593Smuzhiyun RCR_AM |
98*4882a593Smuzhiyun RCR_APM |
99*4882a593Smuzhiyun 0);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT |
102*4882a593Smuzhiyun IMR_C2HCMD |
103*4882a593Smuzhiyun IMR_HIGHDOK |
104*4882a593Smuzhiyun IMR_MGNTDOK |
105*4882a593Smuzhiyun IMR_BKDOK |
106*4882a593Smuzhiyun IMR_BEDOK |
107*4882a593Smuzhiyun IMR_VIDOK |
108*4882a593Smuzhiyun IMR_VODOK |
109*4882a593Smuzhiyun IMR_RDU |
110*4882a593Smuzhiyun IMR_ROK |
111*4882a593Smuzhiyun 0);
112*4882a593Smuzhiyun rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* for LPS & IPS */
115*4882a593Smuzhiyun rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
116*4882a593Smuzhiyun rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
117*4882a593Smuzhiyun rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
118*4882a593Smuzhiyun rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
119*4882a593Smuzhiyun if (rtlpriv->cfg->mod_params->disable_watchdog)
120*4882a593Smuzhiyun pr_info("watchdog disabled\n");
121*4882a593Smuzhiyun rtlpriv->psc.reg_fwctrl_lps = 3;
122*4882a593Smuzhiyun rtlpriv->psc.reg_max_lps_awakeintvl = 5;
123*4882a593Smuzhiyun /* for ASPM, you can close aspm through
124*4882a593Smuzhiyun * set const_support_pciaspm = 0
125*4882a593Smuzhiyun */
126*4882a593Smuzhiyun rtl92ee_init_aspm_vars(hw);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (rtlpriv->psc.reg_fwctrl_lps == 1)
129*4882a593Smuzhiyun rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
130*4882a593Smuzhiyun else if (rtlpriv->psc.reg_fwctrl_lps == 2)
131*4882a593Smuzhiyun rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
132*4882a593Smuzhiyun else if (rtlpriv->psc.reg_fwctrl_lps == 3)
133*4882a593Smuzhiyun rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* for early mode */
136*4882a593Smuzhiyun rtlpriv->rtlhal.earlymode_enable = false;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*low power */
139*4882a593Smuzhiyun rtlpriv->psc.low_power_enable = false;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* for firmware buf */
142*4882a593Smuzhiyun rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
143*4882a593Smuzhiyun if (!rtlpriv->rtlhal.pfirmware) {
144*4882a593Smuzhiyun pr_err("Can't alloc buffer for fw\n");
145*4882a593Smuzhiyun return 1;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* request fw */
149*4882a593Smuzhiyun fw_name = "rtlwifi/rtl8192eefw.bin";
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun rtlpriv->max_fw_size = 0x8000;
152*4882a593Smuzhiyun pr_info("Using firmware %s\n", fw_name);
153*4882a593Smuzhiyun err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
154*4882a593Smuzhiyun rtlpriv->io.dev, GFP_KERNEL, hw,
155*4882a593Smuzhiyun rtl_fw_cb);
156*4882a593Smuzhiyun if (err) {
157*4882a593Smuzhiyun pr_err("Failed to request firmware!\n");
158*4882a593Smuzhiyun vfree(rtlpriv->rtlhal.pfirmware);
159*4882a593Smuzhiyun rtlpriv->rtlhal.pfirmware = NULL;
160*4882a593Smuzhiyun return 1;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
rtl92ee_deinit_sw_vars(struct ieee80211_hw * hw)166*4882a593Smuzhiyun static void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun if (rtlpriv->rtlhal.pfirmware) {
171*4882a593Smuzhiyun vfree(rtlpriv->rtlhal.pfirmware);
172*4882a593Smuzhiyun rtlpriv->rtlhal.pfirmware = NULL;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* get bt coexist status */
rtl92ee_get_btc_status(void)177*4882a593Smuzhiyun static bool rtl92ee_get_btc_status(void)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun return true;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun static struct rtl_hal_ops rtl8192ee_hal_ops = {
183*4882a593Smuzhiyun .init_sw_vars = rtl92ee_init_sw_vars,
184*4882a593Smuzhiyun .deinit_sw_vars = rtl92ee_deinit_sw_vars,
185*4882a593Smuzhiyun .read_eeprom_info = rtl92ee_read_eeprom_info,
186*4882a593Smuzhiyun .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
187*4882a593Smuzhiyun .hw_init = rtl92ee_hw_init,
188*4882a593Smuzhiyun .hw_disable = rtl92ee_card_disable,
189*4882a593Smuzhiyun .hw_suspend = rtl92ee_suspend,
190*4882a593Smuzhiyun .hw_resume = rtl92ee_resume,
191*4882a593Smuzhiyun .enable_interrupt = rtl92ee_enable_interrupt,
192*4882a593Smuzhiyun .disable_interrupt = rtl92ee_disable_interrupt,
193*4882a593Smuzhiyun .set_network_type = rtl92ee_set_network_type,
194*4882a593Smuzhiyun .set_chk_bssid = rtl92ee_set_check_bssid,
195*4882a593Smuzhiyun .set_qos = rtl92ee_set_qos,
196*4882a593Smuzhiyun .set_bcn_reg = rtl92ee_set_beacon_related_registers,
197*4882a593Smuzhiyun .set_bcn_intv = rtl92ee_set_beacon_interval,
198*4882a593Smuzhiyun .update_interrupt_mask = rtl92ee_update_interrupt_mask,
199*4882a593Smuzhiyun .get_hw_reg = rtl92ee_get_hw_reg,
200*4882a593Smuzhiyun .set_hw_reg = rtl92ee_set_hw_reg,
201*4882a593Smuzhiyun .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
202*4882a593Smuzhiyun .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
203*4882a593Smuzhiyun .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
204*4882a593Smuzhiyun .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
205*4882a593Smuzhiyun .fill_tx_desc = rtl92ee_tx_fill_desc,
206*4882a593Smuzhiyun .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
207*4882a593Smuzhiyun .query_rx_desc = rtl92ee_rx_query_desc,
208*4882a593Smuzhiyun .set_channel_access = rtl92ee_update_channel_access_setting,
209*4882a593Smuzhiyun .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
210*4882a593Smuzhiyun .set_bw_mode = rtl92ee_phy_set_bw_mode,
211*4882a593Smuzhiyun .switch_channel = rtl92ee_phy_sw_chnl,
212*4882a593Smuzhiyun .dm_watchdog = rtl92ee_dm_watchdog,
213*4882a593Smuzhiyun .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
214*4882a593Smuzhiyun .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
215*4882a593Smuzhiyun .led_control = rtl92ee_led_control,
216*4882a593Smuzhiyun .set_desc = rtl92ee_set_desc,
217*4882a593Smuzhiyun .get_desc = rtl92ee_get_desc,
218*4882a593Smuzhiyun .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
219*4882a593Smuzhiyun .get_available_desc = rtl92ee_get_available_desc,
220*4882a593Smuzhiyun .tx_polling = rtl92ee_tx_polling,
221*4882a593Smuzhiyun .enable_hw_sec = rtl92ee_enable_hw_security_config,
222*4882a593Smuzhiyun .set_key = rtl92ee_set_key,
223*4882a593Smuzhiyun .init_sw_leds = rtl92ee_init_sw_leds,
224*4882a593Smuzhiyun .get_bbreg = rtl92ee_phy_query_bb_reg,
225*4882a593Smuzhiyun .set_bbreg = rtl92ee_phy_set_bb_reg,
226*4882a593Smuzhiyun .get_rfreg = rtl92ee_phy_query_rf_reg,
227*4882a593Smuzhiyun .set_rfreg = rtl92ee_phy_set_rf_reg,
228*4882a593Smuzhiyun .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
229*4882a593Smuzhiyun .get_btc_status = rtl92ee_get_btc_status,
230*4882a593Smuzhiyun .c2h_ra_report_handler = rtl92ee_c2h_ra_report_handler,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun static struct rtl_mod_params rtl92ee_mod_params = {
234*4882a593Smuzhiyun .sw_crypto = false,
235*4882a593Smuzhiyun .inactiveps = true,
236*4882a593Smuzhiyun .swctrl_lps = false,
237*4882a593Smuzhiyun .fwctrl_lps = true,
238*4882a593Smuzhiyun .msi_support = true,
239*4882a593Smuzhiyun .dma64 = false,
240*4882a593Smuzhiyun .aspm_support = 1,
241*4882a593Smuzhiyun .debug_level = 0,
242*4882a593Smuzhiyun .debug_mask = 0,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static const struct rtl_hal_cfg rtl92ee_hal_cfg = {
246*4882a593Smuzhiyun .bar_id = 2,
247*4882a593Smuzhiyun .write_readback = true,
248*4882a593Smuzhiyun .name = "rtl92ee_pci",
249*4882a593Smuzhiyun .ops = &rtl8192ee_hal_ops,
250*4882a593Smuzhiyun .mod_params = &rtl92ee_mod_params,
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
253*4882a593Smuzhiyun .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
254*4882a593Smuzhiyun .maps[SYS_CLK] = REG_SYS_CLKR,
255*4882a593Smuzhiyun .maps[MAC_RCR_AM] = AM,
256*4882a593Smuzhiyun .maps[MAC_RCR_AB] = AB,
257*4882a593Smuzhiyun .maps[MAC_RCR_ACRC32] = ACRC32,
258*4882a593Smuzhiyun .maps[MAC_RCR_ACF] = ACF,
259*4882a593Smuzhiyun .maps[MAC_RCR_AAP] = AAP,
260*4882a593Smuzhiyun .maps[MAC_HIMR] = REG_HIMR,
261*4882a593Smuzhiyun .maps[MAC_HIMRE] = REG_HIMRE,
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun .maps[EFUSE_TEST] = REG_EFUSE_TEST,
266*4882a593Smuzhiyun .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
267*4882a593Smuzhiyun .maps[EFUSE_CLK] = 0,
268*4882a593Smuzhiyun .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
269*4882a593Smuzhiyun .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
270*4882a593Smuzhiyun .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
271*4882a593Smuzhiyun .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
272*4882a593Smuzhiyun .maps[EFUSE_ANA8M] = ANA8M,
273*4882a593Smuzhiyun .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
274*4882a593Smuzhiyun .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
275*4882a593Smuzhiyun .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
276*4882a593Smuzhiyun .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun .maps[RWCAM] = REG_CAMCMD,
279*4882a593Smuzhiyun .maps[WCAMI] = REG_CAMWRITE,
280*4882a593Smuzhiyun .maps[RCAMO] = REG_CAMREAD,
281*4882a593Smuzhiyun .maps[CAMDBG] = REG_CAMDBG,
282*4882a593Smuzhiyun .maps[SECR] = REG_SECCFG,
283*4882a593Smuzhiyun .maps[SEC_CAM_NONE] = CAM_NONE,
284*4882a593Smuzhiyun .maps[SEC_CAM_WEP40] = CAM_WEP40,
285*4882a593Smuzhiyun .maps[SEC_CAM_TKIP] = CAM_TKIP,
286*4882a593Smuzhiyun .maps[SEC_CAM_AES] = CAM_AES,
287*4882a593Smuzhiyun .maps[SEC_CAM_WEP104] = CAM_WEP104,
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
290*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
291*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
292*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
293*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
294*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
295*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
296*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
297*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
298*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
299*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
300*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
301*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
304*4882a593Smuzhiyun .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
305*4882a593Smuzhiyun .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
306*4882a593Smuzhiyun .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
307*4882a593Smuzhiyun .maps[RTL_IMR_RDU] = IMR_RDU,
308*4882a593Smuzhiyun .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
309*4882a593Smuzhiyun .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
310*4882a593Smuzhiyun .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
311*4882a593Smuzhiyun .maps[RTL_IMR_TBDER] = IMR_TBDER,
312*4882a593Smuzhiyun .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
313*4882a593Smuzhiyun .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
314*4882a593Smuzhiyun .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
315*4882a593Smuzhiyun .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
316*4882a593Smuzhiyun .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
317*4882a593Smuzhiyun .maps[RTL_IMR_VODOK] = IMR_VODOK,
318*4882a593Smuzhiyun .maps[RTL_IMR_ROK] = IMR_ROK,
319*4882a593Smuzhiyun .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
322*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
323*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
324*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
325*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
326*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
327*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
328*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
329*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
330*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
331*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
332*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
335*4882a593Smuzhiyun .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun static const struct pci_device_id rtl92ee_pci_ids[] = {
339*4882a593Smuzhiyun {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
340*4882a593Smuzhiyun {},
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
346*4882a593Smuzhiyun MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
347*4882a593Smuzhiyun MODULE_LICENSE("GPL");
348*4882a593Smuzhiyun MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
349*4882a593Smuzhiyun MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
352*4882a593Smuzhiyun module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644);
353*4882a593Smuzhiyun module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);
354*4882a593Smuzhiyun module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
355*4882a593Smuzhiyun module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
356*4882a593Smuzhiyun module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
357*4882a593Smuzhiyun module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
358*4882a593Smuzhiyun module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);
359*4882a593Smuzhiyun module_param_named(aspm, rtl92ee_mod_params.aspm_support, int, 0444);
360*4882a593Smuzhiyun module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
361*4882a593Smuzhiyun bool, 0444);
362*4882a593Smuzhiyun MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
363*4882a593Smuzhiyun MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
364*4882a593Smuzhiyun MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
365*4882a593Smuzhiyun MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
366*4882a593Smuzhiyun MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
367*4882a593Smuzhiyun MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
368*4882a593Smuzhiyun MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
369*4882a593Smuzhiyun MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
370*4882a593Smuzhiyun MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
371*4882a593Smuzhiyun MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun static struct pci_driver rtl92ee_driver = {
376*4882a593Smuzhiyun .name = KBUILD_MODNAME,
377*4882a593Smuzhiyun .id_table = rtl92ee_pci_ids,
378*4882a593Smuzhiyun .probe = rtl_pci_probe,
379*4882a593Smuzhiyun .remove = rtl_pci_disconnect,
380*4882a593Smuzhiyun .driver.pm = &rtlwifi_pm_ops,
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun module_pci_driver(rtl92ee_driver);
384