1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include "../wifi.h"
5*4882a593Smuzhiyun #include "reg.h"
6*4882a593Smuzhiyun #include "def.h"
7*4882a593Smuzhiyun #include "phy.h"
8*4882a593Smuzhiyun #include "rf.h"
9*4882a593Smuzhiyun #include "dm.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
12*4882a593Smuzhiyun
rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw * hw,u8 bandwidth)13*4882a593Smuzhiyun void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
16*4882a593Smuzhiyun struct rtl_phy *rtlphy = &rtlpriv->phy;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun switch (bandwidth) {
19*4882a593Smuzhiyun case HT_CHANNEL_WIDTH_20:
20*4882a593Smuzhiyun rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
21*4882a593Smuzhiyun 0xfffff3ff) | BIT(10) | BIT(11));
22*4882a593Smuzhiyun rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
23*4882a593Smuzhiyun rtlphy->rfreg_chnlval[0]);
24*4882a593Smuzhiyun rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
25*4882a593Smuzhiyun rtlphy->rfreg_chnlval[0]);
26*4882a593Smuzhiyun break;
27*4882a593Smuzhiyun case HT_CHANNEL_WIDTH_20_40:
28*4882a593Smuzhiyun rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
29*4882a593Smuzhiyun 0xfffff3ff) | BIT(10));
30*4882a593Smuzhiyun rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
31*4882a593Smuzhiyun rtlphy->rfreg_chnlval[0]);
32*4882a593Smuzhiyun rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
33*4882a593Smuzhiyun rtlphy->rfreg_chnlval[0]);
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun default:
36*4882a593Smuzhiyun pr_err("unknown bandwidth: %#X\n", bandwidth);
37*4882a593Smuzhiyun break;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
rtl92ee_phy_rf6052_config(struct ieee80211_hw * hw)41*4882a593Smuzhiyun bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
44*4882a593Smuzhiyun struct rtl_phy *rtlphy = &rtlpriv->phy;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (rtlphy->rf_type == RF_1T1R)
47*4882a593Smuzhiyun rtlphy->num_total_rfpath = 1;
48*4882a593Smuzhiyun else
49*4882a593Smuzhiyun rtlphy->num_total_rfpath = 2;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return _rtl92ee_phy_rf6052_config_parafile(hw);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
_rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw * hw)54*4882a593Smuzhiyun static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
57*4882a593Smuzhiyun struct rtl_phy *rtlphy = &rtlpriv->phy;
58*4882a593Smuzhiyun u32 u4_regvalue = 0;
59*4882a593Smuzhiyun u8 rfpath;
60*4882a593Smuzhiyun bool rtstatus = true;
61*4882a593Smuzhiyun struct bb_reg_def *pphyreg;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
64*4882a593Smuzhiyun pphyreg = &rtlphy->phyreg_def[rfpath];
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun switch (rfpath) {
67*4882a593Smuzhiyun case RF90_PATH_A:
68*4882a593Smuzhiyun case RF90_PATH_C:
69*4882a593Smuzhiyun u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
70*4882a593Smuzhiyun BRFSI_RFENV);
71*4882a593Smuzhiyun break;
72*4882a593Smuzhiyun case RF90_PATH_B:
73*4882a593Smuzhiyun case RF90_PATH_D:
74*4882a593Smuzhiyun u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
75*4882a593Smuzhiyun BRFSI_RFENV << 16);
76*4882a593Smuzhiyun break;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
80*4882a593Smuzhiyun udelay(1);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
83*4882a593Smuzhiyun udelay(1);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
86*4882a593Smuzhiyun B3WIREADDREAALENGTH, 0x0);
87*4882a593Smuzhiyun udelay(1);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
90*4882a593Smuzhiyun udelay(1);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun switch (rfpath) {
93*4882a593Smuzhiyun case RF90_PATH_A:
94*4882a593Smuzhiyun rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
95*4882a593Smuzhiyun (enum radio_path)rfpath);
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun case RF90_PATH_B:
98*4882a593Smuzhiyun rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
99*4882a593Smuzhiyun (enum radio_path)rfpath);
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun case RF90_PATH_C:
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun case RF90_PATH_D:
104*4882a593Smuzhiyun break;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun switch (rfpath) {
108*4882a593Smuzhiyun case RF90_PATH_A:
109*4882a593Smuzhiyun case RF90_PATH_C:
110*4882a593Smuzhiyun rtl_set_bbreg(hw, pphyreg->rfintfs,
111*4882a593Smuzhiyun BRFSI_RFENV, u4_regvalue);
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun case RF90_PATH_B:
114*4882a593Smuzhiyun case RF90_PATH_D:
115*4882a593Smuzhiyun rtl_set_bbreg(hw, pphyreg->rfintfs,
116*4882a593Smuzhiyun BRFSI_RFENV << 16, u4_regvalue);
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (!rtstatus) {
121*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
122*4882a593Smuzhiyun "Radio[%d] Fail!!\n", rfpath);
123*4882a593Smuzhiyun return false;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
128*4882a593Smuzhiyun return rtstatus;
129*4882a593Smuzhiyun }
130