1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92E_PHY_H__ 5*4882a593Smuzhiyun #define __RTL92E_PHY_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence 8*4882a593Smuzhiyun * will be wrong. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #define MAX_TX_COUNT 4 11*4882a593Smuzhiyun #define TX_1S 0 12*4882a593Smuzhiyun #define TX_2S 1 13*4882a593Smuzhiyun #define TX_3S 2 14*4882a593Smuzhiyun #define TX_4S 3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MAX_POWER_INDEX 0x3f 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MAX_PRECMD_CNT 16 19*4882a593Smuzhiyun #define MAX_RFDEPENDCMD_CNT 16 20*4882a593Smuzhiyun #define MAX_POSTCMD_CNT 16 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MAX_DOZE_WAITING_TIMES_9x 64 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define RT_CANNOT_IO(hw) false 25*4882a593Smuzhiyun #define HIGHPOWER_RADIOA_ARRAYLEN 22 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define IQK_ADDA_REG_NUM 16 28*4882a593Smuzhiyun #define IQK_MAC_REG_NUM 4 29*4882a593Smuzhiyun #define IQK_BB_REG_NUM 9 30*4882a593Smuzhiyun #define MAX_TOLERANCE 5 31*4882a593Smuzhiyun #define IQK_DELAY_TIME 10 32*4882a593Smuzhiyun #define index_mapping_NUM 15 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define APK_BB_REG_NUM 5 35*4882a593Smuzhiyun #define APK_AFE_REG_NUM 16 36*4882a593Smuzhiyun #define APK_CURVE_REG_NUM 4 37*4882a593Smuzhiyun #define PATH_NUM 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define LOOP_LIMIT 5 40*4882a593Smuzhiyun #define MAX_STALL_TIME 50 41*4882a593Smuzhiyun #define ANTENNADIVERSITYVALUE 0x80 42*4882a593Smuzhiyun #define MAX_TXPWR_IDX_NMODE_92S 63 43*4882a593Smuzhiyun #define RESET_CNT_LIMIT 3 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define RF6052_MAX_PATH 2 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CT_OFFSET_MAC_ADDR 0X16 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A 50*4882a593Smuzhiyun #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60 51*4882a593Smuzhiyun #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66 52*4882a593Smuzhiyun #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69 53*4882a593Smuzhiyun #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F 56*4882a593Smuzhiyun #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CT_OFFSET_CHANNEL_PLAH 0x75 59*4882a593Smuzhiyun #define CT_OFFSET_THERMAL_METER 0x78 60*4882a593Smuzhiyun #define CT_OFFSET_RF_OPTION 0x79 61*4882a593Smuzhiyun #define CT_OFFSET_VERSION 0x7E 62*4882a593Smuzhiyun #define CT_OFFSET_CUSTOMER_ID 0x7F 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define RTL92C_MAX_PATH_NUM 2 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum swchnlcmd_id { 67*4882a593Smuzhiyun CMDID_END, 68*4882a593Smuzhiyun CMDID_SET_TXPOWEROWER_LEVEL, 69*4882a593Smuzhiyun CMDID_BBREGWRITE10, 70*4882a593Smuzhiyun CMDID_WRITEPORT_ULONG, 71*4882a593Smuzhiyun CMDID_WRITEPORT_USHORT, 72*4882a593Smuzhiyun CMDID_WRITEPORT_UCHAR, 73*4882a593Smuzhiyun CMDID_RF_WRITEREG, 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct swchnlcmd { 77*4882a593Smuzhiyun enum swchnlcmd_id cmdid; 78*4882a593Smuzhiyun u32 para1; 79*4882a593Smuzhiyun u32 para2; 80*4882a593Smuzhiyun u32 msdelay; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun enum baseband_config_type { 84*4882a593Smuzhiyun BASEBAND_CONFIG_PHY_REG = 0, 85*4882a593Smuzhiyun BASEBAND_CONFIG_AGC_TAB = 1, 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun enum ant_div_type { 89*4882a593Smuzhiyun NO_ANTDIV = 0xFF, 90*4882a593Smuzhiyun CG_TRX_HW_ANTDIV = 0x01, 91*4882a593Smuzhiyun CGCS_RX_HW_ANTDIV = 0x02, 92*4882a593Smuzhiyun FIXED_HW_ANTDIV = 0x03, 93*4882a593Smuzhiyun CG_TRX_SMART_ANTDIV = 0x04, 94*4882a593Smuzhiyun CGCS_RX_SW_ANTDIV = 0x05, 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, 98*4882a593Smuzhiyun u32 regaddr, u32 bitmask); 99*4882a593Smuzhiyun void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, 100*4882a593Smuzhiyun u32 regaddr, u32 bitmask, u32 data); 101*4882a593Smuzhiyun u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw, 102*4882a593Smuzhiyun enum radio_path rfpath, u32 regaddr, 103*4882a593Smuzhiyun u32 bitmask); 104*4882a593Smuzhiyun void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw, 105*4882a593Smuzhiyun enum radio_path rfpath, u32 regaddr, 106*4882a593Smuzhiyun u32 bitmask, u32 data); 107*4882a593Smuzhiyun bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw); 108*4882a593Smuzhiyun bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw); 109*4882a593Smuzhiyun bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw); 110*4882a593Smuzhiyun void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 111*4882a593Smuzhiyun void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, 112*4882a593Smuzhiyun long *powerlevel); 113*4882a593Smuzhiyun void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); 114*4882a593Smuzhiyun void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, 115*4882a593Smuzhiyun u8 operation); 116*4882a593Smuzhiyun void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 117*4882a593Smuzhiyun void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw, 118*4882a593Smuzhiyun enum nl80211_channel_type ch_type); 119*4882a593Smuzhiyun void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw); 120*4882a593Smuzhiyun u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw); 121*4882a593Smuzhiyun void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery); 122*4882a593Smuzhiyun void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta); 123*4882a593Smuzhiyun void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw); 124*4882a593Smuzhiyun void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 125*4882a593Smuzhiyun bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 126*4882a593Smuzhiyun enum radio_path rfpath); 127*4882a593Smuzhiyun bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 128*4882a593Smuzhiyun bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, 129*4882a593Smuzhiyun enum rf_pwrstate rfpwr_state); 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif 132