1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92E_DM_H__ 5*4882a593Smuzhiyun #define __RTL92E_DM_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define OFDMCCA_TH 500 8*4882a593Smuzhiyun #define BW_IND_BIAS 500 9*4882a593Smuzhiyun #define MF_USC 2 10*4882a593Smuzhiyun #define MF_LSC 1 11*4882a593Smuzhiyun #define MF_USC_LSC 0 12*4882a593Smuzhiyun #define MONITOR_TIME 30 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MAIN_ANT 0 15*4882a593Smuzhiyun #define AUX_ANT 1 16*4882a593Smuzhiyun #define MAIN_ANT_CG_TRX 1 17*4882a593Smuzhiyun #define AUX_ANT_CG_TRX 0 18*4882a593Smuzhiyun #define MAIN_ANT_CGCS_RX 0 19*4882a593Smuzhiyun #define AUX_ANT_CGCS_RX 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /*RF REG LIST*/ 22*4882a593Smuzhiyun #define DM_REG_RF_MODE_11N 0x00 23*4882a593Smuzhiyun #define DM_REG_RF_0B_11N 0x0B 24*4882a593Smuzhiyun #define DM_REG_CHNBW_11N 0x18 25*4882a593Smuzhiyun #define DM_REG_T_METER_11N 0x24 26*4882a593Smuzhiyun #define DM_REG_RF_25_11N 0x25 27*4882a593Smuzhiyun #define DM_REG_RF_26_11N 0x26 28*4882a593Smuzhiyun #define DM_REG_RF_27_11N 0x27 29*4882a593Smuzhiyun #define DM_REG_RF_2B_11N 0x2B 30*4882a593Smuzhiyun #define DM_REG_RF_2C_11N 0x2C 31*4882a593Smuzhiyun #define DM_REG_RXRF_A3_11N 0x3C 32*4882a593Smuzhiyun #define DM_REG_T_METER_92D_11N 0x42 33*4882a593Smuzhiyun #define DM_REG_T_METER_92E_11N 0x42 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /*BB REG LIST*/ 36*4882a593Smuzhiyun /*PAGE 8 */ 37*4882a593Smuzhiyun #define DM_REG_BB_CTRL_11N 0x800 38*4882a593Smuzhiyun #define DM_REG_RF_PIN_11N 0x804 39*4882a593Smuzhiyun #define DM_REG_PSD_CTRL_11N 0x808 40*4882a593Smuzhiyun #define DM_REG_TX_ANT_CTRL_11N 0x80C 41*4882a593Smuzhiyun #define DM_REG_BB_PWR_SAV5_11N 0x818 42*4882a593Smuzhiyun #define DM_REG_CCK_RPT_FORMAT_11N 0x824 43*4882a593Smuzhiyun #define DM_REG_RX_DEFUALT_A_11N 0x858 44*4882a593Smuzhiyun #define DM_REG_RX_DEFUALT_B_11N 0x85A 45*4882a593Smuzhiyun #define DM_REG_BB_PWR_SAV3_11N 0x85C 46*4882a593Smuzhiyun #define DM_REG_ANTSEL_CTRL_11N 0x860 47*4882a593Smuzhiyun #define DM_REG_RX_ANT_CTRL_11N 0x864 48*4882a593Smuzhiyun #define DM_REG_PIN_CTRL_11N 0x870 49*4882a593Smuzhiyun #define DM_REG_BB_PWR_SAV1_11N 0x874 50*4882a593Smuzhiyun #define DM_REG_ANTSEL_PATH_11N 0x878 51*4882a593Smuzhiyun #define DM_REG_BB_3WIRE_11N 0x88C 52*4882a593Smuzhiyun #define DM_REG_SC_CNT_11N 0x8C4 53*4882a593Smuzhiyun #define DM_REG_PSD_DATA_11N 0x8B4 54*4882a593Smuzhiyun /*PAGE 9*/ 55*4882a593Smuzhiyun #define DM_REG_ANT_MAPPING1_11N 0x914 56*4882a593Smuzhiyun #define DM_REG_ANT_MAPPING2_11N 0x918 57*4882a593Smuzhiyun /*PAGE A*/ 58*4882a593Smuzhiyun #define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00 59*4882a593Smuzhiyun #define DM_REG_CCK_CCA_11N 0xA0A 60*4882a593Smuzhiyun #define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C 61*4882a593Smuzhiyun #define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10 62*4882a593Smuzhiyun #define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14 63*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA1_11N 0xA22 64*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA2_11N 0xA23 65*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA3_11N 0xA24 66*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA4_11N 0xA25 67*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA5_11N 0xA26 68*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA6_11N 0xA27 69*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA7_11N 0xA28 70*4882a593Smuzhiyun #define DM_REG_CCK_FILTER_PARA8_11N 0xA29 71*4882a593Smuzhiyun #define DM_REG_CCK_FA_RST_11N 0xA2C 72*4882a593Smuzhiyun #define DM_REG_CCK_FA_MSB_11N 0xA58 73*4882a593Smuzhiyun #define DM_REG_CCK_FA_LSB_11N 0xA5C 74*4882a593Smuzhiyun #define DM_REG_CCK_CCA_CNT_11N 0xA60 75*4882a593Smuzhiyun #define DM_REG_BB_PWR_SAV4_11N 0xA74 76*4882a593Smuzhiyun /*PAGE B */ 77*4882a593Smuzhiyun #define DM_REG_LNA_SWITCH_11N 0xB2C 78*4882a593Smuzhiyun #define DM_REG_PATH_SWITCH_11N 0xB30 79*4882a593Smuzhiyun #define DM_REG_RSSI_CTRL_11N 0xB38 80*4882a593Smuzhiyun #define DM_REG_CONFIG_ANTA_11N 0xB68 81*4882a593Smuzhiyun #define DM_REG_RSSI_BT_11N 0xB9C 82*4882a593Smuzhiyun /*PAGE C */ 83*4882a593Smuzhiyun #define DM_REG_OFDM_FA_HOLDC_11N 0xC00 84*4882a593Smuzhiyun #define DM_REG_RX_PATH_11N 0xC04 85*4882a593Smuzhiyun #define DM_REG_TRMUX_11N 0xC08 86*4882a593Smuzhiyun #define DM_REG_OFDM_FA_RSTC_11N 0xC0C 87*4882a593Smuzhiyun #define DM_REG_RXIQI_MATRIX_11N 0xC14 88*4882a593Smuzhiyun #define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C 89*4882a593Smuzhiyun #define DM_REG_IGI_A_11N 0xC50 90*4882a593Smuzhiyun #define DM_REG_ANTDIV_PARA2_11N 0xC54 91*4882a593Smuzhiyun #define DM_REG_IGI_B_11N 0xC58 92*4882a593Smuzhiyun #define DM_REG_ANTDIV_PARA3_11N 0xC5C 93*4882a593Smuzhiyun #define DM_REG_L1SBD_PD_CH_11N 0XC6C 94*4882a593Smuzhiyun #define DM_REG_BB_PWR_SAV2_11N 0xC70 95*4882a593Smuzhiyun #define DM_REG_RX_OFF_11N 0xC7C 96*4882a593Smuzhiyun #define DM_REG_TXIQK_MATRIXA_11N 0xC80 97*4882a593Smuzhiyun #define DM_REG_TXIQK_MATRIXB_11N 0xC88 98*4882a593Smuzhiyun #define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 99*4882a593Smuzhiyun #define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C 100*4882a593Smuzhiyun #define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 101*4882a593Smuzhiyun #define DM_REG_ANTDIV_PARA1_11N 0xCA4 102*4882a593Smuzhiyun #define DM_REG_OFDM_FA_TYPE1_11N 0xCF0 103*4882a593Smuzhiyun /*PAGE D */ 104*4882a593Smuzhiyun #define DM_REG_OFDM_FA_RSTD_11N 0xD00 105*4882a593Smuzhiyun #define DM_REG_OFDM_FA_TYPE2_11N 0xDA0 106*4882a593Smuzhiyun #define DM_REG_OFDM_FA_TYPE3_11N 0xDA4 107*4882a593Smuzhiyun #define DM_REG_OFDM_FA_TYPE4_11N 0xDA8 108*4882a593Smuzhiyun /*PAGE E */ 109*4882a593Smuzhiyun #define DM_REG_TXAGC_A_6_18_11N 0xE00 110*4882a593Smuzhiyun #define DM_REG_TXAGC_A_24_54_11N 0xE04 111*4882a593Smuzhiyun #define DM_REG_TXAGC_A_1_MCS32_11N 0xE08 112*4882a593Smuzhiyun #define DM_REG_TXAGC_A_MCS0_3_11N 0xE10 113*4882a593Smuzhiyun #define DM_REG_TXAGC_A_MCS4_7_11N 0xE14 114*4882a593Smuzhiyun #define DM_REG_TXAGC_A_MCS8_11_11N 0xE18 115*4882a593Smuzhiyun #define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C 116*4882a593Smuzhiyun #define DM_REG_FPGA0_IQK_11N 0xE28 117*4882a593Smuzhiyun #define DM_REG_TXIQK_TONE_A_11N 0xE30 118*4882a593Smuzhiyun #define DM_REG_RXIQK_TONE_A_11N 0xE34 119*4882a593Smuzhiyun #define DM_REG_TXIQK_PI_A_11N 0xE38 120*4882a593Smuzhiyun #define DM_REG_RXIQK_PI_A_11N 0xE3C 121*4882a593Smuzhiyun #define DM_REG_TXIQK_11N 0xE40 122*4882a593Smuzhiyun #define DM_REG_RXIQK_11N 0xE44 123*4882a593Smuzhiyun #define DM_REG_IQK_AGC_PTS_11N 0xE48 124*4882a593Smuzhiyun #define DM_REG_IQK_AGC_RSP_11N 0xE4C 125*4882a593Smuzhiyun #define DM_REG_BLUETOOTH_11N 0xE6C 126*4882a593Smuzhiyun #define DM_REG_RX_WAIT_CCA_11N 0xE70 127*4882a593Smuzhiyun #define DM_REG_TX_CCK_RFON_11N 0xE74 128*4882a593Smuzhiyun #define DM_REG_TX_CCK_BBON_11N 0xE78 129*4882a593Smuzhiyun #define DM_REG_OFDM_RFON_11N 0xE7C 130*4882a593Smuzhiyun #define DM_REG_OFDM_BBON_11N 0xE80 131*4882a593Smuzhiyun #define DM_REG_TX2RX_11N 0xE84 132*4882a593Smuzhiyun #define DM_REG_TX2TX_11N 0xE88 133*4882a593Smuzhiyun #define DM_REG_RX_CCK_11N 0xE8C 134*4882a593Smuzhiyun #define DM_REG_RX_OFDM_11N 0xED0 135*4882a593Smuzhiyun #define DM_REG_RX_WAIT_RIFS_11N 0xED4 136*4882a593Smuzhiyun #define DM_REG_RX2RX_11N 0xED8 137*4882a593Smuzhiyun #define DM_REG_STANDBY_11N 0xEDC 138*4882a593Smuzhiyun #define DM_REG_SLEEP_11N 0xEE0 139*4882a593Smuzhiyun #define DM_REG_PMPD_ANAEN_11N 0xEEC 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /*MAC REG LIST*/ 142*4882a593Smuzhiyun #define DM_REG_BB_RST_11N 0x02 143*4882a593Smuzhiyun #define DM_REG_ANTSEL_PIN_11N 0x4C 144*4882a593Smuzhiyun #define DM_REG_EARLY_MODE_11N 0x4D0 145*4882a593Smuzhiyun #define DM_REG_RSSI_MONITOR_11N 0x4FE 146*4882a593Smuzhiyun #define DM_REG_EDCA_VO_11N 0x500 147*4882a593Smuzhiyun #define DM_REG_EDCA_VI_11N 0x504 148*4882a593Smuzhiyun #define DM_REG_EDCA_BE_11N 0x508 149*4882a593Smuzhiyun #define DM_REG_EDCA_BK_11N 0x50C 150*4882a593Smuzhiyun #define DM_REG_TXPAUSE_11N 0x522 151*4882a593Smuzhiyun #define DM_REG_RESP_TX_11N 0x6D8 152*4882a593Smuzhiyun #define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0 153*4882a593Smuzhiyun #define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /*DIG Related*/ 156*4882a593Smuzhiyun #define DM_BIT_IGI_11N 0x0000007F 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define HAL_DM_DIG_DISABLE BIT(0) 159*4882a593Smuzhiyun #define HAL_DM_HIPWR_DISABLE BIT(1) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define OFDM_TABLE_LENGTH 43 162*4882a593Smuzhiyun #define CCK_TABLE_LENGTH 33 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define OFDM_TABLE_SIZE 43 165*4882a593Smuzhiyun #define CCK_TABLE_SIZE 33 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define BW_AUTO_SWITCH_HIGH_LOW 25 168*4882a593Smuzhiyun #define BW_AUTO_SWITCH_LOW_HIGH 30 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define DM_DIG_FA_UPPER 0x3e 171*4882a593Smuzhiyun #define DM_DIG_FA_LOWER 0x1e 172*4882a593Smuzhiyun #define DM_DIG_FA_TH0 0x200 173*4882a593Smuzhiyun #define DM_DIG_FA_TH1 0x300 174*4882a593Smuzhiyun #define DM_DIG_FA_TH2 0x400 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define RXPATHSELECTION_SS_TH_LOW 30 177*4882a593Smuzhiyun #define RXPATHSELECTION_DIFF_TH 18 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define DM_RATR_STA_INIT 0 180*4882a593Smuzhiyun #define DM_RATR_STA_HIGH 1 181*4882a593Smuzhiyun #define DM_RATR_STA_MIDDLE 2 182*4882a593Smuzhiyun #define DM_RATR_STA_LOW 3 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define CTS2SELF_THVAL 30 185*4882a593Smuzhiyun #define REGC38_TH 20 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define WAIOTTHVAL 25 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_NORMAL 0 190*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_LEVEL1 1 191*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_LEVEL2 2 192*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_BT1 3 193*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_BT2 4 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define DM_TYPE_BYFW 0 196*4882a593Smuzhiyun #define DM_TYPE_BYDRIVER 1 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 199*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 200*4882a593Smuzhiyun #define TXPWRTRACK_MAX_IDX 6 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* Dynamic ATC switch */ 203*4882a593Smuzhiyun #define ATC_STATUS_OFF 0x0 /* enable */ 204*4882a593Smuzhiyun #define ATC_STATUS_ON 0x1 /* disable */ 205*4882a593Smuzhiyun #define CFO_THRESHOLD_XTAL 10 /* kHz */ 206*4882a593Smuzhiyun #define CFO_THRESHOLD_ATC 80 /* kHz */ 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* RSSI Dump Message */ 209*4882a593Smuzhiyun #define RA_RSSIDUMP 0xcb0 210*4882a593Smuzhiyun #define RB_RSSIDUMP 0xcb1 211*4882a593Smuzhiyun #define RS1_RXEVMDUMP 0xcb2 212*4882a593Smuzhiyun #define RS2_RXEVMDUMP 0xcb3 213*4882a593Smuzhiyun #define RA_RXSNRDUMP 0xcb4 214*4882a593Smuzhiyun #define RB_RXSNRDUMP 0xcb5 215*4882a593Smuzhiyun #define RA_CFOSHORTDUMP 0xcb6 216*4882a593Smuzhiyun #define RB_CFOSHORTDUMP 0xcb8 217*4882a593Smuzhiyun #define RA_CFOLONGDUMP 0xcba 218*4882a593Smuzhiyun #define RB_CFOLONGDUMP 0xcbc 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun void rtl92ee_dm_init(struct ieee80211_hw *hw); 221*4882a593Smuzhiyun void rtl92ee_dm_watchdog(struct ieee80211_hw *hw); 222*4882a593Smuzhiyun void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, 223*4882a593Smuzhiyun u8 cur_thres); 224*4882a593Smuzhiyun void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi); 225*4882a593Smuzhiyun void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw); 226*4882a593Smuzhiyun void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 227*4882a593Smuzhiyun void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw, 228*4882a593Smuzhiyun u8 rate, bool collision_state); 229*4882a593Smuzhiyun #endif 230