1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92E_DEF_H__ 5*4882a593Smuzhiyun #define __RTL92E_DEF_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define RX_DESC_NUM_92E 512 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 10*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_LOWER 1 11*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_UPPER 2 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define RX_MPDU_QUEUE 0 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define IS_HT_RATE(_rate) \ 16*4882a593Smuzhiyun (_rate >= DESC92C_RATEMCS0) 17*4882a593Smuzhiyun #define IS_CCK_RATE(_rate) \ 18*4882a593Smuzhiyun (_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M) 19*4882a593Smuzhiyun #define IS_OFDM_RATE(_rate) \ 20*4882a593Smuzhiyun (_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun enum version_8192e { 23*4882a593Smuzhiyun VERSION_TEST_CHIP_2T2R_8192E = 0x0024, 24*4882a593Smuzhiyun VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C, 25*4882a593Smuzhiyun VERSION_UNKNOWN = 0xFF, 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun enum rtl_desc_qsel { 29*4882a593Smuzhiyun QSLT_BK = 0x2, 30*4882a593Smuzhiyun QSLT_BE = 0x0, 31*4882a593Smuzhiyun QSLT_VI = 0x5, 32*4882a593Smuzhiyun QSLT_VO = 0x7, 33*4882a593Smuzhiyun QSLT_BEACON = 0x10, 34*4882a593Smuzhiyun QSLT_HIGH = 0x11, 35*4882a593Smuzhiyun QSLT_MGNT = 0x12, 36*4882a593Smuzhiyun QSLT_CMD = 0x13, 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun enum rtl_desc92c_rate { 40*4882a593Smuzhiyun DESC92C_RATE1M = 0x00, 41*4882a593Smuzhiyun DESC92C_RATE2M = 0x01, 42*4882a593Smuzhiyun DESC92C_RATE5_5M = 0x02, 43*4882a593Smuzhiyun DESC92C_RATE11M = 0x03, 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun DESC92C_RATE6M = 0x04, 46*4882a593Smuzhiyun DESC92C_RATE9M = 0x05, 47*4882a593Smuzhiyun DESC92C_RATE12M = 0x06, 48*4882a593Smuzhiyun DESC92C_RATE18M = 0x07, 49*4882a593Smuzhiyun DESC92C_RATE24M = 0x08, 50*4882a593Smuzhiyun DESC92C_RATE36M = 0x09, 51*4882a593Smuzhiyun DESC92C_RATE48M = 0x0a, 52*4882a593Smuzhiyun DESC92C_RATE54M = 0x0b, 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun DESC92C_RATEMCS0 = 0x0c, 55*4882a593Smuzhiyun DESC92C_RATEMCS1 = 0x0d, 56*4882a593Smuzhiyun DESC92C_RATEMCS2 = 0x0e, 57*4882a593Smuzhiyun DESC92C_RATEMCS3 = 0x0f, 58*4882a593Smuzhiyun DESC92C_RATEMCS4 = 0x10, 59*4882a593Smuzhiyun DESC92C_RATEMCS5 = 0x11, 60*4882a593Smuzhiyun DESC92C_RATEMCS6 = 0x12, 61*4882a593Smuzhiyun DESC92C_RATEMCS7 = 0x13, 62*4882a593Smuzhiyun DESC92C_RATEMCS8 = 0x14, 63*4882a593Smuzhiyun DESC92C_RATEMCS9 = 0x15, 64*4882a593Smuzhiyun DESC92C_RATEMCS10 = 0x16, 65*4882a593Smuzhiyun DESC92C_RATEMCS11 = 0x17, 66*4882a593Smuzhiyun DESC92C_RATEMCS12 = 0x18, 67*4882a593Smuzhiyun DESC92C_RATEMCS13 = 0x19, 68*4882a593Smuzhiyun DESC92C_RATEMCS14 = 0x1a, 69*4882a593Smuzhiyun DESC92C_RATEMCS15 = 0x1b, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun #endif 72