1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92C_DM_H__ 5*4882a593Smuzhiyun #define __RTL92C_DM_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define HAL_DM_DIG_DISABLE BIT(0) 8*4882a593Smuzhiyun #define HAL_DM_HIPWR_DISABLE BIT(1) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define OFDM_TABLE_LENGTH 37 11*4882a593Smuzhiyun #define OFDM_TABLE_SIZE_92D 43 12*4882a593Smuzhiyun #define CCK_TABLE_LENGTH 33 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CCK_TABLE_SIZE 33 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define BW_AUTO_SWITCH_HIGH_LOW 25 17*4882a593Smuzhiyun #define BW_AUTO_SWITCH_LOW_HIGH 30 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define DM_DIG_FA_UPPER 0x32 20*4882a593Smuzhiyun #define DM_DIG_FA_LOWER 0x20 21*4882a593Smuzhiyun #define DM_DIG_FA_TH0 0x100 22*4882a593Smuzhiyun #define DM_DIG_FA_TH1 0x400 23*4882a593Smuzhiyun #define DM_DIG_FA_TH2 0x600 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define RXPATHSELECTION_SS_TH_LOW 30 26*4882a593Smuzhiyun #define RXPATHSELECTION_DIFF_TH 18 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define DM_RATR_STA_INIT 0 29*4882a593Smuzhiyun #define DM_RATR_STA_HIGH 1 30*4882a593Smuzhiyun #define DM_RATR_STA_MIDDLE 2 31*4882a593Smuzhiyun #define DM_RATR_STA_LOW 3 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CTS2SELF_THVAL 30 34*4882a593Smuzhiyun #define REGC38_TH 20 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define WAIOTTHVAL 25 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_NORMAL 0 39*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_LEVEL1 1 40*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_LEVEL2 2 41*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_BT1 3 42*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_BT2 4 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define DM_TYPE_BYFW 0 45*4882a593Smuzhiyun #define DM_TYPE_BYDRIVER 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 48*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 49*4882a593Smuzhiyun #define INDEX_MAPPING_NUM 13 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct swat { 52*4882a593Smuzhiyun u8 failure_cnt; 53*4882a593Smuzhiyun u8 try_flag; 54*4882a593Smuzhiyun u8 stop_trying; 55*4882a593Smuzhiyun long pre_rssi; 56*4882a593Smuzhiyun long trying_threshold; 57*4882a593Smuzhiyun u8 cur_antenna; 58*4882a593Smuzhiyun u8 pre_antenna; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun enum tag_dynamic_init_gain_operation_type_definition { 62*4882a593Smuzhiyun DIG_TYPE_THRESH_HIGH = 0, 63*4882a593Smuzhiyun DIG_TYPE_THRESH_LOW = 1, 64*4882a593Smuzhiyun DIG_TYPE_BACKOFF = 2, 65*4882a593Smuzhiyun DIG_TYPE_RX_GAIN_MIN = 3, 66*4882a593Smuzhiyun DIG_TYPE_RX_GAIN_MAX = 4, 67*4882a593Smuzhiyun DIG_TYPE_ENABLE = 5, 68*4882a593Smuzhiyun DIG_TYPE_DISABLE = 6, 69*4882a593Smuzhiyun DIG_OP_TYPE_MAX 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun enum dm_1r_cca { 73*4882a593Smuzhiyun CCA_1R = 0, 74*4882a593Smuzhiyun CCA_2R = 1, 75*4882a593Smuzhiyun CCA_MAX = 2, 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun enum dm_rf { 79*4882a593Smuzhiyun RF_SAVE = 0, 80*4882a593Smuzhiyun RF_NORMAL = 1, 81*4882a593Smuzhiyun RF_MAX = 2, 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun enum dm_sw_ant_switch { 85*4882a593Smuzhiyun ANS_ANTENNA_B = 1, 86*4882a593Smuzhiyun ANS_ANTENNA_A = 2, 87*4882a593Smuzhiyun ANS_ANTENNA_MAX = 3, 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun void rtl92d_dm_init(struct ieee80211_hw *hw); 91*4882a593Smuzhiyun void rtl92d_dm_watchdog(struct ieee80211_hw *hw); 92*4882a593Smuzhiyun void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw); 93*4882a593Smuzhiyun void rtl92d_dm_write_dig(struct ieee80211_hw *hw); 94*4882a593Smuzhiyun void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw); 95*4882a593Smuzhiyun void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif 98