1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include "../wifi.h"
5*4882a593Smuzhiyun #include "../base.h"
6*4882a593Smuzhiyun #include "../core.h"
7*4882a593Smuzhiyun #include "reg.h"
8*4882a593Smuzhiyun #include "def.h"
9*4882a593Smuzhiyun #include "phy.h"
10*4882a593Smuzhiyun #include "dm.h"
11*4882a593Smuzhiyun #include "fw.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define UNDEC_SM_PWDB entry_min_undec_sm_pwdb
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = {
16*4882a593Smuzhiyun 0x7f8001fe, /* 0, +6.0dB */
17*4882a593Smuzhiyun 0x788001e2, /* 1, +5.5dB */
18*4882a593Smuzhiyun 0x71c001c7, /* 2, +5.0dB */
19*4882a593Smuzhiyun 0x6b8001ae, /* 3, +4.5dB */
20*4882a593Smuzhiyun 0x65400195, /* 4, +4.0dB */
21*4882a593Smuzhiyun 0x5fc0017f, /* 5, +3.5dB */
22*4882a593Smuzhiyun 0x5a400169, /* 6, +3.0dB */
23*4882a593Smuzhiyun 0x55400155, /* 7, +2.5dB */
24*4882a593Smuzhiyun 0x50800142, /* 8, +2.0dB */
25*4882a593Smuzhiyun 0x4c000130, /* 9, +1.5dB */
26*4882a593Smuzhiyun 0x47c0011f, /* 10, +1.0dB */
27*4882a593Smuzhiyun 0x43c0010f, /* 11, +0.5dB */
28*4882a593Smuzhiyun 0x40000100, /* 12, +0dB */
29*4882a593Smuzhiyun 0x3c8000f2, /* 13, -0.5dB */
30*4882a593Smuzhiyun 0x390000e4, /* 14, -1.0dB */
31*4882a593Smuzhiyun 0x35c000d7, /* 15, -1.5dB */
32*4882a593Smuzhiyun 0x32c000cb, /* 16, -2.0dB */
33*4882a593Smuzhiyun 0x300000c0, /* 17, -2.5dB */
34*4882a593Smuzhiyun 0x2d4000b5, /* 18, -3.0dB */
35*4882a593Smuzhiyun 0x2ac000ab, /* 19, -3.5dB */
36*4882a593Smuzhiyun 0x288000a2, /* 20, -4.0dB */
37*4882a593Smuzhiyun 0x26000098, /* 21, -4.5dB */
38*4882a593Smuzhiyun 0x24000090, /* 22, -5.0dB */
39*4882a593Smuzhiyun 0x22000088, /* 23, -5.5dB */
40*4882a593Smuzhiyun 0x20000080, /* 24, -6.0dB */
41*4882a593Smuzhiyun 0x1e400079, /* 25, -6.5dB */
42*4882a593Smuzhiyun 0x1c800072, /* 26, -7.0dB */
43*4882a593Smuzhiyun 0x1b00006c, /* 27. -7.5dB */
44*4882a593Smuzhiyun 0x19800066, /* 28, -8.0dB */
45*4882a593Smuzhiyun 0x18000060, /* 29, -8.5dB */
46*4882a593Smuzhiyun 0x16c0005b, /* 30, -9.0dB */
47*4882a593Smuzhiyun 0x15800056, /* 31, -9.5dB */
48*4882a593Smuzhiyun 0x14400051, /* 32, -10.0dB */
49*4882a593Smuzhiyun 0x1300004c, /* 33, -10.5dB */
50*4882a593Smuzhiyun 0x12000048, /* 34, -11.0dB */
51*4882a593Smuzhiyun 0x11000044, /* 35, -11.5dB */
52*4882a593Smuzhiyun 0x10000040, /* 36, -12.0dB */
53*4882a593Smuzhiyun 0x0f00003c, /* 37, -12.5dB */
54*4882a593Smuzhiyun 0x0e400039, /* 38, -13.0dB */
55*4882a593Smuzhiyun 0x0d800036, /* 39, -13.5dB */
56*4882a593Smuzhiyun 0x0cc00033, /* 40, -14.0dB */
57*4882a593Smuzhiyun 0x0c000030, /* 41, -14.5dB */
58*4882a593Smuzhiyun 0x0b40002d, /* 42, -15.0dB */
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
62*4882a593Smuzhiyun {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
63*4882a593Smuzhiyun {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
64*4882a593Smuzhiyun {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
65*4882a593Smuzhiyun {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
66*4882a593Smuzhiyun {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
67*4882a593Smuzhiyun {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
68*4882a593Smuzhiyun {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
69*4882a593Smuzhiyun {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
70*4882a593Smuzhiyun {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
71*4882a593Smuzhiyun {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
72*4882a593Smuzhiyun {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
73*4882a593Smuzhiyun {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
74*4882a593Smuzhiyun {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
75*4882a593Smuzhiyun {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
76*4882a593Smuzhiyun {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
77*4882a593Smuzhiyun {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
78*4882a593Smuzhiyun {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
79*4882a593Smuzhiyun {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
80*4882a593Smuzhiyun {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
81*4882a593Smuzhiyun {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
82*4882a593Smuzhiyun {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
83*4882a593Smuzhiyun {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
84*4882a593Smuzhiyun {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
85*4882a593Smuzhiyun {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
86*4882a593Smuzhiyun {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
87*4882a593Smuzhiyun {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
88*4882a593Smuzhiyun {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
89*4882a593Smuzhiyun {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
90*4882a593Smuzhiyun {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
91*4882a593Smuzhiyun {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
92*4882a593Smuzhiyun {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
93*4882a593Smuzhiyun {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
94*4882a593Smuzhiyun {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
98*4882a593Smuzhiyun {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
99*4882a593Smuzhiyun {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
100*4882a593Smuzhiyun {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
101*4882a593Smuzhiyun {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
102*4882a593Smuzhiyun {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
103*4882a593Smuzhiyun {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
104*4882a593Smuzhiyun {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
105*4882a593Smuzhiyun {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
106*4882a593Smuzhiyun {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
107*4882a593Smuzhiyun {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
108*4882a593Smuzhiyun {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
109*4882a593Smuzhiyun {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
110*4882a593Smuzhiyun {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
111*4882a593Smuzhiyun {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
112*4882a593Smuzhiyun {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
113*4882a593Smuzhiyun {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
114*4882a593Smuzhiyun {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
115*4882a593Smuzhiyun {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
116*4882a593Smuzhiyun {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
117*4882a593Smuzhiyun {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
118*4882a593Smuzhiyun {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
119*4882a593Smuzhiyun {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
120*4882a593Smuzhiyun {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
121*4882a593Smuzhiyun {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
122*4882a593Smuzhiyun {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
123*4882a593Smuzhiyun {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
124*4882a593Smuzhiyun {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
125*4882a593Smuzhiyun {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
126*4882a593Smuzhiyun {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
127*4882a593Smuzhiyun {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
128*4882a593Smuzhiyun {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
129*4882a593Smuzhiyun {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
130*4882a593Smuzhiyun {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw * hw)133*4882a593Smuzhiyun static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun u32 ret_value;
136*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
137*4882a593Smuzhiyun struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
138*4882a593Smuzhiyun unsigned long flag = 0;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* hold ofdm counter */
141*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
142*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
145*4882a593Smuzhiyun falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
146*4882a593Smuzhiyun falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
147*4882a593Smuzhiyun ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
148*4882a593Smuzhiyun falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
149*4882a593Smuzhiyun ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
150*4882a593Smuzhiyun falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
151*4882a593Smuzhiyun falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
152*4882a593Smuzhiyun ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
153*4882a593Smuzhiyun falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
154*4882a593Smuzhiyun falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
155*4882a593Smuzhiyun falsealm_cnt->cnt_rate_illegal +
156*4882a593Smuzhiyun falsealm_cnt->cnt_crc8_fail +
157*4882a593Smuzhiyun falsealm_cnt->cnt_mcs_fail +
158*4882a593Smuzhiyun falsealm_cnt->cnt_fast_fsync_fail +
159*4882a593Smuzhiyun falsealm_cnt->cnt_sb_search_fail;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
162*4882a593Smuzhiyun /* hold cck counter */
163*4882a593Smuzhiyun rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
164*4882a593Smuzhiyun ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
165*4882a593Smuzhiyun falsealm_cnt->cnt_cck_fail = ret_value;
166*4882a593Smuzhiyun ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
167*4882a593Smuzhiyun falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
168*4882a593Smuzhiyun rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
169*4882a593Smuzhiyun } else {
170*4882a593Smuzhiyun falsealm_cnt->cnt_cck_fail = 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /* reset false alarm counter registers */
174*4882a593Smuzhiyun falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
175*4882a593Smuzhiyun falsealm_cnt->cnt_sb_search_fail +
176*4882a593Smuzhiyun falsealm_cnt->cnt_parity_fail +
177*4882a593Smuzhiyun falsealm_cnt->cnt_rate_illegal +
178*4882a593Smuzhiyun falsealm_cnt->cnt_crc8_fail +
179*4882a593Smuzhiyun falsealm_cnt->cnt_mcs_fail +
180*4882a593Smuzhiyun falsealm_cnt->cnt_cck_fail;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
183*4882a593Smuzhiyun /* update ofdm counter */
184*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
185*4882a593Smuzhiyun /* update page C counter */
186*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
187*4882a593Smuzhiyun /* update page D counter */
188*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
189*4882a593Smuzhiyun if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
190*4882a593Smuzhiyun /* reset cck counter */
191*4882a593Smuzhiyun rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
192*4882a593Smuzhiyun rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
193*4882a593Smuzhiyun /* enable cck counter */
194*4882a593Smuzhiyun rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
195*4882a593Smuzhiyun rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
198*4882a593Smuzhiyun "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n",
199*4882a593Smuzhiyun falsealm_cnt->cnt_fast_fsync_fail,
200*4882a593Smuzhiyun falsealm_cnt->cnt_sb_search_fail);
201*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
202*4882a593Smuzhiyun "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n",
203*4882a593Smuzhiyun falsealm_cnt->cnt_parity_fail,
204*4882a593Smuzhiyun falsealm_cnt->cnt_rate_illegal,
205*4882a593Smuzhiyun falsealm_cnt->cnt_crc8_fail,
206*4882a593Smuzhiyun falsealm_cnt->cnt_mcs_fail);
207*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
208*4882a593Smuzhiyun "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n",
209*4882a593Smuzhiyun falsealm_cnt->cnt_ofdm_fail,
210*4882a593Smuzhiyun falsealm_cnt->cnt_cck_fail,
211*4882a593Smuzhiyun falsealm_cnt->cnt_all);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
rtl92d_dm_find_minimum_rssi(struct ieee80211_hw * hw)214*4882a593Smuzhiyun static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
217*4882a593Smuzhiyun struct dig_t *de_digtable = &rtlpriv->dm_digtable;
218*4882a593Smuzhiyun struct rtl_mac *mac = rtl_mac(rtlpriv);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /* Determine the minimum RSSI */
221*4882a593Smuzhiyun if ((mac->link_state < MAC80211_LINKED) &&
222*4882a593Smuzhiyun (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
223*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm = 0;
224*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
225*4882a593Smuzhiyun "Not connected to any\n");
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun if (mac->link_state >= MAC80211_LINKED) {
228*4882a593Smuzhiyun if (mac->opmode == NL80211_IFTYPE_AP ||
229*4882a593Smuzhiyun mac->opmode == NL80211_IFTYPE_ADHOC) {
230*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm =
231*4882a593Smuzhiyun rtlpriv->dm.UNDEC_SM_PWDB;
232*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
233*4882a593Smuzhiyun "AP Client PWDB = 0x%lx\n",
234*4882a593Smuzhiyun rtlpriv->dm.UNDEC_SM_PWDB);
235*4882a593Smuzhiyun } else {
236*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm =
237*4882a593Smuzhiyun rtlpriv->dm.undec_sm_pwdb;
238*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
239*4882a593Smuzhiyun "STA Default Port PWDB = 0x%x\n",
240*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun } else {
243*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB;
244*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
245*4882a593Smuzhiyun "AP Ext Port or disconnect PWDB = 0x%x\n",
246*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n",
250*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm);
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw * hw)253*4882a593Smuzhiyun static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
256*4882a593Smuzhiyun struct dig_t *de_digtable = &rtlpriv->dm_digtable;
257*4882a593Smuzhiyun unsigned long flag = 0;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (de_digtable->cursta_cstate == DIG_STA_CONNECT) {
260*4882a593Smuzhiyun if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
261*4882a593Smuzhiyun if (de_digtable->min_undec_pwdb_for_dm <= 25)
262*4882a593Smuzhiyun de_digtable->cur_cck_pd_state =
263*4882a593Smuzhiyun CCK_PD_STAGE_LOWRSSI;
264*4882a593Smuzhiyun else
265*4882a593Smuzhiyun de_digtable->cur_cck_pd_state =
266*4882a593Smuzhiyun CCK_PD_STAGE_HIGHRSSI;
267*4882a593Smuzhiyun } else {
268*4882a593Smuzhiyun if (de_digtable->min_undec_pwdb_for_dm <= 20)
269*4882a593Smuzhiyun de_digtable->cur_cck_pd_state =
270*4882a593Smuzhiyun CCK_PD_STAGE_LOWRSSI;
271*4882a593Smuzhiyun else
272*4882a593Smuzhiyun de_digtable->cur_cck_pd_state =
273*4882a593Smuzhiyun CCK_PD_STAGE_HIGHRSSI;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun } else {
276*4882a593Smuzhiyun de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) {
279*4882a593Smuzhiyun if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
280*4882a593Smuzhiyun rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
281*4882a593Smuzhiyun rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
282*4882a593Smuzhiyun rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
283*4882a593Smuzhiyun } else {
284*4882a593Smuzhiyun rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
285*4882a593Smuzhiyun rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
286*4882a593Smuzhiyun rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n",
291*4882a593Smuzhiyun de_digtable->cursta_cstate == DIG_STA_CONNECT ?
292*4882a593Smuzhiyun "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT");
293*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n",
294*4882a593Smuzhiyun de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ?
295*4882a593Smuzhiyun "Low RSSI " : "High RSSI ");
296*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n",
297*4882a593Smuzhiyun IS_92D_SINGLEPHY(rtlpriv->rtlhal.version));
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
rtl92d_dm_write_dig(struct ieee80211_hw * hw)301*4882a593Smuzhiyun void rtl92d_dm_write_dig(struct ieee80211_hw *hw)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
304*4882a593Smuzhiyun struct dig_t *de_digtable = &rtlpriv->dm_digtable;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
307*4882a593Smuzhiyun "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
308*4882a593Smuzhiyun de_digtable->cur_igvalue, de_digtable->pre_igvalue,
309*4882a593Smuzhiyun de_digtable->back_val);
310*4882a593Smuzhiyun if (de_digtable->dig_enable_flag == false) {
311*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n");
312*4882a593Smuzhiyun de_digtable->pre_igvalue = 0x17;
313*4882a593Smuzhiyun return;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) {
316*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
317*4882a593Smuzhiyun de_digtable->cur_igvalue);
318*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
319*4882a593Smuzhiyun de_digtable->cur_igvalue);
320*4882a593Smuzhiyun de_digtable->pre_igvalue = de_digtable->cur_igvalue;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
rtl92d_early_mode_enabled(struct rtl_priv * rtlpriv)324*4882a593Smuzhiyun static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct dig_t *de_digtable = &rtlpriv->dm_digtable;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) &&
329*4882a593Smuzhiyun (rtlpriv->mac80211.vendor == PEER_CISCO)) {
330*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n");
331*4882a593Smuzhiyun if (de_digtable->last_min_undec_pwdb_for_dm >= 50
332*4882a593Smuzhiyun && de_digtable->min_undec_pwdb_for_dm < 50) {
333*4882a593Smuzhiyun rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00);
334*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
335*4882a593Smuzhiyun "Early Mode Off\n");
336*4882a593Smuzhiyun } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 &&
337*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm > 55) {
338*4882a593Smuzhiyun rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
339*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
340*4882a593Smuzhiyun "Early Mode On\n");
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) {
343*4882a593Smuzhiyun rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
344*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n");
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
rtl92d_dm_dig(struct ieee80211_hw * hw)348*4882a593Smuzhiyun static void rtl92d_dm_dig(struct ieee80211_hw *hw)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
351*4882a593Smuzhiyun struct dig_t *de_digtable = &rtlpriv->dm_digtable;
352*4882a593Smuzhiyun u8 value_igi = de_digtable->cur_igvalue;
353*4882a593Smuzhiyun struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n");
356*4882a593Smuzhiyun if (rtlpriv->rtlhal.earlymode_enable) {
357*4882a593Smuzhiyun rtl92d_early_mode_enabled(rtlpriv);
358*4882a593Smuzhiyun de_digtable->last_min_undec_pwdb_for_dm =
359*4882a593Smuzhiyun de_digtable->min_undec_pwdb_for_dm;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun if (!rtlpriv->dm.dm_initialgain_enable)
362*4882a593Smuzhiyun return;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun /* because we will send data pkt when scanning
365*4882a593Smuzhiyun * this will cause some ap like gear-3700 wep TP
366*4882a593Smuzhiyun * lower if we return here, this is the diff of
367*4882a593Smuzhiyun * mac80211 driver vs ieee80211 driver */
368*4882a593Smuzhiyun /* if (rtlpriv->mac80211.act_scanning)
369*4882a593Smuzhiyun * return; */
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun /* Not STA mode return tmp */
372*4882a593Smuzhiyun if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
373*4882a593Smuzhiyun return;
374*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n");
375*4882a593Smuzhiyun /* Decide the current status and if modify initial gain or not */
376*4882a593Smuzhiyun if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
377*4882a593Smuzhiyun de_digtable->cursta_cstate = DIG_STA_CONNECT;
378*4882a593Smuzhiyun else
379*4882a593Smuzhiyun de_digtable->cursta_cstate = DIG_STA_DISCONNECT;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /* adjust initial gain according to false alarm counter */
382*4882a593Smuzhiyun if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0)
383*4882a593Smuzhiyun value_igi--;
384*4882a593Smuzhiyun else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1)
385*4882a593Smuzhiyun value_igi += 0;
386*4882a593Smuzhiyun else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2)
387*4882a593Smuzhiyun value_igi++;
388*4882a593Smuzhiyun else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2)
389*4882a593Smuzhiyun value_igi += 2;
390*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
391*4882a593Smuzhiyun "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n",
392*4882a593Smuzhiyun de_digtable->large_fa_hit, de_digtable->forbidden_igi);
393*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
394*4882a593Smuzhiyun "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n",
395*4882a593Smuzhiyun de_digtable->recover_cnt, de_digtable->rx_gain_min);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun /* deal with abnormally large false alarm */
398*4882a593Smuzhiyun if (falsealm_cnt->cnt_all > 10000) {
399*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
400*4882a593Smuzhiyun "dm_DIG(): Abnormally false alarm case\n");
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun de_digtable->large_fa_hit++;
403*4882a593Smuzhiyun if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) {
404*4882a593Smuzhiyun de_digtable->forbidden_igi = de_digtable->cur_igvalue;
405*4882a593Smuzhiyun de_digtable->large_fa_hit = 1;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun if (de_digtable->large_fa_hit >= 3) {
408*4882a593Smuzhiyun if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX)
409*4882a593Smuzhiyun de_digtable->rx_gain_min = DM_DIG_MAX;
410*4882a593Smuzhiyun else
411*4882a593Smuzhiyun de_digtable->rx_gain_min =
412*4882a593Smuzhiyun (de_digtable->forbidden_igi + 1);
413*4882a593Smuzhiyun de_digtable->recover_cnt = 3600; /* 3600=2hr */
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun } else {
416*4882a593Smuzhiyun /* Recovery mechanism for IGI lower bound */
417*4882a593Smuzhiyun if (de_digtable->recover_cnt != 0) {
418*4882a593Smuzhiyun de_digtable->recover_cnt--;
419*4882a593Smuzhiyun } else {
420*4882a593Smuzhiyun if (de_digtable->large_fa_hit == 0) {
421*4882a593Smuzhiyun if ((de_digtable->forbidden_igi - 1) <
422*4882a593Smuzhiyun DM_DIG_FA_LOWER) {
423*4882a593Smuzhiyun de_digtable->forbidden_igi =
424*4882a593Smuzhiyun DM_DIG_FA_LOWER;
425*4882a593Smuzhiyun de_digtable->rx_gain_min =
426*4882a593Smuzhiyun DM_DIG_FA_LOWER;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun } else {
429*4882a593Smuzhiyun de_digtable->forbidden_igi--;
430*4882a593Smuzhiyun de_digtable->rx_gain_min =
431*4882a593Smuzhiyun (de_digtable->forbidden_igi + 1);
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun } else if (de_digtable->large_fa_hit == 3) {
434*4882a593Smuzhiyun de_digtable->large_fa_hit = 0;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
439*4882a593Smuzhiyun "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n",
440*4882a593Smuzhiyun de_digtable->large_fa_hit, de_digtable->forbidden_igi);
441*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
442*4882a593Smuzhiyun "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n",
443*4882a593Smuzhiyun de_digtable->recover_cnt, de_digtable->rx_gain_min);
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun if (value_igi > DM_DIG_MAX)
446*4882a593Smuzhiyun value_igi = DM_DIG_MAX;
447*4882a593Smuzhiyun else if (value_igi < de_digtable->rx_gain_min)
448*4882a593Smuzhiyun value_igi = de_digtable->rx_gain_min;
449*4882a593Smuzhiyun de_digtable->cur_igvalue = value_igi;
450*4882a593Smuzhiyun rtl92d_dm_write_dig(hw);
451*4882a593Smuzhiyun if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G)
452*4882a593Smuzhiyun rtl92d_dm_cck_packet_detection_thresh(hw);
453*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n");
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw * hw)456*4882a593Smuzhiyun static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun rtlpriv->dm.dynamic_txpower_enable = true;
461*4882a593Smuzhiyun rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
462*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
rtl92d_dm_dynamic_txpower(struct ieee80211_hw * hw)465*4882a593Smuzhiyun static void rtl92d_dm_dynamic_txpower(struct ieee80211_hw *hw)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
468*4882a593Smuzhiyun struct rtl_phy *rtlphy = &(rtlpriv->phy);
469*4882a593Smuzhiyun struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
470*4882a593Smuzhiyun struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
471*4882a593Smuzhiyun long undec_sm_pwdb;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun if ((!rtlpriv->dm.dynamic_txpower_enable)
474*4882a593Smuzhiyun || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
475*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
476*4882a593Smuzhiyun return;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun if ((mac->link_state < MAC80211_LINKED) &&
479*4882a593Smuzhiyun (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
480*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
481*4882a593Smuzhiyun "Not connected to any\n");
482*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
483*4882a593Smuzhiyun rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
484*4882a593Smuzhiyun return;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun if (mac->link_state >= MAC80211_LINKED) {
487*4882a593Smuzhiyun if (mac->opmode == NL80211_IFTYPE_ADHOC) {
488*4882a593Smuzhiyun undec_sm_pwdb =
489*4882a593Smuzhiyun rtlpriv->dm.UNDEC_SM_PWDB;
490*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
491*4882a593Smuzhiyun "IBSS Client PWDB = 0x%lx\n",
492*4882a593Smuzhiyun undec_sm_pwdb);
493*4882a593Smuzhiyun } else {
494*4882a593Smuzhiyun undec_sm_pwdb =
495*4882a593Smuzhiyun rtlpriv->dm.undec_sm_pwdb;
496*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
497*4882a593Smuzhiyun "STA Default Port PWDB = 0x%lx\n",
498*4882a593Smuzhiyun undec_sm_pwdb);
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun } else {
501*4882a593Smuzhiyun undec_sm_pwdb =
502*4882a593Smuzhiyun rtlpriv->dm.UNDEC_SM_PWDB;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
505*4882a593Smuzhiyun "AP Ext Port PWDB = 0x%lx\n",
506*4882a593Smuzhiyun undec_sm_pwdb);
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun if (rtlhal->current_bandtype == BAND_ON_5G) {
509*4882a593Smuzhiyun if (undec_sm_pwdb >= 0x33) {
510*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl =
511*4882a593Smuzhiyun TXHIGHPWRLEVEL_LEVEL2;
512*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
513*4882a593Smuzhiyun "5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n");
514*4882a593Smuzhiyun } else if ((undec_sm_pwdb < 0x33)
515*4882a593Smuzhiyun && (undec_sm_pwdb >= 0x2b)) {
516*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl =
517*4882a593Smuzhiyun TXHIGHPWRLEVEL_LEVEL1;
518*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
519*4882a593Smuzhiyun "5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n");
520*4882a593Smuzhiyun } else if (undec_sm_pwdb < 0x2b) {
521*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl =
522*4882a593Smuzhiyun TXHIGHPWRLEVEL_NORMAL;
523*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
524*4882a593Smuzhiyun "5G:TxHighPwrLevel_Normal\n");
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun } else {
527*4882a593Smuzhiyun if (undec_sm_pwdb >=
528*4882a593Smuzhiyun TX_POWER_NEAR_FIELD_THRESH_LVL2) {
529*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl =
530*4882a593Smuzhiyun TXHIGHPWRLEVEL_LEVEL2;
531*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
532*4882a593Smuzhiyun "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
533*4882a593Smuzhiyun } else
534*4882a593Smuzhiyun if ((undec_sm_pwdb <
535*4882a593Smuzhiyun (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3))
536*4882a593Smuzhiyun && (undec_sm_pwdb >=
537*4882a593Smuzhiyun TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl =
540*4882a593Smuzhiyun TXHIGHPWRLEVEL_LEVEL1;
541*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
542*4882a593Smuzhiyun "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
543*4882a593Smuzhiyun } else if (undec_sm_pwdb <
544*4882a593Smuzhiyun (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
545*4882a593Smuzhiyun rtlpriv->dm.dynamic_txhighpower_lvl =
546*4882a593Smuzhiyun TXHIGHPWRLEVEL_NORMAL;
547*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
548*4882a593Smuzhiyun "TXHIGHPWRLEVEL_NORMAL\n");
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
552*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
553*4882a593Smuzhiyun "PHY_SetTxPowerLevel8192S() Channel = %d\n",
554*4882a593Smuzhiyun rtlphy->current_channel);
555*4882a593Smuzhiyun rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
rtl92d_dm_pwdb_monitor(struct ieee80211_hw * hw)560*4882a593Smuzhiyun static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /* AP & ADHOC & MESH will return tmp */
565*4882a593Smuzhiyun if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
566*4882a593Smuzhiyun return;
567*4882a593Smuzhiyun /* Indicate Rx signal strength to FW. */
568*4882a593Smuzhiyun if (rtlpriv->dm.useramask) {
569*4882a593Smuzhiyun u32 temp = rtlpriv->dm.undec_sm_pwdb;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun temp <<= 16;
572*4882a593Smuzhiyun temp |= 0x100;
573*4882a593Smuzhiyun /* fw v12 cmdid 5:use max macid ,for nic ,
574*4882a593Smuzhiyun * default macid is 0 ,max macid is 1 */
575*4882a593Smuzhiyun rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp));
576*4882a593Smuzhiyun } else {
577*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0x4fe,
578*4882a593Smuzhiyun (u8) rtlpriv->dm.undec_sm_pwdb);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
rtl92d_dm_init_edca_turbo(struct ieee80211_hw * hw)582*4882a593Smuzhiyun void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun rtlpriv->dm.current_turbo_edca = false;
587*4882a593Smuzhiyun rtlpriv->dm.is_any_nonbepkts = false;
588*4882a593Smuzhiyun rtlpriv->dm.is_cur_rdlstate = false;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
rtl92d_dm_check_edca_turbo(struct ieee80211_hw * hw)591*4882a593Smuzhiyun static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
594*4882a593Smuzhiyun struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
595*4882a593Smuzhiyun static u64 last_txok_cnt;
596*4882a593Smuzhiyun static u64 last_rxok_cnt;
597*4882a593Smuzhiyun u64 cur_txok_cnt;
598*4882a593Smuzhiyun u64 cur_rxok_cnt;
599*4882a593Smuzhiyun u32 edca_be_ul = 0x5ea42b;
600*4882a593Smuzhiyun u32 edca_be_dl = 0x5ea42b;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun if (mac->link_state != MAC80211_LINKED) {
603*4882a593Smuzhiyun rtlpriv->dm.current_turbo_edca = false;
604*4882a593Smuzhiyun goto exit;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun /* Enable BEQ TxOP limit configuration in wireless G-mode. */
608*4882a593Smuzhiyun /* To check whether we shall force turn on TXOP configuration. */
609*4882a593Smuzhiyun if ((!rtlpriv->dm.disable_framebursting) &&
610*4882a593Smuzhiyun (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION ||
611*4882a593Smuzhiyun rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION ||
612*4882a593Smuzhiyun rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) {
613*4882a593Smuzhiyun /* Force TxOP limit to 0x005e for UL. */
614*4882a593Smuzhiyun if (!(edca_be_ul & 0xffff0000))
615*4882a593Smuzhiyun edca_be_ul |= 0x005e0000;
616*4882a593Smuzhiyun /* Force TxOP limit to 0x005e for DL. */
617*4882a593Smuzhiyun if (!(edca_be_dl & 0xffff0000))
618*4882a593Smuzhiyun edca_be_dl |= 0x005e0000;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun if ((!rtlpriv->dm.is_any_nonbepkts) &&
622*4882a593Smuzhiyun (!rtlpriv->dm.disable_framebursting)) {
623*4882a593Smuzhiyun cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
624*4882a593Smuzhiyun cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
625*4882a593Smuzhiyun if (cur_rxok_cnt > 4 * cur_txok_cnt) {
626*4882a593Smuzhiyun if (!rtlpriv->dm.is_cur_rdlstate ||
627*4882a593Smuzhiyun !rtlpriv->dm.current_turbo_edca) {
628*4882a593Smuzhiyun rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
629*4882a593Smuzhiyun edca_be_dl);
630*4882a593Smuzhiyun rtlpriv->dm.is_cur_rdlstate = true;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun } else {
633*4882a593Smuzhiyun if (rtlpriv->dm.is_cur_rdlstate ||
634*4882a593Smuzhiyun !rtlpriv->dm.current_turbo_edca) {
635*4882a593Smuzhiyun rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
636*4882a593Smuzhiyun edca_be_ul);
637*4882a593Smuzhiyun rtlpriv->dm.is_cur_rdlstate = false;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun rtlpriv->dm.current_turbo_edca = true;
641*4882a593Smuzhiyun } else {
642*4882a593Smuzhiyun if (rtlpriv->dm.current_turbo_edca) {
643*4882a593Smuzhiyun u8 tmp = AC0_BE;
644*4882a593Smuzhiyun rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
645*4882a593Smuzhiyun &tmp);
646*4882a593Smuzhiyun rtlpriv->dm.current_turbo_edca = false;
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun exit:
651*4882a593Smuzhiyun rtlpriv->dm.is_any_nonbepkts = false;
652*4882a593Smuzhiyun last_txok_cnt = rtlpriv->stats.txbytesunicast;
653*4882a593Smuzhiyun last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw * hw)656*4882a593Smuzhiyun static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
659*4882a593Smuzhiyun u8 index_mapping[RX_INDEX_MAPPING_NUM] = {
660*4882a593Smuzhiyun 0x0f, 0x0f, 0x0d, 0x0c, 0x0b,
661*4882a593Smuzhiyun 0x0a, 0x09, 0x08, 0x07, 0x06,
662*4882a593Smuzhiyun 0x05, 0x04, 0x04, 0x03, 0x02
663*4882a593Smuzhiyun };
664*4882a593Smuzhiyun int i;
665*4882a593Smuzhiyun u32 u4tmp;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter -
668*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_rxgain)]) << 12;
669*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
670*4882a593Smuzhiyun "===> Rx Gain %x\n", u4tmp);
671*4882a593Smuzhiyun for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
672*4882a593Smuzhiyun rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK,
673*4882a593Smuzhiyun (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
rtl92d_bandtype_2_4G(struct ieee80211_hw * hw,long * temp_cckg,u8 * cck_index_old)676*4882a593Smuzhiyun static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
677*4882a593Smuzhiyun u8 *cck_index_old)
678*4882a593Smuzhiyun {
679*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
680*4882a593Smuzhiyun int i;
681*4882a593Smuzhiyun unsigned long flag = 0;
682*4882a593Smuzhiyun long temp_cck;
683*4882a593Smuzhiyun const u8 *cckswing;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun /* Query CCK default setting From 0xa24 */
686*4882a593Smuzhiyun rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
687*4882a593Smuzhiyun temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
688*4882a593Smuzhiyun MASKDWORD) & MASKCCK;
689*4882a593Smuzhiyun rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
690*4882a593Smuzhiyun for (i = 0; i < CCK_TABLE_LENGTH; i++) {
691*4882a593Smuzhiyun if (rtlpriv->dm.cck_inch14)
692*4882a593Smuzhiyun cckswing = &cckswing_table_ch14[i][2];
693*4882a593Smuzhiyun else
694*4882a593Smuzhiyun cckswing = &cckswing_table_ch1ch13[i][2];
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) {
697*4882a593Smuzhiyun *cck_index_old = (u8)i;
698*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
699*4882a593Smuzhiyun "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
700*4882a593Smuzhiyun RCCK0_TXFILTER2, temp_cck,
701*4882a593Smuzhiyun *cck_index_old,
702*4882a593Smuzhiyun rtlpriv->dm.cck_inch14);
703*4882a593Smuzhiyun break;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun *temp_cckg = temp_cck;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
rtl92d_bandtype_5G(struct rtl_hal * rtlhal,u8 * ofdm_index,bool * internal_pa,u8 thermalvalue,u8 delta,u8 rf,struct rtl_efuse * rtlefuse,struct rtl_priv * rtlpriv,struct rtl_phy * rtlphy,const u8 index_mapping[5][INDEX_MAPPING_NUM],const u8 index_mapping_pa[8][INDEX_MAPPING_NUM])709*4882a593Smuzhiyun static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index,
710*4882a593Smuzhiyun bool *internal_pa, u8 thermalvalue, u8 delta,
711*4882a593Smuzhiyun u8 rf, struct rtl_efuse *rtlefuse,
712*4882a593Smuzhiyun struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy,
713*4882a593Smuzhiyun const u8 index_mapping[5][INDEX_MAPPING_NUM],
714*4882a593Smuzhiyun const u8 index_mapping_pa[8][INDEX_MAPPING_NUM])
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun int i;
717*4882a593Smuzhiyun u8 index;
718*4882a593Smuzhiyun u8 offset = 0;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun for (i = 0; i < rf; i++) {
721*4882a593Smuzhiyun if (rtlhal->macphymode == DUALMAC_DUALPHY &&
722*4882a593Smuzhiyun rtlhal->interfaceindex == 1) /* MAC 1 5G */
723*4882a593Smuzhiyun *internal_pa = rtlefuse->internal_pa_5g[1];
724*4882a593Smuzhiyun else
725*4882a593Smuzhiyun *internal_pa = rtlefuse->internal_pa_5g[i];
726*4882a593Smuzhiyun if (*internal_pa) {
727*4882a593Smuzhiyun if (rtlhal->interfaceindex == 1 || i == rf)
728*4882a593Smuzhiyun offset = 4;
729*4882a593Smuzhiyun else
730*4882a593Smuzhiyun offset = 0;
731*4882a593Smuzhiyun if (rtlphy->current_channel >= 100 &&
732*4882a593Smuzhiyun rtlphy->current_channel <= 165)
733*4882a593Smuzhiyun offset += 2;
734*4882a593Smuzhiyun } else {
735*4882a593Smuzhiyun if (rtlhal->interfaceindex == 1 || i == rf)
736*4882a593Smuzhiyun offset = 2;
737*4882a593Smuzhiyun else
738*4882a593Smuzhiyun offset = 0;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun if (thermalvalue > rtlefuse->eeprom_thermalmeter)
741*4882a593Smuzhiyun offset++;
742*4882a593Smuzhiyun if (*internal_pa) {
743*4882a593Smuzhiyun if (delta > INDEX_MAPPING_NUM - 1)
744*4882a593Smuzhiyun index = index_mapping_pa[offset]
745*4882a593Smuzhiyun [INDEX_MAPPING_NUM - 1];
746*4882a593Smuzhiyun else
747*4882a593Smuzhiyun index =
748*4882a593Smuzhiyun index_mapping_pa[offset][delta];
749*4882a593Smuzhiyun } else {
750*4882a593Smuzhiyun if (delta > INDEX_MAPPING_NUM - 1)
751*4882a593Smuzhiyun index =
752*4882a593Smuzhiyun index_mapping[offset][INDEX_MAPPING_NUM - 1];
753*4882a593Smuzhiyun else
754*4882a593Smuzhiyun index = index_mapping[offset][delta];
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
757*4882a593Smuzhiyun if (*internal_pa && thermalvalue > 0x12) {
758*4882a593Smuzhiyun ofdm_index[i] = rtlpriv->dm.ofdm_index[i] -
759*4882a593Smuzhiyun ((delta / 2) * 3 + (delta % 2));
760*4882a593Smuzhiyun } else {
761*4882a593Smuzhiyun ofdm_index[i] -= index;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun } else {
764*4882a593Smuzhiyun ofdm_index[i] += index;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw * hw)769*4882a593Smuzhiyun static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
770*4882a593Smuzhiyun struct ieee80211_hw *hw)
771*4882a593Smuzhiyun {
772*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
773*4882a593Smuzhiyun struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
774*4882a593Smuzhiyun struct rtl_phy *rtlphy = &(rtlpriv->phy);
775*4882a593Smuzhiyun struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
776*4882a593Smuzhiyun u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain;
777*4882a593Smuzhiyun u8 offset, thermalvalue_avg_count = 0;
778*4882a593Smuzhiyun u32 thermalvalue_avg = 0;
779*4882a593Smuzhiyun bool internal_pa = false;
780*4882a593Smuzhiyun long ele_a = 0, ele_d, temp_cck, val_x, value32;
781*4882a593Smuzhiyun long val_y, ele_c = 0;
782*4882a593Smuzhiyun u8 ofdm_index[2];
783*4882a593Smuzhiyun s8 cck_index = 0;
784*4882a593Smuzhiyun u8 ofdm_index_old[2] = {0, 0};
785*4882a593Smuzhiyun s8 cck_index_old = 0;
786*4882a593Smuzhiyun u8 index;
787*4882a593Smuzhiyun int i;
788*4882a593Smuzhiyun bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
789*4882a593Smuzhiyun u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf;
790*4882a593Smuzhiyun u8 indexforchannel =
791*4882a593Smuzhiyun rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel);
792*4882a593Smuzhiyun static const u8 index_mapping[5][INDEX_MAPPING_NUM] = {
793*4882a593Smuzhiyun /* 5G, path A/MAC 0, decrease power */
794*4882a593Smuzhiyun {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
795*4882a593Smuzhiyun /* 5G, path A/MAC 0, increase power */
796*4882a593Smuzhiyun {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
797*4882a593Smuzhiyun /* 5G, path B/MAC 1, decrease power */
798*4882a593Smuzhiyun {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
799*4882a593Smuzhiyun /* 5G, path B/MAC 1, increase power */
800*4882a593Smuzhiyun {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
801*4882a593Smuzhiyun /* 2.4G, for decreas power */
802*4882a593Smuzhiyun {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10},
803*4882a593Smuzhiyun };
804*4882a593Smuzhiyun static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = {
805*4882a593Smuzhiyun /* 5G, path A/MAC 0, ch36-64, decrease power */
806*4882a593Smuzhiyun {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
807*4882a593Smuzhiyun /* 5G, path A/MAC 0, ch36-64, increase power */
808*4882a593Smuzhiyun {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
809*4882a593Smuzhiyun /* 5G, path A/MAC 0, ch100-165, decrease power */
810*4882a593Smuzhiyun {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15},
811*4882a593Smuzhiyun /* 5G, path A/MAC 0, ch100-165, increase power */
812*4882a593Smuzhiyun {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
813*4882a593Smuzhiyun /* 5G, path B/MAC 1, ch36-64, decrease power */
814*4882a593Smuzhiyun {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
815*4882a593Smuzhiyun /* 5G, path B/MAC 1, ch36-64, increase power */
816*4882a593Smuzhiyun {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
817*4882a593Smuzhiyun /* 5G, path B/MAC 1, ch100-165, decrease power */
818*4882a593Smuzhiyun {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14},
819*4882a593Smuzhiyun /* 5G, path B/MAC 1, ch100-165, increase power */
820*4882a593Smuzhiyun {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
821*4882a593Smuzhiyun };
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun rtlpriv->dm.txpower_trackinginit = true;
824*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n");
825*4882a593Smuzhiyun thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800);
826*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
827*4882a593Smuzhiyun "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
828*4882a593Smuzhiyun thermalvalue,
829*4882a593Smuzhiyun rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter);
830*4882a593Smuzhiyun rtl92d_phy_ap_calibrate(hw, (thermalvalue -
831*4882a593Smuzhiyun rtlefuse->eeprom_thermalmeter));
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (!thermalvalue)
834*4882a593Smuzhiyun goto exit;
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun if (is2t)
837*4882a593Smuzhiyun rf = 2;
838*4882a593Smuzhiyun else
839*4882a593Smuzhiyun rf = 1;
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex)
842*4882a593Smuzhiyun goto old_index_done;
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D;
845*4882a593Smuzhiyun for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
846*4882a593Smuzhiyun if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
847*4882a593Smuzhiyun ofdm_index_old[0] = (u8)i;
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
850*4882a593Smuzhiyun "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
851*4882a593Smuzhiyun ROFDM0_XATXIQIMBALANCE,
852*4882a593Smuzhiyun ele_d, ofdm_index_old[0]);
853*4882a593Smuzhiyun break;
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun if (is2t) {
857*4882a593Smuzhiyun ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
858*4882a593Smuzhiyun MASKDWORD) & MASKOFDM_D;
859*4882a593Smuzhiyun for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
860*4882a593Smuzhiyun if (ele_d ==
861*4882a593Smuzhiyun (ofdmswing_table[i] & MASKOFDM_D)) {
862*4882a593Smuzhiyun ofdm_index_old[1] = (u8)i;
863*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING,
864*4882a593Smuzhiyun DBG_LOUD,
865*4882a593Smuzhiyun "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n",
866*4882a593Smuzhiyun ROFDM0_XBTXIQIMBALANCE, ele_d,
867*4882a593Smuzhiyun ofdm_index_old[1]);
868*4882a593Smuzhiyun break;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun if (rtlhal->current_bandtype == BAND_ON_2_4G) {
873*4882a593Smuzhiyun rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old);
874*4882a593Smuzhiyun } else {
875*4882a593Smuzhiyun temp_cck = 0x090e1317;
876*4882a593Smuzhiyun cck_index_old = 12;
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun if (!rtlpriv->dm.thermalvalue) {
880*4882a593Smuzhiyun rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter;
881*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_lck = thermalvalue;
882*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_iqk = thermalvalue;
883*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter;
884*4882a593Smuzhiyun for (i = 0; i < rf; i++)
885*4882a593Smuzhiyun rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
886*4882a593Smuzhiyun rtlpriv->dm.cck_index = cck_index_old;
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun if (rtlhal->reloadtxpowerindex) {
889*4882a593Smuzhiyun for (i = 0; i < rf; i++)
890*4882a593Smuzhiyun rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
891*4882a593Smuzhiyun rtlpriv->dm.cck_index = cck_index_old;
892*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
893*4882a593Smuzhiyun "reload ofdm index for band switch\n");
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun old_index_done:
896*4882a593Smuzhiyun for (i = 0; i < rf; i++)
897*4882a593Smuzhiyun ofdm_index[i] = rtlpriv->dm.ofdm_index[i];
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_avg
900*4882a593Smuzhiyun [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue;
901*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_avg_index++;
902*4882a593Smuzhiyun if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM)
903*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_avg_index = 0;
904*4882a593Smuzhiyun for (i = 0; i < AVG_THERMAL_NUM; i++) {
905*4882a593Smuzhiyun if (rtlpriv->dm.thermalvalue_avg[i]) {
906*4882a593Smuzhiyun thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i];
907*4882a593Smuzhiyun thermalvalue_avg_count++;
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun if (thermalvalue_avg_count)
911*4882a593Smuzhiyun thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count);
912*4882a593Smuzhiyun if (rtlhal->reloadtxpowerindex) {
913*4882a593Smuzhiyun delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
914*4882a593Smuzhiyun (thermalvalue - rtlefuse->eeprom_thermalmeter) :
915*4882a593Smuzhiyun (rtlefuse->eeprom_thermalmeter - thermalvalue);
916*4882a593Smuzhiyun rtlhal->reloadtxpowerindex = false;
917*4882a593Smuzhiyun rtlpriv->dm.done_txpower = false;
918*4882a593Smuzhiyun } else if (rtlpriv->dm.done_txpower) {
919*4882a593Smuzhiyun delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
920*4882a593Smuzhiyun (thermalvalue - rtlpriv->dm.thermalvalue) :
921*4882a593Smuzhiyun (rtlpriv->dm.thermalvalue - thermalvalue);
922*4882a593Smuzhiyun } else {
923*4882a593Smuzhiyun delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
924*4882a593Smuzhiyun (thermalvalue - rtlefuse->eeprom_thermalmeter) :
925*4882a593Smuzhiyun (rtlefuse->eeprom_thermalmeter - thermalvalue);
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
928*4882a593Smuzhiyun (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
929*4882a593Smuzhiyun (rtlpriv->dm.thermalvalue_lck - thermalvalue);
930*4882a593Smuzhiyun delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
931*4882a593Smuzhiyun (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
932*4882a593Smuzhiyun (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
933*4882a593Smuzhiyun delta_rxgain =
934*4882a593Smuzhiyun (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ?
935*4882a593Smuzhiyun (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) :
936*4882a593Smuzhiyun (rtlpriv->dm.thermalvalue_rxgain - thermalvalue);
937*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
938*4882a593Smuzhiyun "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
939*4882a593Smuzhiyun thermalvalue, rtlpriv->dm.thermalvalue,
940*4882a593Smuzhiyun rtlefuse->eeprom_thermalmeter, delta, delta_lck,
941*4882a593Smuzhiyun delta_iqk);
942*4882a593Smuzhiyun if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) {
943*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_lck = thermalvalue;
944*4882a593Smuzhiyun rtl92d_phy_lc_calibrate(hw);
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun if (delta == 0 || !rtlpriv->dm.txpower_track_control)
948*4882a593Smuzhiyun goto check_delta;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun rtlpriv->dm.done_txpower = true;
951*4882a593Smuzhiyun delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
952*4882a593Smuzhiyun (thermalvalue - rtlefuse->eeprom_thermalmeter) :
953*4882a593Smuzhiyun (rtlefuse->eeprom_thermalmeter - thermalvalue);
954*4882a593Smuzhiyun if (rtlhal->current_bandtype == BAND_ON_2_4G) {
955*4882a593Smuzhiyun offset = 4;
956*4882a593Smuzhiyun if (delta > INDEX_MAPPING_NUM - 1)
957*4882a593Smuzhiyun index = index_mapping[offset][INDEX_MAPPING_NUM - 1];
958*4882a593Smuzhiyun else
959*4882a593Smuzhiyun index = index_mapping[offset][delta];
960*4882a593Smuzhiyun if (thermalvalue > rtlpriv->dm.thermalvalue) {
961*4882a593Smuzhiyun for (i = 0; i < rf; i++)
962*4882a593Smuzhiyun ofdm_index[i] -= delta;
963*4882a593Smuzhiyun cck_index -= delta;
964*4882a593Smuzhiyun } else {
965*4882a593Smuzhiyun for (i = 0; i < rf; i++)
966*4882a593Smuzhiyun ofdm_index[i] += index;
967*4882a593Smuzhiyun cck_index += index;
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun } else if (rtlhal->current_bandtype == BAND_ON_5G) {
970*4882a593Smuzhiyun rtl92d_bandtype_5G(rtlhal, ofdm_index,
971*4882a593Smuzhiyun &internal_pa, thermalvalue,
972*4882a593Smuzhiyun delta, rf, rtlefuse, rtlpriv,
973*4882a593Smuzhiyun rtlphy, index_mapping,
974*4882a593Smuzhiyun index_mapping_internal_pa);
975*4882a593Smuzhiyun }
976*4882a593Smuzhiyun if (is2t) {
977*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
978*4882a593Smuzhiyun "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n",
979*4882a593Smuzhiyun rtlpriv->dm.ofdm_index[0],
980*4882a593Smuzhiyun rtlpriv->dm.ofdm_index[1],
981*4882a593Smuzhiyun rtlpriv->dm.cck_index);
982*4882a593Smuzhiyun } else {
983*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
984*4882a593Smuzhiyun "temp OFDM_A_index=0x%x,cck_index = 0x%x\n",
985*4882a593Smuzhiyun rtlpriv->dm.ofdm_index[0],
986*4882a593Smuzhiyun rtlpriv->dm.cck_index);
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun for (i = 0; i < rf; i++) {
989*4882a593Smuzhiyun if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1)
990*4882a593Smuzhiyun ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1;
991*4882a593Smuzhiyun else if (ofdm_index[i] < ofdm_min_index)
992*4882a593Smuzhiyun ofdm_index[i] = ofdm_min_index;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun if (rtlhal->current_bandtype == BAND_ON_2_4G) {
995*4882a593Smuzhiyun if (cck_index > CCK_TABLE_SIZE - 1) {
996*4882a593Smuzhiyun cck_index = CCK_TABLE_SIZE - 1;
997*4882a593Smuzhiyun } else if (internal_pa ||
998*4882a593Smuzhiyun rtlhal->current_bandtype == BAND_ON_2_4G) {
999*4882a593Smuzhiyun if (ofdm_index[i] < ofdm_min_index_internal_pa)
1000*4882a593Smuzhiyun ofdm_index[i] = ofdm_min_index_internal_pa;
1001*4882a593Smuzhiyun } else if (cck_index < 0) {
1002*4882a593Smuzhiyun cck_index = 0;
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun if (is2t) {
1006*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1007*4882a593Smuzhiyun "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n",
1008*4882a593Smuzhiyun ofdm_index[0], ofdm_index[1],
1009*4882a593Smuzhiyun cck_index);
1010*4882a593Smuzhiyun } else {
1011*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1012*4882a593Smuzhiyun "new OFDM_A_index=0x%x,cck_index = 0x%x\n",
1013*4882a593Smuzhiyun ofdm_index[0], cck_index);
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
1016*4882a593Smuzhiyun val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0];
1017*4882a593Smuzhiyun val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1];
1018*4882a593Smuzhiyun if (val_x != 0) {
1019*4882a593Smuzhiyun if ((val_x & 0x00000200) != 0)
1020*4882a593Smuzhiyun val_x = val_x | 0xFFFFFC00;
1021*4882a593Smuzhiyun ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun /* new element C = element D x Y */
1024*4882a593Smuzhiyun if ((val_y & 0x00000200) != 0)
1025*4882a593Smuzhiyun val_y = val_y | 0xFFFFFC00;
1026*4882a593Smuzhiyun ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun /* write new elements A, C, D to regC80 and
1029*4882a593Smuzhiyun * regC94, element B is always 0
1030*4882a593Smuzhiyun */
1031*4882a593Smuzhiyun value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a;
1032*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1033*4882a593Smuzhiyun MASKDWORD, value32);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun value32 = (ele_c & 0x000003C0) >> 6;
1036*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
1037*4882a593Smuzhiyun value32);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun value32 = ((val_x * ele_d) >> 7) & 0x01;
1040*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
1041*4882a593Smuzhiyun value32);
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun } else {
1044*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1045*4882a593Smuzhiyun MASKDWORD,
1046*4882a593Smuzhiyun ofdmswing_table[(u8)ofdm_index[0]]);
1047*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
1048*4882a593Smuzhiyun 0x00);
1049*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1050*4882a593Smuzhiyun BIT(24), 0x00);
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1054*4882a593Smuzhiyun "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n",
1055*4882a593Smuzhiyun rtlhal->interfaceindex,
1056*4882a593Smuzhiyun val_x, val_y, ele_a, ele_c, ele_d,
1057*4882a593Smuzhiyun val_x, val_y);
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun if (cck_index >= CCK_TABLE_SIZE)
1060*4882a593Smuzhiyun cck_index = CCK_TABLE_SIZE - 1;
1061*4882a593Smuzhiyun if (cck_index < 0)
1062*4882a593Smuzhiyun cck_index = 0;
1063*4882a593Smuzhiyun if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1064*4882a593Smuzhiyun /* Adjust CCK according to IQK result */
1065*4882a593Smuzhiyun if (!rtlpriv->dm.cck_inch14) {
1066*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa22,
1067*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][0]);
1068*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa23,
1069*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][1]);
1070*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa24,
1071*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][2]);
1072*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa25,
1073*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][3]);
1074*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa26,
1075*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][4]);
1076*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa27,
1077*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][5]);
1078*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa28,
1079*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][6]);
1080*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa29,
1081*4882a593Smuzhiyun cckswing_table_ch1ch13[cck_index][7]);
1082*4882a593Smuzhiyun } else {
1083*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa22,
1084*4882a593Smuzhiyun cckswing_table_ch14[cck_index][0]);
1085*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa23,
1086*4882a593Smuzhiyun cckswing_table_ch14[cck_index][1]);
1087*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa24,
1088*4882a593Smuzhiyun cckswing_table_ch14[cck_index][2]);
1089*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa25,
1090*4882a593Smuzhiyun cckswing_table_ch14[cck_index][3]);
1091*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa26,
1092*4882a593Smuzhiyun cckswing_table_ch14[cck_index][4]);
1093*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa27,
1094*4882a593Smuzhiyun cckswing_table_ch14[cck_index][5]);
1095*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa28,
1096*4882a593Smuzhiyun cckswing_table_ch14[cck_index][6]);
1097*4882a593Smuzhiyun rtl_write_byte(rtlpriv, 0xa29,
1098*4882a593Smuzhiyun cckswing_table_ch14[cck_index][7]);
1099*4882a593Smuzhiyun }
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun if (is2t) {
1102*4882a593Smuzhiyun ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22;
1103*4882a593Smuzhiyun val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4];
1104*4882a593Smuzhiyun val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5];
1105*4882a593Smuzhiyun if (val_x != 0) {
1106*4882a593Smuzhiyun if ((val_x & 0x00000200) != 0)
1107*4882a593Smuzhiyun /* consider minus */
1108*4882a593Smuzhiyun val_x = val_x | 0xFFFFFC00;
1109*4882a593Smuzhiyun ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
1110*4882a593Smuzhiyun /* new element C = element D x Y */
1111*4882a593Smuzhiyun if ((val_y & 0x00000200) != 0)
1112*4882a593Smuzhiyun val_y = val_y | 0xFFFFFC00;
1113*4882a593Smuzhiyun ele_c = ((val_y * ele_d) >> 8) & 0x00003FF;
1114*4882a593Smuzhiyun /* write new elements A, C, D to regC88
1115*4882a593Smuzhiyun * and regC9C, element B is always 0
1116*4882a593Smuzhiyun */
1117*4882a593Smuzhiyun value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a;
1118*4882a593Smuzhiyun rtl_set_bbreg(hw,
1119*4882a593Smuzhiyun ROFDM0_XBTXIQIMBALANCE,
1120*4882a593Smuzhiyun MASKDWORD, value32);
1121*4882a593Smuzhiyun value32 = (ele_c & 0x000003C0) >> 6;
1122*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1123*4882a593Smuzhiyun MASKH4BITS, value32);
1124*4882a593Smuzhiyun value32 = ((val_x * ele_d) >> 7) & 0x01;
1125*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1126*4882a593Smuzhiyun BIT(28), value32);
1127*4882a593Smuzhiyun } else {
1128*4882a593Smuzhiyun rtl_set_bbreg(hw,
1129*4882a593Smuzhiyun ROFDM0_XBTXIQIMBALANCE,
1130*4882a593Smuzhiyun MASKDWORD,
1131*4882a593Smuzhiyun ofdmswing_table[ofdm_index[1]]);
1132*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1133*4882a593Smuzhiyun MASKH4BITS, 0x00);
1134*4882a593Smuzhiyun rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1135*4882a593Smuzhiyun BIT(28), 0x00);
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1138*4882a593Smuzhiyun "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n",
1139*4882a593Smuzhiyun val_x, val_y, ele_a, ele_c,
1140*4882a593Smuzhiyun ele_d, val_x, val_y);
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1143*4882a593Smuzhiyun "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n",
1144*4882a593Smuzhiyun rtl_get_bbreg(hw, 0xc80, MASKDWORD),
1145*4882a593Smuzhiyun rtl_get_bbreg(hw, 0xc94, MASKDWORD),
1146*4882a593Smuzhiyun rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
1147*4882a593Smuzhiyun RFREG_OFFSET_MASK));
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun check_delta:
1150*4882a593Smuzhiyun if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) {
1151*4882a593Smuzhiyun rtl92d_phy_reset_iqk_result(hw);
1152*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1153*4882a593Smuzhiyun rtl92d_phy_iq_calibrate(hw);
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G &&
1156*4882a593Smuzhiyun thermalvalue <= rtlefuse->eeprom_thermalmeter) {
1157*4882a593Smuzhiyun rtlpriv->dm.thermalvalue_rxgain = thermalvalue;
1158*4882a593Smuzhiyun rtl92d_dm_rxgain_tracking_thermalmeter(hw);
1159*4882a593Smuzhiyun }
1160*4882a593Smuzhiyun if (rtlpriv->dm.txpower_track_control)
1161*4882a593Smuzhiyun rtlpriv->dm.thermalvalue = thermalvalue;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun exit:
1164*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun
rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw * hw)1167*4882a593Smuzhiyun static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1168*4882a593Smuzhiyun {
1169*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun rtlpriv->dm.txpower_tracking = true;
1172*4882a593Smuzhiyun rtlpriv->dm.txpower_trackinginit = false;
1173*4882a593Smuzhiyun rtlpriv->dm.txpower_track_control = true;
1174*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1175*4882a593Smuzhiyun "pMgntInfo->txpower_tracking = %d\n",
1176*4882a593Smuzhiyun rtlpriv->dm.txpower_tracking);
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun
rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw * hw)1179*4882a593Smuzhiyun void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw)
1180*4882a593Smuzhiyun {
1181*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun if (!rtlpriv->dm.txpower_tracking)
1184*4882a593Smuzhiyun return;
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun if (!rtlpriv->dm.tm_trigger) {
1187*4882a593Smuzhiyun rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) |
1188*4882a593Smuzhiyun BIT(16), 0x03);
1189*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1190*4882a593Smuzhiyun "Trigger 92S Thermal Meter!!\n");
1191*4882a593Smuzhiyun rtlpriv->dm.tm_trigger = 1;
1192*4882a593Smuzhiyun return;
1193*4882a593Smuzhiyun } else {
1194*4882a593Smuzhiyun rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1195*4882a593Smuzhiyun "Schedule TxPowerTracking direct call!!\n");
1196*4882a593Smuzhiyun rtl92d_dm_txpower_tracking_callback_thermalmeter(hw);
1197*4882a593Smuzhiyun rtlpriv->dm.tm_trigger = 0;
1198*4882a593Smuzhiyun }
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw * hw)1201*4882a593Smuzhiyun void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
1204*4882a593Smuzhiyun struct rate_adaptive *ra = &(rtlpriv->ra);
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun ra->ratr_state = DM_RATR_STA_INIT;
1207*4882a593Smuzhiyun ra->pre_ratr_state = DM_RATR_STA_INIT;
1208*4882a593Smuzhiyun if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1209*4882a593Smuzhiyun rtlpriv->dm.useramask = true;
1210*4882a593Smuzhiyun else
1211*4882a593Smuzhiyun rtlpriv->dm.useramask = false;
1212*4882a593Smuzhiyun }
1213*4882a593Smuzhiyun
rtl92d_dm_init(struct ieee80211_hw * hw)1214*4882a593Smuzhiyun void rtl92d_dm_init(struct ieee80211_hw *hw)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1219*4882a593Smuzhiyun rtl_dm_diginit(hw, 0x20);
1220*4882a593Smuzhiyun rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER;
1221*4882a593Smuzhiyun rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER;
1222*4882a593Smuzhiyun rtl92d_dm_init_dynamic_txpower(hw);
1223*4882a593Smuzhiyun rtl92d_dm_init_edca_turbo(hw);
1224*4882a593Smuzhiyun rtl92d_dm_init_rate_adaptive_mask(hw);
1225*4882a593Smuzhiyun rtl92d_dm_initialize_txpower_tracking(hw);
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun
rtl92d_dm_watchdog(struct ieee80211_hw * hw)1228*4882a593Smuzhiyun void rtl92d_dm_watchdog(struct ieee80211_hw *hw)
1229*4882a593Smuzhiyun {
1230*4882a593Smuzhiyun struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1231*4882a593Smuzhiyun bool fw_current_inpsmode = false;
1232*4882a593Smuzhiyun bool fwps_awake = true;
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun /* 1. RF is OFF. (No need to do DM.)
1235*4882a593Smuzhiyun * 2. Fw is under power saving mode for FwLPS.
1236*4882a593Smuzhiyun * (Prevent from SW/FW I/O racing.)
1237*4882a593Smuzhiyun * 3. IPS workitem is scheduled. (Prevent from IPS sequence
1238*4882a593Smuzhiyun * to be swapped with DM.
1239*4882a593Smuzhiyun * 4. RFChangeInProgress is TRUE.
1240*4882a593Smuzhiyun * (Prevent from broken by IPS/HW/SW Rf off.) */
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1243*4882a593Smuzhiyun fwps_awake) && (!ppsc->rfchange_inprogress)) {
1244*4882a593Smuzhiyun rtl92d_dm_pwdb_monitor(hw);
1245*4882a593Smuzhiyun rtl92d_dm_false_alarm_counter_statistics(hw);
1246*4882a593Smuzhiyun rtl92d_dm_find_minimum_rssi(hw);
1247*4882a593Smuzhiyun rtl92d_dm_dig(hw);
1248*4882a593Smuzhiyun /* rtl92d_dm_dynamic_bb_powersaving(hw); */
1249*4882a593Smuzhiyun rtl92d_dm_dynamic_txpower(hw);
1250*4882a593Smuzhiyun /* rtl92d_dm_check_txpower_tracking_thermal_meter(hw); */
1251*4882a593Smuzhiyun /* rtl92d_dm_refresh_rate_adaptive_mask(hw); */
1252*4882a593Smuzhiyun /* rtl92d_dm_interrupt_migration(hw); */
1253*4882a593Smuzhiyun rtl92d_dm_check_edca_turbo(hw);
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun }
1256