1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92CU_TABLE__H_ 5*4882a593Smuzhiyun #define __RTL92CU_TABLE__H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/types.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RTL8192CUPHY_REG_2TARRAY_LENGTH 374 10*4882a593Smuzhiyun extern u32 RTL8192CUPHY_REG_2TARRAY[RTL8192CUPHY_REG_2TARRAY_LENGTH]; 11*4882a593Smuzhiyun #define RTL8192CUPHY_REG_1TARRAY_LENGTH 374 12*4882a593Smuzhiyun extern u32 RTL8192CUPHY_REG_1TARRAY[RTL8192CUPHY_REG_1TARRAY_LENGTH]; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define RTL8192CUPHY_REG_ARRAY_PGLENGTH 336 15*4882a593Smuzhiyun extern u32 RTL8192CUPHY_REG_ARRAY_PG[RTL8192CUPHY_REG_ARRAY_PGLENGTH]; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RTL8192CURADIOA_2TARRAYLENGTH 282 18*4882a593Smuzhiyun extern u32 RTL8192CURADIOA_2TARRAY[RTL8192CURADIOA_2TARRAYLENGTH]; 19*4882a593Smuzhiyun #define RTL8192CURADIOB_2TARRAYLENGTH 78 20*4882a593Smuzhiyun extern u32 RTL8192CU_RADIOB_2TARRAY[RTL8192CURADIOB_2TARRAYLENGTH]; 21*4882a593Smuzhiyun #define RTL8192CURADIOA_1TARRAYLENGTH 282 22*4882a593Smuzhiyun extern u32 RTL8192CU_RADIOA_1TARRAY[RTL8192CURADIOA_1TARRAYLENGTH]; 23*4882a593Smuzhiyun #define RTL8192CURADIOB_1TARRAYLENGTH 1 24*4882a593Smuzhiyun extern u32 RTL8192CU_RADIOB_1TARRAY[RTL8192CURADIOB_1TARRAYLENGTH]; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define RTL8192CUMAC_2T_ARRAYLENGTH 172 27*4882a593Smuzhiyun extern u32 RTL8192CUMAC_2T_ARRAY[RTL8192CUMAC_2T_ARRAYLENGTH]; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define RTL8192CUAGCTAB_2TARRAYLENGTH 320 30*4882a593Smuzhiyun extern u32 RTL8192CUAGCTAB_2TARRAY[RTL8192CUAGCTAB_2TARRAYLENGTH]; 31*4882a593Smuzhiyun #define RTL8192CUAGCTAB_1TARRAYLENGTH 320 32*4882a593Smuzhiyun extern u32 RTL8192CUAGCTAB_1TARRAY[RTL8192CUAGCTAB_1TARRAYLENGTH]; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define RTL8192CUPHY_REG_1T_HPARRAYLENGTH 378 35*4882a593Smuzhiyun extern u32 RTL8192CUPHY_REG_1T_HPARRAY[RTL8192CUPHY_REG_1T_HPARRAYLENGTH]; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define RTL8192CUPHY_REG_ARRAY_PG_HPLENGTH 336 38*4882a593Smuzhiyun extern u32 RTL8192CUPHY_REG_ARRAY_PG_HP[RTL8192CUPHY_REG_ARRAY_PG_HPLENGTH]; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define RTL8192CURADIOA_1T_HPARRAYLENGTH 282 41*4882a593Smuzhiyun extern u32 RTL8192CURADIOA_1T_HPARRAY[RTL8192CURADIOA_1T_HPARRAYLENGTH]; 42*4882a593Smuzhiyun #define RTL8192CUAGCTAB_1T_HPARRAYLENGTH 320 43*4882a593Smuzhiyun extern u32 RTL8192CUAGCTAB_1T_HPARRAY[RTL8192CUAGCTAB_1T_HPARRAYLENGTH]; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46