xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/mac.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2009-2012  Realtek Corporation.*/
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include "../wifi.h"
5*4882a593Smuzhiyun #include "../pci.h"
6*4882a593Smuzhiyun #include "../usb.h"
7*4882a593Smuzhiyun #include "../ps.h"
8*4882a593Smuzhiyun #include "../cam.h"
9*4882a593Smuzhiyun #include "../stats.h"
10*4882a593Smuzhiyun #include "reg.h"
11*4882a593Smuzhiyun #include "def.h"
12*4882a593Smuzhiyun #include "phy.h"
13*4882a593Smuzhiyun #include "rf.h"
14*4882a593Smuzhiyun #include "dm.h"
15*4882a593Smuzhiyun #include "mac.h"
16*4882a593Smuzhiyun #include "trx.h"
17*4882a593Smuzhiyun #include "../rtl8192c/fw_common.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* macro to shorten lines */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define LINK_Q	ui_link_quality
24*4882a593Smuzhiyun #define RX_EVM	rx_evm_percentage
25*4882a593Smuzhiyun #define RX_SIGQ	rx_mimo_sig_qual
26*4882a593Smuzhiyun 
rtl92c_read_chip_version(struct ieee80211_hw * hw)27*4882a593Smuzhiyun void rtl92c_read_chip_version(struct ieee80211_hw *hw)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
30*4882a593Smuzhiyun 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
31*4882a593Smuzhiyun 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
32*4882a593Smuzhiyun 	enum version_8192c chip_version = VERSION_UNKNOWN;
33*4882a593Smuzhiyun 	const char *versionid;
34*4882a593Smuzhiyun 	u32 value32;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
37*4882a593Smuzhiyun 	if (value32 & TRP_VAUX_EN) {
38*4882a593Smuzhiyun 		chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
39*4882a593Smuzhiyun 			       VERSION_TEST_CHIP_88C;
40*4882a593Smuzhiyun 	} else {
41*4882a593Smuzhiyun 		/* Normal mass production chip. */
42*4882a593Smuzhiyun 		chip_version = NORMAL_CHIP;
43*4882a593Smuzhiyun 		chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
44*4882a593Smuzhiyun 		chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
45*4882a593Smuzhiyun 		if (IS_VENDOR_UMC(chip_version))
46*4882a593Smuzhiyun 			chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
47*4882a593Smuzhiyun 					 CHIP_VENDOR_UMC_B_CUT : 0);
48*4882a593Smuzhiyun 		if (IS_92C_SERIAL(chip_version)) {
49*4882a593Smuzhiyun 			value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
50*4882a593Smuzhiyun 			chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
51*4882a593Smuzhiyun 				 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
52*4882a593Smuzhiyun 		}
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 	rtlhal->version  = (enum version_8192c)chip_version;
55*4882a593Smuzhiyun 	pr_info("Chip version 0x%x\n", chip_version);
56*4882a593Smuzhiyun 	switch (rtlhal->version) {
57*4882a593Smuzhiyun 	case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
58*4882a593Smuzhiyun 		versionid = "NORMAL_B_CHIP_92C";
59*4882a593Smuzhiyun 		break;
60*4882a593Smuzhiyun 	case VERSION_NORMAL_TSMC_CHIP_92C:
61*4882a593Smuzhiyun 		versionid = "NORMAL_TSMC_CHIP_92C";
62*4882a593Smuzhiyun 		break;
63*4882a593Smuzhiyun 	case VERSION_NORMAL_TSMC_CHIP_88C:
64*4882a593Smuzhiyun 		versionid = "NORMAL_TSMC_CHIP_88C";
65*4882a593Smuzhiyun 		break;
66*4882a593Smuzhiyun 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
67*4882a593Smuzhiyun 		versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
68*4882a593Smuzhiyun 		break;
69*4882a593Smuzhiyun 	case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
70*4882a593Smuzhiyun 		versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
71*4882a593Smuzhiyun 		break;
72*4882a593Smuzhiyun 	case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
73*4882a593Smuzhiyun 		versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
74*4882a593Smuzhiyun 		break;
75*4882a593Smuzhiyun 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
76*4882a593Smuzhiyun 		versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
77*4882a593Smuzhiyun 		break;
78*4882a593Smuzhiyun 	case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
79*4882a593Smuzhiyun 		versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
80*4882a593Smuzhiyun 		break;
81*4882a593Smuzhiyun 	case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
82*4882a593Smuzhiyun 		versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
83*4882a593Smuzhiyun 		break;
84*4882a593Smuzhiyun 	case VERSION_TEST_CHIP_92C:
85*4882a593Smuzhiyun 		versionid = "TEST_CHIP_92C";
86*4882a593Smuzhiyun 		break;
87*4882a593Smuzhiyun 	case VERSION_TEST_CHIP_88C:
88*4882a593Smuzhiyun 		versionid = "TEST_CHIP_88C";
89*4882a593Smuzhiyun 		break;
90*4882a593Smuzhiyun 	default:
91*4882a593Smuzhiyun 		versionid = "UNKNOWN";
92*4882a593Smuzhiyun 		break;
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
95*4882a593Smuzhiyun 		"Chip Version ID: %s\n", versionid);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	if (IS_92C_SERIAL(rtlhal->version))
98*4882a593Smuzhiyun 		rtlphy->rf_type =
99*4882a593Smuzhiyun 			 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
100*4882a593Smuzhiyun 	else
101*4882a593Smuzhiyun 		rtlphy->rf_type = RF_1T1R;
102*4882a593Smuzhiyun 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
103*4882a593Smuzhiyun 		"Chip RF Type: %s\n",
104*4882a593Smuzhiyun 		rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
105*4882a593Smuzhiyun 	if (get_rf_type(rtlphy) == RF_1T1R)
106*4882a593Smuzhiyun 		rtlpriv->dm.rfpath_rxenable[0] = true;
107*4882a593Smuzhiyun 	else
108*4882a593Smuzhiyun 		rtlpriv->dm.rfpath_rxenable[0] =
109*4882a593Smuzhiyun 		    rtlpriv->dm.rfpath_rxenable[1] = true;
110*4882a593Smuzhiyun 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
111*4882a593Smuzhiyun 		rtlhal->version);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /**
115*4882a593Smuzhiyun  * writeLLT - LLT table write access
116*4882a593Smuzhiyun  * @io: io callback
117*4882a593Smuzhiyun  * @address: LLT logical address.
118*4882a593Smuzhiyun  * @data: LLT data content
119*4882a593Smuzhiyun  *
120*4882a593Smuzhiyun  * Realtek hardware access function.
121*4882a593Smuzhiyun  *
122*4882a593Smuzhiyun  */
rtl92c_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)123*4882a593Smuzhiyun bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
126*4882a593Smuzhiyun 	bool status = true;
127*4882a593Smuzhiyun 	long count = 0;
128*4882a593Smuzhiyun 	u32 value = _LLT_INIT_ADDR(address) |
129*4882a593Smuzhiyun 	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
132*4882a593Smuzhiyun 	do {
133*4882a593Smuzhiyun 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
134*4882a593Smuzhiyun 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
135*4882a593Smuzhiyun 			break;
136*4882a593Smuzhiyun 		if (count > POLLING_LLT_THRESHOLD) {
137*4882a593Smuzhiyun 			pr_err("Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
138*4882a593Smuzhiyun 			       address, _LLT_OP_VALUE(value));
139*4882a593Smuzhiyun 			status = false;
140*4882a593Smuzhiyun 			break;
141*4882a593Smuzhiyun 		}
142*4882a593Smuzhiyun 	} while (++count);
143*4882a593Smuzhiyun 	return status;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /**
147*4882a593Smuzhiyun  * rtl92c_init_LLT_table - Init LLT table
148*4882a593Smuzhiyun  * @io: io callback
149*4882a593Smuzhiyun  * @boundary:
150*4882a593Smuzhiyun  *
151*4882a593Smuzhiyun  * Realtek hardware access function.
152*4882a593Smuzhiyun  *
153*4882a593Smuzhiyun  */
rtl92c_init_llt_table(struct ieee80211_hw * hw,u32 boundary)154*4882a593Smuzhiyun bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	bool rst = true;
157*4882a593Smuzhiyun 	u32	i;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	for (i = 0; i < (boundary - 1); i++) {
160*4882a593Smuzhiyun 		rst = rtl92c_llt_write(hw, i , i + 1);
161*4882a593Smuzhiyun 		if (!rst) {
162*4882a593Smuzhiyun 			pr_err("===> %s #1 fail\n", __func__);
163*4882a593Smuzhiyun 			return rst;
164*4882a593Smuzhiyun 		}
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 	/* end of list */
167*4882a593Smuzhiyun 	rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
168*4882a593Smuzhiyun 	if (!rst) {
169*4882a593Smuzhiyun 		pr_err("===> %s #2 fail\n", __func__);
170*4882a593Smuzhiyun 		return rst;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 	/* Make the other pages as ring buffer
173*4882a593Smuzhiyun 	 * This ring buffer is used as beacon buffer if we config this MAC
174*4882a593Smuzhiyun 	 *  as two MAC transfer.
175*4882a593Smuzhiyun 	 * Otherwise used as local loopback buffer.
176*4882a593Smuzhiyun 	 */
177*4882a593Smuzhiyun 	for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
178*4882a593Smuzhiyun 		rst = rtl92c_llt_write(hw, i, (i + 1));
179*4882a593Smuzhiyun 		if (!rst) {
180*4882a593Smuzhiyun 			pr_err("===> %s #3 fail\n", __func__);
181*4882a593Smuzhiyun 			return rst;
182*4882a593Smuzhiyun 		}
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 	/* Let last entry point to the start entry of ring buffer */
185*4882a593Smuzhiyun 	rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
186*4882a593Smuzhiyun 	if (!rst) {
187*4882a593Smuzhiyun 		pr_err("===> %s #4 fail\n", __func__);
188*4882a593Smuzhiyun 		return rst;
189*4882a593Smuzhiyun 	}
190*4882a593Smuzhiyun 	return rst;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
rtl92c_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)193*4882a593Smuzhiyun void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
194*4882a593Smuzhiyun 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
195*4882a593Smuzhiyun 		     bool is_wepkey, bool clear_all)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
198*4882a593Smuzhiyun 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
199*4882a593Smuzhiyun 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
200*4882a593Smuzhiyun 	u8 *macaddr = p_macaddr;
201*4882a593Smuzhiyun 	u32 entry_id = 0;
202*4882a593Smuzhiyun 	bool is_pairwise = false;
203*4882a593Smuzhiyun 	static u8 cam_const_addr[4][6] = {
204*4882a593Smuzhiyun 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
205*4882a593Smuzhiyun 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
206*4882a593Smuzhiyun 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
207*4882a593Smuzhiyun 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
208*4882a593Smuzhiyun 	};
209*4882a593Smuzhiyun 	static u8 cam_const_broad[] = {
210*4882a593Smuzhiyun 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
211*4882a593Smuzhiyun 	};
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	if (clear_all) {
214*4882a593Smuzhiyun 		u8 idx = 0;
215*4882a593Smuzhiyun 		u8 cam_offset = 0;
216*4882a593Smuzhiyun 		u8 clear_number = 5;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
219*4882a593Smuzhiyun 		for (idx = 0; idx < clear_number; idx++) {
220*4882a593Smuzhiyun 			rtl_cam_mark_invalid(hw, cam_offset + idx);
221*4882a593Smuzhiyun 			rtl_cam_empty_entry(hw, cam_offset + idx);
222*4882a593Smuzhiyun 			if (idx < 5) {
223*4882a593Smuzhiyun 				memset(rtlpriv->sec.key_buf[idx], 0,
224*4882a593Smuzhiyun 				       MAX_KEY_LEN);
225*4882a593Smuzhiyun 				rtlpriv->sec.key_len[idx] = 0;
226*4882a593Smuzhiyun 			}
227*4882a593Smuzhiyun 		}
228*4882a593Smuzhiyun 	} else {
229*4882a593Smuzhiyun 		switch (enc_algo) {
230*4882a593Smuzhiyun 		case WEP40_ENCRYPTION:
231*4882a593Smuzhiyun 			enc_algo = CAM_WEP40;
232*4882a593Smuzhiyun 			break;
233*4882a593Smuzhiyun 		case WEP104_ENCRYPTION:
234*4882a593Smuzhiyun 			enc_algo = CAM_WEP104;
235*4882a593Smuzhiyun 			break;
236*4882a593Smuzhiyun 		case TKIP_ENCRYPTION:
237*4882a593Smuzhiyun 			enc_algo = CAM_TKIP;
238*4882a593Smuzhiyun 			break;
239*4882a593Smuzhiyun 		case AESCCMP_ENCRYPTION:
240*4882a593Smuzhiyun 			enc_algo = CAM_AES;
241*4882a593Smuzhiyun 			break;
242*4882a593Smuzhiyun 		default:
243*4882a593Smuzhiyun 			pr_err("illegal switch case\n");
244*4882a593Smuzhiyun 			enc_algo = CAM_TKIP;
245*4882a593Smuzhiyun 			break;
246*4882a593Smuzhiyun 		}
247*4882a593Smuzhiyun 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
248*4882a593Smuzhiyun 			macaddr = cam_const_addr[key_index];
249*4882a593Smuzhiyun 			entry_id = key_index;
250*4882a593Smuzhiyun 		} else {
251*4882a593Smuzhiyun 			if (is_group) {
252*4882a593Smuzhiyun 				macaddr = cam_const_broad;
253*4882a593Smuzhiyun 				entry_id = key_index;
254*4882a593Smuzhiyun 			} else {
255*4882a593Smuzhiyun 				if (mac->opmode == NL80211_IFTYPE_AP ||
256*4882a593Smuzhiyun 				    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
257*4882a593Smuzhiyun 					entry_id = rtl_cam_get_free_entry(hw,
258*4882a593Smuzhiyun 								 p_macaddr);
259*4882a593Smuzhiyun 					if (entry_id >=  TOTAL_CAM_ENTRY) {
260*4882a593Smuzhiyun 						pr_err("Can not find free hw security cam entry\n");
261*4882a593Smuzhiyun 						return;
262*4882a593Smuzhiyun 					}
263*4882a593Smuzhiyun 				} else {
264*4882a593Smuzhiyun 					entry_id = CAM_PAIRWISE_KEY_POSITION;
265*4882a593Smuzhiyun 				}
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 				key_index = PAIRWISE_KEYIDX;
268*4882a593Smuzhiyun 				is_pairwise = true;
269*4882a593Smuzhiyun 			}
270*4882a593Smuzhiyun 		}
271*4882a593Smuzhiyun 		if (rtlpriv->sec.key_len[key_index] == 0) {
272*4882a593Smuzhiyun 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
273*4882a593Smuzhiyun 				"delete one entry\n");
274*4882a593Smuzhiyun 			if (mac->opmode == NL80211_IFTYPE_AP ||
275*4882a593Smuzhiyun 			    mac->opmode == NL80211_IFTYPE_MESH_POINT)
276*4882a593Smuzhiyun 				rtl_cam_del_entry(hw, p_macaddr);
277*4882a593Smuzhiyun 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
278*4882a593Smuzhiyun 		} else {
279*4882a593Smuzhiyun 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
280*4882a593Smuzhiyun 				"The insert KEY length is %d\n",
281*4882a593Smuzhiyun 				 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
282*4882a593Smuzhiyun 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
283*4882a593Smuzhiyun 				"The insert KEY is %x %x\n",
284*4882a593Smuzhiyun 				rtlpriv->sec.key_buf[0][0],
285*4882a593Smuzhiyun 				rtlpriv->sec.key_buf[0][1]);
286*4882a593Smuzhiyun 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
287*4882a593Smuzhiyun 				"add one entry\n");
288*4882a593Smuzhiyun 			if (is_pairwise) {
289*4882a593Smuzhiyun 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
290*4882a593Smuzhiyun 					      "Pairwise Key content",
291*4882a593Smuzhiyun 					      rtlpriv->sec.pairwise_key,
292*4882a593Smuzhiyun 					      rtlpriv->sec.
293*4882a593Smuzhiyun 					      key_len[PAIRWISE_KEYIDX]);
294*4882a593Smuzhiyun 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
295*4882a593Smuzhiyun 					"set Pairwise key\n");
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 				rtl_cam_add_one_entry(hw, macaddr, key_index,
298*4882a593Smuzhiyun 						entry_id, enc_algo,
299*4882a593Smuzhiyun 						CAM_CONFIG_NO_USEDK,
300*4882a593Smuzhiyun 						rtlpriv->sec.
301*4882a593Smuzhiyun 						key_buf[key_index]);
302*4882a593Smuzhiyun 			} else {
303*4882a593Smuzhiyun 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
304*4882a593Smuzhiyun 					"set group key\n");
305*4882a593Smuzhiyun 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
306*4882a593Smuzhiyun 					rtl_cam_add_one_entry(hw,
307*4882a593Smuzhiyun 						rtlefuse->dev_addr,
308*4882a593Smuzhiyun 						PAIRWISE_KEYIDX,
309*4882a593Smuzhiyun 						CAM_PAIRWISE_KEY_POSITION,
310*4882a593Smuzhiyun 						enc_algo,
311*4882a593Smuzhiyun 						CAM_CONFIG_NO_USEDK,
312*4882a593Smuzhiyun 						rtlpriv->sec.key_buf
313*4882a593Smuzhiyun 						[entry_id]);
314*4882a593Smuzhiyun 				}
315*4882a593Smuzhiyun 				rtl_cam_add_one_entry(hw, macaddr, key_index,
316*4882a593Smuzhiyun 						entry_id, enc_algo,
317*4882a593Smuzhiyun 						CAM_CONFIG_NO_USEDK,
318*4882a593Smuzhiyun 						rtlpriv->sec.key_buf[entry_id]);
319*4882a593Smuzhiyun 			}
320*4882a593Smuzhiyun 		}
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
rtl92c_get_txdma_status(struct ieee80211_hw * hw)324*4882a593Smuzhiyun u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
rtl92c_enable_interrupt(struct ieee80211_hw * hw)331*4882a593Smuzhiyun void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
334*4882a593Smuzhiyun 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
335*4882a593Smuzhiyun 	struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	if (IS_HARDWARE_TYPE_8192CE(rtlpriv)) {
338*4882a593Smuzhiyun 		rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
339*4882a593Smuzhiyun 				0xFFFFFFFF);
340*4882a593Smuzhiyun 		rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
341*4882a593Smuzhiyun 				0xFFFFFFFF);
342*4882a593Smuzhiyun 	} else {
343*4882a593Smuzhiyun 		rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
344*4882a593Smuzhiyun 				0xFFFFFFFF);
345*4882a593Smuzhiyun 		rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
346*4882a593Smuzhiyun 				0xFFFFFFFF);
347*4882a593Smuzhiyun 	}
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun 
rtl92c_init_interrupt(struct ieee80211_hw * hw)350*4882a593Smuzhiyun void rtl92c_init_interrupt(struct ieee80211_hw *hw)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun 	 rtl92c_enable_interrupt(hw);
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
rtl92c_disable_interrupt(struct ieee80211_hw * hw)355*4882a593Smuzhiyun void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
360*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun 
rtl92c_set_qos(struct ieee80211_hw * hw,int aci)363*4882a593Smuzhiyun void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	rtl92c_dm_init_edca_turbo(hw);
368*4882a593Smuzhiyun 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
rtl92c_init_driver_info_size(struct ieee80211_hw * hw,u8 size)371*4882a593Smuzhiyun void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
rtl92c_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)378*4882a593Smuzhiyun int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun 	u8 value;
381*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	switch (type) {
384*4882a593Smuzhiyun 	case NL80211_IFTYPE_UNSPECIFIED:
385*4882a593Smuzhiyun 		value = NT_NO_LINK;
386*4882a593Smuzhiyun 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
387*4882a593Smuzhiyun 			"Set Network type to NO LINK!\n");
388*4882a593Smuzhiyun 		break;
389*4882a593Smuzhiyun 	case NL80211_IFTYPE_ADHOC:
390*4882a593Smuzhiyun 		value = NT_LINK_AD_HOC;
391*4882a593Smuzhiyun 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
392*4882a593Smuzhiyun 			"Set Network type to Ad Hoc!\n");
393*4882a593Smuzhiyun 		break;
394*4882a593Smuzhiyun 	case NL80211_IFTYPE_STATION:
395*4882a593Smuzhiyun 		value = NT_LINK_AP;
396*4882a593Smuzhiyun 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
397*4882a593Smuzhiyun 			"Set Network type to STA!\n");
398*4882a593Smuzhiyun 		break;
399*4882a593Smuzhiyun 	case NL80211_IFTYPE_AP:
400*4882a593Smuzhiyun 		value = NT_AS_AP;
401*4882a593Smuzhiyun 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
402*4882a593Smuzhiyun 			"Set Network type to AP!\n");
403*4882a593Smuzhiyun 		break;
404*4882a593Smuzhiyun 	default:
405*4882a593Smuzhiyun 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
406*4882a593Smuzhiyun 			"Network type %d not supported!\n", type);
407*4882a593Smuzhiyun 		return -EOPNOTSUPP;
408*4882a593Smuzhiyun 	}
409*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, MSR, value);
410*4882a593Smuzhiyun 	return 0;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun 
rtl92c_init_network_type(struct ieee80211_hw * hw)413*4882a593Smuzhiyun void rtl92c_init_network_type(struct ieee80211_hw *hw)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun 	rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun 
rtl92c_init_adaptive_ctrl(struct ieee80211_hw * hw)418*4882a593Smuzhiyun void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun 	u16	value16;
421*4882a593Smuzhiyun 	u32	value32;
422*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/* Response Rate Set */
425*4882a593Smuzhiyun 	value32 = rtl_read_dword(rtlpriv, REG_RRSR);
426*4882a593Smuzhiyun 	value32 &= ~RATE_BITMAP_ALL;
427*4882a593Smuzhiyun 	value32 |= RATE_RRSR_CCK_ONLY_1M;
428*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_RRSR, value32);
429*4882a593Smuzhiyun 	/* SIFS (used in NAV) */
430*4882a593Smuzhiyun 	value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
431*4882a593Smuzhiyun 	rtl_write_word(rtlpriv,  REG_SPEC_SIFS, value16);
432*4882a593Smuzhiyun 	/* Retry Limit */
433*4882a593Smuzhiyun 	value16 = _LRL(0x30) | _SRL(0x30);
434*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv,  REG_RL, value16);
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun 
rtl92c_init_rate_fallback(struct ieee80211_hw * hw)437*4882a593Smuzhiyun void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	/* Set Data Auto Rate Fallback Retry Count register. */
442*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv,  REG_DARFRC, 0x00000000);
443*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv,  REG_DARFRC+4, 0x10080404);
444*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv,  REG_RARFRC, 0x04030201);
445*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv,  REG_RARFRC+4, 0x08070605);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
rtl92c_set_cck_sifs(struct ieee80211_hw * hw,u8 trx_sifs,u8 ctx_sifs)448*4882a593Smuzhiyun static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
449*4882a593Smuzhiyun 				u8 ctx_sifs)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
454*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun 
rtl92c_set_ofdm_sifs(struct ieee80211_hw * hw,u8 trx_sifs,u8 ctx_sifs)457*4882a593Smuzhiyun static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
458*4882a593Smuzhiyun 				 u8 ctx_sifs)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
463*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
rtl92c_init_edca_param(struct ieee80211_hw * hw,u16 queue,u16 txop,u8 cw_min,u8 cw_max,u8 aifs)466*4882a593Smuzhiyun void rtl92c_init_edca_param(struct ieee80211_hw *hw,
467*4882a593Smuzhiyun 			    u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	/* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
470*4882a593Smuzhiyun 	 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
471*4882a593Smuzhiyun 	 */
472*4882a593Smuzhiyun 	u32 value;
473*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	value = (u32)aifs;
476*4882a593Smuzhiyun 	value |= ((u32)cw_min & 0xF) << 8;
477*4882a593Smuzhiyun 	value |= ((u32)cw_max & 0xF) << 12;
478*4882a593Smuzhiyun 	value |= (u32)txop << 16;
479*4882a593Smuzhiyun 	/* 92C hardware register sequence is the same as queue number. */
480*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun 
rtl92c_init_edca(struct ieee80211_hw * hw)483*4882a593Smuzhiyun void rtl92c_init_edca(struct ieee80211_hw *hw)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun 	u16 value16;
486*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	/* disable EDCCA count down, to reduce collison and retry */
489*4882a593Smuzhiyun 	value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
490*4882a593Smuzhiyun 	value16 |= DIS_EDCA_CNT_DWN;
491*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
492*4882a593Smuzhiyun 	/* Update SIFS timing.  ??????????
493*4882a593Smuzhiyun 	 * pHalData->SifsTime = 0x0e0e0a0a; */
494*4882a593Smuzhiyun 	rtl92c_set_cck_sifs(hw, 0xa, 0xa);
495*4882a593Smuzhiyun 	rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
496*4882a593Smuzhiyun 	/* Set CCK/OFDM SIFS to be 10us. */
497*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
498*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
499*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
500*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
501*4882a593Smuzhiyun 	/* TXOP */
502*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
503*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
504*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
505*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
506*4882a593Smuzhiyun 	/* PIFS */
507*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
508*4882a593Smuzhiyun 	/* AGGR BREAK TIME Register */
509*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
510*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
511*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
512*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun 
rtl92c_init_ampdu_aggregation(struct ieee80211_hw * hw)515*4882a593Smuzhiyun void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
520*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
521*4882a593Smuzhiyun 	/* init AMPDU aggregation number, tuning for Tx's TP, */
522*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, 0x4CA, 0x0708);
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
rtl92c_init_beacon_max_error(struct ieee80211_hw * hw)525*4882a593Smuzhiyun void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
rtl92c_init_rdg_setting(struct ieee80211_hw * hw)532*4882a593Smuzhiyun void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
537*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
538*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
rtl92c_init_retry_function(struct ieee80211_hw * hw)541*4882a593Smuzhiyun void rtl92c_init_retry_function(struct ieee80211_hw *hw)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun 	u8	value8;
544*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
547*4882a593Smuzhiyun 	value8 |= EN_AMPDU_RTY_NEW;
548*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
549*4882a593Smuzhiyun 	/* Set ACK timeout */
550*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
rtl92c_disable_fast_edca(struct ieee80211_hw * hw)553*4882a593Smuzhiyun void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
rtl92c_set_min_space(struct ieee80211_hw * hw,bool is2T)560*4882a593Smuzhiyun void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
563*4882a593Smuzhiyun 	u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun /*==============================================================*/
569*4882a593Smuzhiyun 
_rtl92c_query_rxphystatus(struct ieee80211_hw * hw,struct rtl_stats * pstats,struct rx_desc_92c * p_desc,struct rx_fwinfo_92c * p_drvinfo,bool packet_match_bssid,bool packet_toself,bool packet_beacon)570*4882a593Smuzhiyun static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
571*4882a593Smuzhiyun 				      struct rtl_stats *pstats,
572*4882a593Smuzhiyun 				      struct rx_desc_92c *p_desc,
573*4882a593Smuzhiyun 				      struct rx_fwinfo_92c *p_drvinfo,
574*4882a593Smuzhiyun 				      bool packet_match_bssid,
575*4882a593Smuzhiyun 				      bool packet_toself,
576*4882a593Smuzhiyun 				      bool packet_beacon)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	struct rtl_priv *rtlpriv = rtl_priv(hw);
579*4882a593Smuzhiyun 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
580*4882a593Smuzhiyun 	struct phy_sts_cck_8192s_t *cck_buf;
581*4882a593Smuzhiyun 	s8 rx_pwr_all = 0, rx_pwr[4];
582*4882a593Smuzhiyun 	u8 rf_rx_num = 0, evm, pwdb_all;
583*4882a593Smuzhiyun 	u8 i, max_spatial_stream;
584*4882a593Smuzhiyun 	u32 rssi, total_rssi = 0;
585*4882a593Smuzhiyun 	bool in_powersavemode = false;
586*4882a593Smuzhiyun 	bool is_cck_rate;
587*4882a593Smuzhiyun 	__le32 *pdesc = (__le32 *)p_desc;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs);
590*4882a593Smuzhiyun 	pstats->packet_matchbssid = packet_match_bssid;
591*4882a593Smuzhiyun 	pstats->packet_toself = packet_toself;
592*4882a593Smuzhiyun 	pstats->packet_beacon = packet_beacon;
593*4882a593Smuzhiyun 	pstats->is_cck = is_cck_rate;
594*4882a593Smuzhiyun 	pstats->RX_SIGQ[0] = -1;
595*4882a593Smuzhiyun 	pstats->RX_SIGQ[1] = -1;
596*4882a593Smuzhiyun 	if (is_cck_rate) {
597*4882a593Smuzhiyun 		u8 report, cck_highpwr;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 		cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
600*4882a593Smuzhiyun 		if (!in_powersavemode)
601*4882a593Smuzhiyun 			cck_highpwr = rtlphy->cck_high_power;
602*4882a593Smuzhiyun 		else
603*4882a593Smuzhiyun 			cck_highpwr = false;
604*4882a593Smuzhiyun 		if (!cck_highpwr) {
605*4882a593Smuzhiyun 			u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 			report = cck_buf->cck_agc_rpt & 0xc0;
608*4882a593Smuzhiyun 			report = report >> 6;
609*4882a593Smuzhiyun 			switch (report) {
610*4882a593Smuzhiyun 			case 0x3:
611*4882a593Smuzhiyun 				rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
612*4882a593Smuzhiyun 				break;
613*4882a593Smuzhiyun 			case 0x2:
614*4882a593Smuzhiyun 				rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
615*4882a593Smuzhiyun 				break;
616*4882a593Smuzhiyun 			case 0x1:
617*4882a593Smuzhiyun 				rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
618*4882a593Smuzhiyun 				break;
619*4882a593Smuzhiyun 			case 0x0:
620*4882a593Smuzhiyun 				rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
621*4882a593Smuzhiyun 				break;
622*4882a593Smuzhiyun 			}
623*4882a593Smuzhiyun 		} else {
624*4882a593Smuzhiyun 			u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 			report = p_drvinfo->cfosho[0] & 0x60;
627*4882a593Smuzhiyun 			report = report >> 5;
628*4882a593Smuzhiyun 			switch (report) {
629*4882a593Smuzhiyun 			case 0x3:
630*4882a593Smuzhiyun 				rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
631*4882a593Smuzhiyun 				break;
632*4882a593Smuzhiyun 			case 0x2:
633*4882a593Smuzhiyun 				rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
634*4882a593Smuzhiyun 				break;
635*4882a593Smuzhiyun 			case 0x1:
636*4882a593Smuzhiyun 				rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
637*4882a593Smuzhiyun 				break;
638*4882a593Smuzhiyun 			case 0x0:
639*4882a593Smuzhiyun 				rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
640*4882a593Smuzhiyun 				break;
641*4882a593Smuzhiyun 			}
642*4882a593Smuzhiyun 		}
643*4882a593Smuzhiyun 		pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
644*4882a593Smuzhiyun 		pstats->rx_pwdb_all = pwdb_all;
645*4882a593Smuzhiyun 		pstats->recvsignalpower = rx_pwr_all;
646*4882a593Smuzhiyun 		if (packet_match_bssid) {
647*4882a593Smuzhiyun 			u8 sq;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 			if (pstats->rx_pwdb_all > 40)
650*4882a593Smuzhiyun 				sq = 100;
651*4882a593Smuzhiyun 			else {
652*4882a593Smuzhiyun 				sq = cck_buf->sq_rpt;
653*4882a593Smuzhiyun 				if (sq > 64)
654*4882a593Smuzhiyun 					sq = 0;
655*4882a593Smuzhiyun 				else if (sq < 20)
656*4882a593Smuzhiyun 					sq = 100;
657*4882a593Smuzhiyun 				else
658*4882a593Smuzhiyun 					sq = ((64 - sq) * 100) / 44;
659*4882a593Smuzhiyun 			}
660*4882a593Smuzhiyun 			pstats->signalquality = sq;
661*4882a593Smuzhiyun 			pstats->RX_SIGQ[0] = sq;
662*4882a593Smuzhiyun 			pstats->RX_SIGQ[1] = -1;
663*4882a593Smuzhiyun 		}
664*4882a593Smuzhiyun 	} else {
665*4882a593Smuzhiyun 		rtlpriv->dm.rfpath_rxenable[0] =
666*4882a593Smuzhiyun 		    rtlpriv->dm.rfpath_rxenable[1] = true;
667*4882a593Smuzhiyun 		for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
668*4882a593Smuzhiyun 			if (rtlpriv->dm.rfpath_rxenable[i])
669*4882a593Smuzhiyun 				rf_rx_num++;
670*4882a593Smuzhiyun 			rx_pwr[i] =
671*4882a593Smuzhiyun 			    ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
672*4882a593Smuzhiyun 			rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
673*4882a593Smuzhiyun 			total_rssi += rssi;
674*4882a593Smuzhiyun 			rtlpriv->stats.rx_snr_db[i] =
675*4882a593Smuzhiyun 			    (long)(p_drvinfo->rxsnr[i] / 2);
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun 			if (packet_match_bssid)
678*4882a593Smuzhiyun 				pstats->rx_mimo_signalstrength[i] = (u8) rssi;
679*4882a593Smuzhiyun 		}
680*4882a593Smuzhiyun 		rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
681*4882a593Smuzhiyun 		pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
682*4882a593Smuzhiyun 		pstats->rx_pwdb_all = pwdb_all;
683*4882a593Smuzhiyun 		pstats->rxpower = rx_pwr_all;
684*4882a593Smuzhiyun 		pstats->recvsignalpower = rx_pwr_all;
685*4882a593Smuzhiyun 		if (get_rx_desc_rx_mcs(pdesc) &&
686*4882a593Smuzhiyun 		    get_rx_desc_rx_mcs(pdesc) >= DESC_RATEMCS8 &&
687*4882a593Smuzhiyun 		    get_rx_desc_rx_mcs(pdesc) <= DESC_RATEMCS15)
688*4882a593Smuzhiyun 			max_spatial_stream = 2;
689*4882a593Smuzhiyun 		else
690*4882a593Smuzhiyun 			max_spatial_stream = 1;
691*4882a593Smuzhiyun 		for (i = 0; i < max_spatial_stream; i++) {
692*4882a593Smuzhiyun 			evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]);
693*4882a593Smuzhiyun 			if (packet_match_bssid) {
694*4882a593Smuzhiyun 				if (i == 0)
695*4882a593Smuzhiyun 					pstats->signalquality =
696*4882a593Smuzhiyun 					    (u8) (evm & 0xff);
697*4882a593Smuzhiyun 				pstats->RX_SIGQ[i] =
698*4882a593Smuzhiyun 				    (u8) (evm & 0xff);
699*4882a593Smuzhiyun 			}
700*4882a593Smuzhiyun 		}
701*4882a593Smuzhiyun 	}
702*4882a593Smuzhiyun 	if (is_cck_rate)
703*4882a593Smuzhiyun 		pstats->signalstrength =
704*4882a593Smuzhiyun 		    (u8)(rtl_signal_scale_mapping(hw, pwdb_all));
705*4882a593Smuzhiyun 	else if (rf_rx_num != 0)
706*4882a593Smuzhiyun 		pstats->signalstrength =
707*4882a593Smuzhiyun 		    (u8)(rtl_signal_scale_mapping(hw, total_rssi /= rf_rx_num));
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun 
rtl92c_translate_rx_signal_stuff(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_stats * pstats,struct rx_desc_92c * pdesc,struct rx_fwinfo_92c * p_drvinfo)710*4882a593Smuzhiyun void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
711*4882a593Smuzhiyun 					       struct sk_buff *skb,
712*4882a593Smuzhiyun 					       struct rtl_stats *pstats,
713*4882a593Smuzhiyun 					       struct rx_desc_92c *pdesc,
714*4882a593Smuzhiyun 					       struct rx_fwinfo_92c *p_drvinfo)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
717*4882a593Smuzhiyun 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
718*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
719*4882a593Smuzhiyun 	u8 *tmp_buf;
720*4882a593Smuzhiyun 	u8 *praddr;
721*4882a593Smuzhiyun 	__le16 fc;
722*4882a593Smuzhiyun 	u16 type, cpu_fc;
723*4882a593Smuzhiyun 	bool packet_matchbssid, packet_toself, packet_beacon = false;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
726*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)tmp_buf;
727*4882a593Smuzhiyun 	fc = hdr->frame_control;
728*4882a593Smuzhiyun 	cpu_fc = le16_to_cpu(fc);
729*4882a593Smuzhiyun 	type = WLAN_FC_GET_TYPE(fc);
730*4882a593Smuzhiyun 	praddr = hdr->addr1;
731*4882a593Smuzhiyun 	packet_matchbssid =
732*4882a593Smuzhiyun 	    ((IEEE80211_FTYPE_CTL != type) &&
733*4882a593Smuzhiyun 	     ether_addr_equal(mac->bssid,
734*4882a593Smuzhiyun 			      (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
735*4882a593Smuzhiyun 			      (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
736*4882a593Smuzhiyun 			      hdr->addr3) &&
737*4882a593Smuzhiyun 	     (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	packet_toself = packet_matchbssid &&
740*4882a593Smuzhiyun 	    ether_addr_equal(praddr, rtlefuse->dev_addr);
741*4882a593Smuzhiyun 	if (ieee80211_is_beacon(fc))
742*4882a593Smuzhiyun 		packet_beacon = true;
743*4882a593Smuzhiyun 	_rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
744*4882a593Smuzhiyun 				   packet_matchbssid, packet_toself,
745*4882a593Smuzhiyun 				   packet_beacon);
746*4882a593Smuzhiyun 	rtl_process_phyinfo(hw, tmp_buf, pstats);
747*4882a593Smuzhiyun }
748