1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92C_DM_H__ 5*4882a593Smuzhiyun #define __RTL92C_DM_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define HAL_DM_DIG_DISABLE BIT(0) 8*4882a593Smuzhiyun #define HAL_DM_HIPWR_DISABLE BIT(1) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define OFDM_TABLE_LENGTH 37 11*4882a593Smuzhiyun #define CCK_TABLE_LENGTH 33 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define OFDM_TABLE_SIZE 37 14*4882a593Smuzhiyun #define CCK_TABLE_SIZE 33 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define BW_AUTO_SWITCH_HIGH_LOW 25 17*4882a593Smuzhiyun #define BW_AUTO_SWITCH_LOW_HIGH 30 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define DM_DIG_FA_UPPER 0x32 20*4882a593Smuzhiyun #define DM_DIG_FA_LOWER 0x20 21*4882a593Smuzhiyun #define DM_DIG_FA_TH0 0x20 22*4882a593Smuzhiyun #define DM_DIG_FA_TH1 0x100 23*4882a593Smuzhiyun #define DM_DIG_FA_TH2 0x200 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define RXPATHSELECTION_SS_TH_LOW 30 26*4882a593Smuzhiyun #define RXPATHSELECTION_DIFF_TH 18 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define DM_RATR_STA_INIT 0 29*4882a593Smuzhiyun #define DM_RATR_STA_HIGH 1 30*4882a593Smuzhiyun #define DM_RATR_STA_MIDDLE 2 31*4882a593Smuzhiyun #define DM_RATR_STA_LOW 3 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CTS2SELF_THVAL 30 34*4882a593Smuzhiyun #define REGC38_TH 20 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define WAIOTTHVAL 25 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_NORMAL 0 39*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_LEVEL1 1 40*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_LEVEL2 2 41*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_BT1 3 42*4882a593Smuzhiyun #define TXHIGHPWRLEVEL_BT2 4 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define DM_TYPE_BYFW 0 45*4882a593Smuzhiyun #define DM_TYPE_BYDRIVER 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 48*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun void rtl92c_dm_init(struct ieee80211_hw *hw); 51*4882a593Smuzhiyun void rtl92c_dm_watchdog(struct ieee80211_hw *hw); 52*4882a593Smuzhiyun void rtl92c_dm_write_dig(struct ieee80211_hw *hw); 53*4882a593Smuzhiyun void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw); 54*4882a593Smuzhiyun void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw); 55*4882a593Smuzhiyun void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 56*4882a593Smuzhiyun void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 57*4882a593Smuzhiyun void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw); 58*4882a593Smuzhiyun void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61