1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL92C_DEF_H__ 5*4882a593Smuzhiyun #define __RTL92C_DEF_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define PHY_RSSI_SLID_WIN_MAX 100 8*4882a593Smuzhiyun #define PHY_LINKQUALITY_SLID_WIN_MAX 20 9*4882a593Smuzhiyun #define PHY_BEACON_RSSI_SLID_WIN_MAX 10 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define RX_SMOOTH_FACTOR 20 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 14*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_LOWER 1 15*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_UPPER 2 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RX_MPDU_QUEUE 0 18*4882a593Smuzhiyun #define RX_CMD_QUEUE 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CHIP_VER_B BIT(4) 21*4882a593Smuzhiyun #define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3) 22*4882a593Smuzhiyun #define CHIP_BONDING_92C_1T2R 0x1 23*4882a593Smuzhiyun #define RF_TYPE_1T2R BIT(1) 24*4882a593Smuzhiyun #define CHIP_92C_BITMASK BIT(0) 25*4882a593Smuzhiyun #define CHIP_UNKNOWN BIT(7) 26*4882a593Smuzhiyun #define CHIP_92C_1T2R 0x03 27*4882a593Smuzhiyun #define CHIP_92C 0x01 28*4882a593Smuzhiyun #define CHIP_88C 0x00 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum version_8192c { 31*4882a593Smuzhiyun VERSION_A_CHIP_92C = 0x01, 32*4882a593Smuzhiyun VERSION_A_CHIP_88C = 0x00, 33*4882a593Smuzhiyun VERSION_B_CHIP_92C = 0x11, 34*4882a593Smuzhiyun VERSION_B_CHIP_88C = 0x10, 35*4882a593Smuzhiyun VERSION_TEST_CHIP_88C = 0x00, 36*4882a593Smuzhiyun VERSION_TEST_CHIP_92C = 0x01, 37*4882a593Smuzhiyun VERSION_NORMAL_TSMC_CHIP_88C = 0x10, 38*4882a593Smuzhiyun VERSION_NORMAL_TSMC_CHIP_92C = 0x11, 39*4882a593Smuzhiyun VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13, 40*4882a593Smuzhiyun VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30, 41*4882a593Smuzhiyun VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31, 42*4882a593Smuzhiyun VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33, 43*4882a593Smuzhiyun VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34, 44*4882a593Smuzhiyun VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c, 45*4882a593Smuzhiyun VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70, 46*4882a593Smuzhiyun VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71, 47*4882a593Smuzhiyun VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73, 48*4882a593Smuzhiyun VERSION_UNKNOWN = 0x88, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum rtl819x_loopback_e { 52*4882a593Smuzhiyun RTL819X_NO_LOOPBACK = 0, 53*4882a593Smuzhiyun RTL819X_MAC_LOOPBACK = 1, 54*4882a593Smuzhiyun RTL819X_DMA_LOOPBACK = 2, 55*4882a593Smuzhiyun RTL819X_CCK_LOOPBACK = 3, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enum rf_optype { 59*4882a593Smuzhiyun RF_OP_BY_SW_3WIRE = 0, 60*4882a593Smuzhiyun RF_OP_BY_FW, 61*4882a593Smuzhiyun RF_OP_MAX 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun enum rf_power_state { 65*4882a593Smuzhiyun RF_ON, 66*4882a593Smuzhiyun RF_OFF, 67*4882a593Smuzhiyun RF_SLEEP, 68*4882a593Smuzhiyun RF_SHUT_DOWN, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun enum power_save_mode { 72*4882a593Smuzhiyun POWER_SAVE_MODE_ACTIVE, 73*4882a593Smuzhiyun POWER_SAVE_MODE_SAVE, 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun enum power_polocy_config { 77*4882a593Smuzhiyun POWERCFG_MAX_POWER_SAVINGS, 78*4882a593Smuzhiyun POWERCFG_GLOBAL_POWER_SAVINGS, 79*4882a593Smuzhiyun POWERCFG_LOCAL_POWER_SAVINGS, 80*4882a593Smuzhiyun POWERCFG_LENOVO, 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun enum interface_select_pci { 84*4882a593Smuzhiyun INTF_SEL1_MINICARD = 0, 85*4882a593Smuzhiyun INTF_SEL0_PCIE = 1, 86*4882a593Smuzhiyun INTF_SEL2_RSV = 2, 87*4882a593Smuzhiyun INTF_SEL3_RSV = 3, 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun enum rtl_desc_qsel { 91*4882a593Smuzhiyun QSLT_BK = 0x2, 92*4882a593Smuzhiyun QSLT_BE = 0x0, 93*4882a593Smuzhiyun QSLT_VI = 0x5, 94*4882a593Smuzhiyun QSLT_VO = 0x7, 95*4882a593Smuzhiyun QSLT_BEACON = 0x10, 96*4882a593Smuzhiyun QSLT_HIGH = 0x11, 97*4882a593Smuzhiyun QSLT_MGNT = 0x12, 98*4882a593Smuzhiyun QSLT_CMD = 0x13, 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct phy_sts_cck_8192s_t { 102*4882a593Smuzhiyun u8 adc_pwdb_X[4]; 103*4882a593Smuzhiyun u8 sq_rpt; 104*4882a593Smuzhiyun u8 cck_agc_rpt; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct h2c_cmd_8192c { 108*4882a593Smuzhiyun u8 element_id; 109*4882a593Smuzhiyun u32 cmd_len; 110*4882a593Smuzhiyun u8 *p_cmdbuffer; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif 114