1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2009-2013 Realtek Corporation.*/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include "../wifi.h"
5*4882a593Smuzhiyun #include "../core.h"
6*4882a593Smuzhiyun #include "../pci.h"
7*4882a593Smuzhiyun #include "reg.h"
8*4882a593Smuzhiyun #include "def.h"
9*4882a593Smuzhiyun #include "phy.h"
10*4882a593Smuzhiyun #include "dm.h"
11*4882a593Smuzhiyun #include "hw.h"
12*4882a593Smuzhiyun #include "trx.h"
13*4882a593Smuzhiyun #include "led.h"
14*4882a593Smuzhiyun #include "table.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/vmalloc.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun
rtl88e_init_aspm_vars(struct ieee80211_hw * hw)19*4882a593Smuzhiyun static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
22*4882a593Smuzhiyun struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /*close ASPM for AMD defaultly */
25*4882a593Smuzhiyun rtlpci->const_amdpci_aspm = 0;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* ASPM PS mode.
28*4882a593Smuzhiyun * 0 - Disable ASPM,
29*4882a593Smuzhiyun * 1 - Enable ASPM without Clock Req,
30*4882a593Smuzhiyun * 2 - Enable ASPM with Clock Req,
31*4882a593Smuzhiyun * 3 - Alwyas Enable ASPM with Clock Req,
32*4882a593Smuzhiyun * 4 - Always Enable ASPM without Clock Req.
33*4882a593Smuzhiyun * set defult to RTL8192CE:3 RTL8192E:2
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun rtlpci->const_pci_aspm = 3;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*Setting for PCI-E device */
38*4882a593Smuzhiyun rtlpci->const_devicepci_aspm_setting = 0x03;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*Setting for PCI-E bridge */
41*4882a593Smuzhiyun rtlpci->const_hostpci_aspm_setting = 0x02;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* In Hw/Sw Radio Off situation.
44*4882a593Smuzhiyun * 0 - Default,
45*4882a593Smuzhiyun * 1 - From ASPM setting without low Mac Pwr,
46*4882a593Smuzhiyun * 2 - From ASPM setting with low Mac Pwr,
47*4882a593Smuzhiyun * 3 - Bus D3
48*4882a593Smuzhiyun * set default to RTL8192CE:0 RTL8192SE:2
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun rtlpci->const_hwsw_rfoff_d3 = 0;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* This setting works for those device with
53*4882a593Smuzhiyun * backdoor ASPM setting such as EPHY setting.
54*4882a593Smuzhiyun * 0 - Not support ASPM,
55*4882a593Smuzhiyun * 1 - Support ASPM,
56*4882a593Smuzhiyun * 2 - According to chipset.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
rtl88e_init_sw_vars(struct ieee80211_hw * hw)61*4882a593Smuzhiyun static int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun int err = 0;
64*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
65*4882a593Smuzhiyun struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66*4882a593Smuzhiyun u8 tid;
67*4882a593Smuzhiyun char *fw_name;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun rtl8188ee_bt_reg_init(hw);
70*4882a593Smuzhiyun rtlpriv->dm.dm_initialgain_enable = true;
71*4882a593Smuzhiyun rtlpriv->dm.dm_flag = 0;
72*4882a593Smuzhiyun rtlpriv->dm.disable_framebursting = false;
73*4882a593Smuzhiyun rtlpriv->dm.thermalvalue = 0;
74*4882a593Smuzhiyun rtlpci->transmit_config = CFENDFORM | BIT(15);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* compatible 5G band 88ce just 2.4G band & smsp */
77*4882a593Smuzhiyun rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
78*4882a593Smuzhiyun rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
79*4882a593Smuzhiyun rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun rtlpci->receive_config = (RCR_APPFCS |
82*4882a593Smuzhiyun RCR_APP_MIC |
83*4882a593Smuzhiyun RCR_APP_ICV |
84*4882a593Smuzhiyun RCR_APP_PHYST_RXFF |
85*4882a593Smuzhiyun RCR_HTC_LOC_CTRL |
86*4882a593Smuzhiyun RCR_AMF |
87*4882a593Smuzhiyun RCR_ACF |
88*4882a593Smuzhiyun RCR_ADF |
89*4882a593Smuzhiyun RCR_AICV |
90*4882a593Smuzhiyun RCR_ACRC32 |
91*4882a593Smuzhiyun RCR_AB |
92*4882a593Smuzhiyun RCR_AM |
93*4882a593Smuzhiyun RCR_APM |
94*4882a593Smuzhiyun 0);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun rtlpci->irq_mask[0] =
97*4882a593Smuzhiyun (u32)(IMR_PSTIMEOUT |
98*4882a593Smuzhiyun IMR_HSISR_IND_ON_INT |
99*4882a593Smuzhiyun IMR_C2HCMD |
100*4882a593Smuzhiyun IMR_HIGHDOK |
101*4882a593Smuzhiyun IMR_MGNTDOK |
102*4882a593Smuzhiyun IMR_BKDOK |
103*4882a593Smuzhiyun IMR_BEDOK |
104*4882a593Smuzhiyun IMR_VIDOK |
105*4882a593Smuzhiyun IMR_VODOK |
106*4882a593Smuzhiyun IMR_RDU |
107*4882a593Smuzhiyun IMR_ROK |
108*4882a593Smuzhiyun 0);
109*4882a593Smuzhiyun rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
110*4882a593Smuzhiyun rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* for LPS & IPS */
113*4882a593Smuzhiyun rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
114*4882a593Smuzhiyun rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
115*4882a593Smuzhiyun rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
116*4882a593Smuzhiyun rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
117*4882a593Smuzhiyun if (rtlpriv->cfg->mod_params->disable_watchdog)
118*4882a593Smuzhiyun pr_info("watchdog disabled\n");
119*4882a593Smuzhiyun if (!rtlpriv->psc.inactiveps)
120*4882a593Smuzhiyun pr_info("rtl8188ee: Power Save off (module option)\n");
121*4882a593Smuzhiyun if (!rtlpriv->psc.fwctrl_lps)
122*4882a593Smuzhiyun pr_info("rtl8188ee: FW Power Save off (module option)\n");
123*4882a593Smuzhiyun rtlpriv->psc.reg_fwctrl_lps = 3;
124*4882a593Smuzhiyun rtlpriv->psc.reg_max_lps_awakeintvl = 5;
125*4882a593Smuzhiyun /* for ASPM, you can close aspm through
126*4882a593Smuzhiyun * set const_support_pciaspm = 0
127*4882a593Smuzhiyun */
128*4882a593Smuzhiyun rtl88e_init_aspm_vars(hw);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (rtlpriv->psc.reg_fwctrl_lps == 1)
131*4882a593Smuzhiyun rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
132*4882a593Smuzhiyun else if (rtlpriv->psc.reg_fwctrl_lps == 2)
133*4882a593Smuzhiyun rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
134*4882a593Smuzhiyun else if (rtlpriv->psc.reg_fwctrl_lps == 3)
135*4882a593Smuzhiyun rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* for firmware buf */
138*4882a593Smuzhiyun rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
139*4882a593Smuzhiyun if (!rtlpriv->rtlhal.pfirmware) {
140*4882a593Smuzhiyun pr_info("Can't alloc buffer for fw.\n");
141*4882a593Smuzhiyun return 1;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun fw_name = "rtlwifi/rtl8188efw.bin";
145*4882a593Smuzhiyun rtlpriv->max_fw_size = 0x8000;
146*4882a593Smuzhiyun pr_info("Using firmware %s\n", fw_name);
147*4882a593Smuzhiyun err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
148*4882a593Smuzhiyun rtlpriv->io.dev, GFP_KERNEL, hw,
149*4882a593Smuzhiyun rtl_fw_cb);
150*4882a593Smuzhiyun if (err) {
151*4882a593Smuzhiyun pr_info("Failed to request firmware!\n");
152*4882a593Smuzhiyun vfree(rtlpriv->rtlhal.pfirmware);
153*4882a593Smuzhiyun rtlpriv->rtlhal.pfirmware = NULL;
154*4882a593Smuzhiyun return 1;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* for early mode */
158*4882a593Smuzhiyun rtlpriv->rtlhal.earlymode_enable = false;
159*4882a593Smuzhiyun rtlpriv->rtlhal.max_earlymode_num = 10;
160*4882a593Smuzhiyun for (tid = 0; tid < 8; tid++)
161*4882a593Smuzhiyun skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /*low power */
164*4882a593Smuzhiyun rtlpriv->psc.low_power_enable = false;
165*4882a593Smuzhiyun if (rtlpriv->psc.low_power_enable) {
166*4882a593Smuzhiyun timer_setup(&rtlpriv->works.fw_clockoff_timer,
167*4882a593Smuzhiyun rtl88ee_fw_clk_off_timer_callback, 0);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun timer_setup(&rtlpriv->works.fast_antenna_training_timer,
171*4882a593Smuzhiyun rtl88e_dm_fast_antenna_training_callback, 0);
172*4882a593Smuzhiyun return err;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
rtl88e_deinit_sw_vars(struct ieee80211_hw * hw)175*4882a593Smuzhiyun static void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct rtl_priv *rtlpriv = rtl_priv(hw);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (rtlpriv->rtlhal.pfirmware) {
180*4882a593Smuzhiyun vfree(rtlpriv->rtlhal.pfirmware);
181*4882a593Smuzhiyun rtlpriv->rtlhal.pfirmware = NULL;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (rtlpriv->psc.low_power_enable)
185*4882a593Smuzhiyun del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* get bt coexist status */
rtl88e_get_btc_status(void)191*4882a593Smuzhiyun static bool rtl88e_get_btc_status(void)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun return false;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun static struct rtl_hal_ops rtl8188ee_hal_ops = {
197*4882a593Smuzhiyun .init_sw_vars = rtl88e_init_sw_vars,
198*4882a593Smuzhiyun .deinit_sw_vars = rtl88e_deinit_sw_vars,
199*4882a593Smuzhiyun .read_eeprom_info = rtl88ee_read_eeprom_info,
200*4882a593Smuzhiyun .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
201*4882a593Smuzhiyun .hw_init = rtl88ee_hw_init,
202*4882a593Smuzhiyun .hw_disable = rtl88ee_card_disable,
203*4882a593Smuzhiyun .hw_suspend = rtl88ee_suspend,
204*4882a593Smuzhiyun .hw_resume = rtl88ee_resume,
205*4882a593Smuzhiyun .enable_interrupt = rtl88ee_enable_interrupt,
206*4882a593Smuzhiyun .disable_interrupt = rtl88ee_disable_interrupt,
207*4882a593Smuzhiyun .set_network_type = rtl88ee_set_network_type,
208*4882a593Smuzhiyun .set_chk_bssid = rtl88ee_set_check_bssid,
209*4882a593Smuzhiyun .set_qos = rtl88ee_set_qos,
210*4882a593Smuzhiyun .set_bcn_reg = rtl88ee_set_beacon_related_registers,
211*4882a593Smuzhiyun .set_bcn_intv = rtl88ee_set_beacon_interval,
212*4882a593Smuzhiyun .update_interrupt_mask = rtl88ee_update_interrupt_mask,
213*4882a593Smuzhiyun .get_hw_reg = rtl88ee_get_hw_reg,
214*4882a593Smuzhiyun .set_hw_reg = rtl88ee_set_hw_reg,
215*4882a593Smuzhiyun .update_rate_tbl = rtl88ee_update_hal_rate_tbl,
216*4882a593Smuzhiyun .fill_tx_desc = rtl88ee_tx_fill_desc,
217*4882a593Smuzhiyun .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
218*4882a593Smuzhiyun .query_rx_desc = rtl88ee_rx_query_desc,
219*4882a593Smuzhiyun .set_channel_access = rtl88ee_update_channel_access_setting,
220*4882a593Smuzhiyun .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
221*4882a593Smuzhiyun .set_bw_mode = rtl88e_phy_set_bw_mode,
222*4882a593Smuzhiyun .switch_channel = rtl88e_phy_sw_chnl,
223*4882a593Smuzhiyun .dm_watchdog = rtl88e_dm_watchdog,
224*4882a593Smuzhiyun .scan_operation_backup = rtl88e_phy_scan_operation_backup,
225*4882a593Smuzhiyun .set_rf_power_state = rtl88e_phy_set_rf_power_state,
226*4882a593Smuzhiyun .led_control = rtl88ee_led_control,
227*4882a593Smuzhiyun .set_desc = rtl88ee_set_desc,
228*4882a593Smuzhiyun .get_desc = rtl88ee_get_desc,
229*4882a593Smuzhiyun .is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
230*4882a593Smuzhiyun .tx_polling = rtl88ee_tx_polling,
231*4882a593Smuzhiyun .enable_hw_sec = rtl88ee_enable_hw_security_config,
232*4882a593Smuzhiyun .set_key = rtl88ee_set_key,
233*4882a593Smuzhiyun .init_sw_leds = rtl88ee_init_sw_leds,
234*4882a593Smuzhiyun .get_bbreg = rtl88e_phy_query_bb_reg,
235*4882a593Smuzhiyun .set_bbreg = rtl88e_phy_set_bb_reg,
236*4882a593Smuzhiyun .get_rfreg = rtl88e_phy_query_rf_reg,
237*4882a593Smuzhiyun .set_rfreg = rtl88e_phy_set_rf_reg,
238*4882a593Smuzhiyun .get_btc_status = rtl88e_get_btc_status,
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun static struct rtl_mod_params rtl88ee_mod_params = {
242*4882a593Smuzhiyun .sw_crypto = false,
243*4882a593Smuzhiyun .inactiveps = true,
244*4882a593Smuzhiyun .swctrl_lps = false,
245*4882a593Smuzhiyun .fwctrl_lps = false,
246*4882a593Smuzhiyun .msi_support = true,
247*4882a593Smuzhiyun .aspm_support = 1,
248*4882a593Smuzhiyun .debug_level = 0,
249*4882a593Smuzhiyun .debug_mask = 0,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static const struct rtl_hal_cfg rtl88ee_hal_cfg = {
253*4882a593Smuzhiyun .bar_id = 2,
254*4882a593Smuzhiyun .write_readback = true,
255*4882a593Smuzhiyun .name = "rtl88e_pci",
256*4882a593Smuzhiyun .ops = &rtl8188ee_hal_ops,
257*4882a593Smuzhiyun .mod_params = &rtl88ee_mod_params,
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
260*4882a593Smuzhiyun .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
261*4882a593Smuzhiyun .maps[SYS_CLK] = REG_SYS_CLKR,
262*4882a593Smuzhiyun .maps[MAC_RCR_AM] = AM,
263*4882a593Smuzhiyun .maps[MAC_RCR_AB] = AB,
264*4882a593Smuzhiyun .maps[MAC_RCR_ACRC32] = ACRC32,
265*4882a593Smuzhiyun .maps[MAC_RCR_ACF] = ACF,
266*4882a593Smuzhiyun .maps[MAC_RCR_AAP] = AAP,
267*4882a593Smuzhiyun .maps[MAC_HIMR] = REG_HIMR,
268*4882a593Smuzhiyun .maps[MAC_HIMRE] = REG_HIMRE,
269*4882a593Smuzhiyun .maps[MAC_HSISR] = REG_HSISR,
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun .maps[EFUSE_TEST] = REG_EFUSE_TEST,
274*4882a593Smuzhiyun .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
275*4882a593Smuzhiyun .maps[EFUSE_CLK] = 0,
276*4882a593Smuzhiyun .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
277*4882a593Smuzhiyun .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
278*4882a593Smuzhiyun .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
279*4882a593Smuzhiyun .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
280*4882a593Smuzhiyun .maps[EFUSE_ANA8M] = ANA8M,
281*4882a593Smuzhiyun .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
282*4882a593Smuzhiyun .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
283*4882a593Smuzhiyun .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
284*4882a593Smuzhiyun .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun .maps[RWCAM] = REG_CAMCMD,
287*4882a593Smuzhiyun .maps[WCAMI] = REG_CAMWRITE,
288*4882a593Smuzhiyun .maps[RCAMO] = REG_CAMREAD,
289*4882a593Smuzhiyun .maps[CAMDBG] = REG_CAMDBG,
290*4882a593Smuzhiyun .maps[SECR] = REG_SECCFG,
291*4882a593Smuzhiyun .maps[SEC_CAM_NONE] = CAM_NONE,
292*4882a593Smuzhiyun .maps[SEC_CAM_WEP40] = CAM_WEP40,
293*4882a593Smuzhiyun .maps[SEC_CAM_TKIP] = CAM_TKIP,
294*4882a593Smuzhiyun .maps[SEC_CAM_AES] = CAM_AES,
295*4882a593Smuzhiyun .maps[SEC_CAM_WEP104] = CAM_WEP104,
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
298*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
299*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
300*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
301*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
302*4882a593Smuzhiyun .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
303*4882a593Smuzhiyun /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
304*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
305*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
306*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
307*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
308*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
309*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
310*4882a593Smuzhiyun .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
311*4882a593Smuzhiyun /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
312*4882a593Smuzhiyun /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
315*4882a593Smuzhiyun .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
316*4882a593Smuzhiyun .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
317*4882a593Smuzhiyun .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
318*4882a593Smuzhiyun .maps[RTL_IMR_RDU] = IMR_RDU,
319*4882a593Smuzhiyun .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
320*4882a593Smuzhiyun .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
321*4882a593Smuzhiyun .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
322*4882a593Smuzhiyun .maps[RTL_IMR_TBDER] = IMR_TBDER,
323*4882a593Smuzhiyun .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
324*4882a593Smuzhiyun .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
325*4882a593Smuzhiyun .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
326*4882a593Smuzhiyun .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
327*4882a593Smuzhiyun .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
328*4882a593Smuzhiyun .maps[RTL_IMR_VODOK] = IMR_VODOK,
329*4882a593Smuzhiyun .maps[RTL_IMR_ROK] = IMR_ROK,
330*4882a593Smuzhiyun .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
331*4882a593Smuzhiyun .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
334*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
335*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
336*4882a593Smuzhiyun .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
337*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
338*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
339*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
340*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
341*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
342*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
343*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
344*4882a593Smuzhiyun .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
347*4882a593Smuzhiyun .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun static const struct pci_device_id rtl88ee_pci_ids[] = {
351*4882a593Smuzhiyun {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
352*4882a593Smuzhiyun {},
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>");
358*4882a593Smuzhiyun MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
359*4882a593Smuzhiyun MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
360*4882a593Smuzhiyun MODULE_LICENSE("GPL");
361*4882a593Smuzhiyun MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
362*4882a593Smuzhiyun MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
365*4882a593Smuzhiyun module_param_named(debug_level, rtl88ee_mod_params.debug_level, int, 0644);
366*4882a593Smuzhiyun module_param_named(debug_mask, rtl88ee_mod_params.debug_mask, ullong, 0644);
367*4882a593Smuzhiyun module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
368*4882a593Smuzhiyun module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
369*4882a593Smuzhiyun module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
370*4882a593Smuzhiyun module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
371*4882a593Smuzhiyun module_param_named(aspm, rtl88ee_mod_params.aspm_support, int, 0444);
372*4882a593Smuzhiyun module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
373*4882a593Smuzhiyun bool, 0444);
374*4882a593Smuzhiyun MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
375*4882a593Smuzhiyun MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
376*4882a593Smuzhiyun MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
377*4882a593Smuzhiyun MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
378*4882a593Smuzhiyun MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
379*4882a593Smuzhiyun MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
380*4882a593Smuzhiyun MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
381*4882a593Smuzhiyun MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
382*4882a593Smuzhiyun MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun static struct pci_driver rtl88ee_driver = {
387*4882a593Smuzhiyun .name = KBUILD_MODNAME,
388*4882a593Smuzhiyun .id_table = rtl88ee_pci_ids,
389*4882a593Smuzhiyun .probe = rtl_pci_probe,
390*4882a593Smuzhiyun .remove = rtl_pci_disconnect,
391*4882a593Smuzhiyun .driver.pm = &rtlwifi_pm_ops,
392*4882a593Smuzhiyun };
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun module_pci_driver(rtl88ee_driver);
395