1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL8723E_PWRSEQCMD_H__ 5*4882a593Smuzhiyun #define __RTL8723E_PWRSEQCMD_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "wifi.h" 8*4882a593Smuzhiyun /*--------------------------------------------- 9*4882a593Smuzhiyun * 3 The value of cmd: 4 bits 10*4882a593Smuzhiyun *--------------------------------------------- 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #define PWR_CMD_READ 0x00 13*4882a593Smuzhiyun #define PWR_CMD_WRITE 0x01 14*4882a593Smuzhiyun #define PWR_CMD_POLLING 0x02 15*4882a593Smuzhiyun #define PWR_CMD_DELAY 0x03 16*4882a593Smuzhiyun #define PWR_CMD_END 0x04 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* define the base address of each block */ 19*4882a593Smuzhiyun #define PWR_BASEADDR_MAC 0x00 20*4882a593Smuzhiyun #define PWR_BASEADDR_USB 0x01 21*4882a593Smuzhiyun #define PWR_BASEADDR_PCIE 0x02 22*4882a593Smuzhiyun #define PWR_BASEADDR_SDIO 0x03 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PWR_INTF_SDIO_MSK BIT(0) 25*4882a593Smuzhiyun #define PWR_INTF_USB_MSK BIT(1) 26*4882a593Smuzhiyun #define PWR_INTF_PCI_MSK BIT(2) 27*4882a593Smuzhiyun #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PWR_FAB_TSMC_MSK BIT(0) 30*4882a593Smuzhiyun #define PWR_FAB_UMC_MSK BIT(1) 31*4882a593Smuzhiyun #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define PWR_CUT_TESTCHIP_MSK BIT(0) 34*4882a593Smuzhiyun #define PWR_CUT_A_MSK BIT(1) 35*4882a593Smuzhiyun #define PWR_CUT_B_MSK BIT(2) 36*4882a593Smuzhiyun #define PWR_CUT_C_MSK BIT(3) 37*4882a593Smuzhiyun #define PWR_CUT_D_MSK BIT(4) 38*4882a593Smuzhiyun #define PWR_CUT_E_MSK BIT(5) 39*4882a593Smuzhiyun #define PWR_CUT_F_MSK BIT(6) 40*4882a593Smuzhiyun #define PWR_CUT_G_MSK BIT(7) 41*4882a593Smuzhiyun #define PWR_CUT_ALL_MSK 0xFF 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun enum pwrseq_delay_unit { 44*4882a593Smuzhiyun PWRSEQ_DELAY_US, 45*4882a593Smuzhiyun PWRSEQ_DELAY_MS, 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct wlan_pwr_cfg { 49*4882a593Smuzhiyun u16 offset; 50*4882a593Smuzhiyun u8 cut_msk; 51*4882a593Smuzhiyun u8 fab_msk:4; 52*4882a593Smuzhiyun u8 interface_msk:4; 53*4882a593Smuzhiyun u8 base:4; 54*4882a593Smuzhiyun u8 cmd:4; 55*4882a593Smuzhiyun u8 msk; 56*4882a593Smuzhiyun u8 value; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset) 60*4882a593Smuzhiyun #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk) 61*4882a593Smuzhiyun #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk) 62*4882a593Smuzhiyun #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk) 63*4882a593Smuzhiyun #define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base) 64*4882a593Smuzhiyun #define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd) 65*4882a593Smuzhiyun #define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk) 66*4882a593Smuzhiyun #define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, 69*4882a593Smuzhiyun u8 fab_version, u8 interface_type, 70*4882a593Smuzhiyun struct wlan_pwr_cfg pwrcfgcmd[]); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif 73