1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __RTL_EFUSE_H_ 5*4882a593Smuzhiyun #define __RTL_EFUSE_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define EFUSE_IC_ID_OFFSET 506 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define EFUSE_MAX_WORD_UNIT 4 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define EFUSE_INIT_MAP 0 12*4882a593Smuzhiyun #define EFUSE_MODIFY_MAP 1 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define PG_STATE_HEADER 0x01 15*4882a593Smuzhiyun #define PG_STATE_WORD_0 0x02 16*4882a593Smuzhiyun #define PG_STATE_WORD_1 0x04 17*4882a593Smuzhiyun #define PG_STATE_WORD_2 0x08 18*4882a593Smuzhiyun #define PG_STATE_WORD_3 0x10 19*4882a593Smuzhiyun #define PG_STATE_DATA 0x20 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define EFUSE_REPEAT_THRESHOLD_ 3 22*4882a593Smuzhiyun #define EFUSE_ERROE_HANDLE 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct efuse_map { 25*4882a593Smuzhiyun u8 offset; 26*4882a593Smuzhiyun u8 word_start; 27*4882a593Smuzhiyun u8 byte_start; 28*4882a593Smuzhiyun u8 byte_cnts; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct pgpkt_struct { 32*4882a593Smuzhiyun u8 offset; 33*4882a593Smuzhiyun u8 word_en; 34*4882a593Smuzhiyun u8 data[8]; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun enum efuse_data_item { 38*4882a593Smuzhiyun EFUSE_CHIP_ID = 0, 39*4882a593Smuzhiyun EFUSE_LDO_SETTING, 40*4882a593Smuzhiyun EFUSE_CLK_SETTING, 41*4882a593Smuzhiyun EFUSE_SDIO_SETTING, 42*4882a593Smuzhiyun EFUSE_CCCR, 43*4882a593Smuzhiyun EFUSE_SDIO_MODE, 44*4882a593Smuzhiyun EFUSE_OCR, 45*4882a593Smuzhiyun EFUSE_F0CIS, 46*4882a593Smuzhiyun EFUSE_F1CIS, 47*4882a593Smuzhiyun EFUSE_MAC_ADDR, 48*4882a593Smuzhiyun EFUSE_EEPROM_VER, 49*4882a593Smuzhiyun EFUSE_CHAN_PLAN, 50*4882a593Smuzhiyun EFUSE_TXPW_TAB 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun enum { 54*4882a593Smuzhiyun VOLTAGE_V25 = 0x03, 55*4882a593Smuzhiyun LDOE25_SHIFT = 28, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct efuse_priv { 59*4882a593Smuzhiyun u8 id[2]; 60*4882a593Smuzhiyun u8 ldo_setting[2]; 61*4882a593Smuzhiyun u8 clk_setting[2]; 62*4882a593Smuzhiyun u8 cccr; 63*4882a593Smuzhiyun u8 sdio_mode; 64*4882a593Smuzhiyun u8 ocr[3]; 65*4882a593Smuzhiyun u8 cis0[17]; 66*4882a593Smuzhiyun u8 cis1[48]; 67*4882a593Smuzhiyun u8 mac_addr[6]; 68*4882a593Smuzhiyun u8 eeprom_verno; 69*4882a593Smuzhiyun u8 channel_plan; 70*4882a593Smuzhiyun u8 tx_power_b[14]; 71*4882a593Smuzhiyun u8 tx_power_g[14]; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 75*4882a593Smuzhiyun void efuse_initialize(struct ieee80211_hw *hw); 76*4882a593Smuzhiyun u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address); 77*4882a593Smuzhiyun int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data); 78*4882a593Smuzhiyun void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value); 79*4882a593Smuzhiyun void read_efuse(struct ieee80211_hw *hw, u16 _offset, 80*4882a593Smuzhiyun u16 _size_byte, u8 *pbuf); 81*4882a593Smuzhiyun void efuse_shadow_read(struct ieee80211_hw *hw, u8 type, 82*4882a593Smuzhiyun u16 offset, u32 *value); 83*4882a593Smuzhiyun void efuse_shadow_write(struct ieee80211_hw *hw, u8 type, 84*4882a593Smuzhiyun u16 offset, u32 value); 85*4882a593Smuzhiyun bool efuse_shadow_update(struct ieee80211_hw *hw); 86*4882a593Smuzhiyun bool efuse_shadow_update_chk(struct ieee80211_hw *hw); 87*4882a593Smuzhiyun void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw); 88*4882a593Smuzhiyun void efuse_force_write_vendor_id(struct ieee80211_hw *hw); 89*4882a593Smuzhiyun void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx); 90*4882a593Smuzhiyun void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate); 91*4882a593Smuzhiyun int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, 92*4882a593Smuzhiyun int max_size, u8 *hwinfo, int *params); 93*4882a593Smuzhiyun void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen); 94*4882a593Smuzhiyun void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, const u8 *buffer, 95*4882a593Smuzhiyun u32 size); 96*4882a593Smuzhiyun void rtl_fw_block_write(struct ieee80211_hw *hw, const u8 *buffer, u32 size); 97*4882a593Smuzhiyun void rtl_efuse_ops_init(struct ieee80211_hw *hw); 98*4882a593Smuzhiyun #endif 99