xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/debug.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright(c) 2009-2012  Realtek Corporation.*/
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #ifndef __RTL_DEBUG_H__
5*4882a593Smuzhiyun #define __RTL_DEBUG_H__
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun /*--------------------------------------------------------------
8*4882a593Smuzhiyun 			Debug level
9*4882a593Smuzhiyun --------------------------------------------------------------*/
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun  *Fatal bug.
12*4882a593Smuzhiyun  *For example, Tx/Rx/IO locked up,
13*4882a593Smuzhiyun  *memory access violation,
14*4882a593Smuzhiyun  *resource allocation failed,
15*4882a593Smuzhiyun  *unexpected HW behavior, HW BUG
16*4882a593Smuzhiyun  *and so on.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun /*#define DBG_EMERG			0 */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  *Abnormal, rare, or unexpeted cases.
22*4882a593Smuzhiyun  *For example, Packet/IO Ctl canceled,
23*4882a593Smuzhiyun  *device suprisely unremoved and so on.
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun #define	DBG_WARNING			2
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun  *Normal case driver developer should
29*4882a593Smuzhiyun  *open, we can see link status like
30*4882a593Smuzhiyun  *assoc/AddBA/DHCP/adapter start and
31*4882a593Smuzhiyun  *so on basic and useful infromations.
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun #define DBG_DMESG			3
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  *Normal case with useful information
37*4882a593Smuzhiyun  *about current SW or HW state.
38*4882a593Smuzhiyun  *For example, Tx/Rx descriptor to fill,
39*4882a593Smuzhiyun  *Tx/Rx descriptor completed status,
40*4882a593Smuzhiyun  *SW protocol state change, dynamic
41*4882a593Smuzhiyun  *mechanism state change and so on.
42*4882a593Smuzhiyun  */
43*4882a593Smuzhiyun #define DBG_LOUD			4
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun  *Normal case with detail execution
47*4882a593Smuzhiyun  *flow or information.
48*4882a593Smuzhiyun  */
49*4882a593Smuzhiyun #define	DBG_TRACE			5
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /*--------------------------------------------------------------
52*4882a593Smuzhiyun 		Define the rt_trace components
53*4882a593Smuzhiyun --------------------------------------------------------------*/
54*4882a593Smuzhiyun #define COMP_ERR			BIT(0)
55*4882a593Smuzhiyun #define COMP_FW				BIT(1)
56*4882a593Smuzhiyun #define COMP_INIT			BIT(2)	/*For init/deinit */
57*4882a593Smuzhiyun #define COMP_RECV			BIT(3)	/*For Rx. */
58*4882a593Smuzhiyun #define COMP_SEND			BIT(4)	/*For Tx. */
59*4882a593Smuzhiyun #define COMP_MLME			BIT(5)	/*For MLME. */
60*4882a593Smuzhiyun #define COMP_SCAN			BIT(6)	/*For Scan. */
61*4882a593Smuzhiyun #define COMP_INTR			BIT(7)	/*For interrupt Related. */
62*4882a593Smuzhiyun #define COMP_LED			BIT(8)	/*For LED. */
63*4882a593Smuzhiyun #define COMP_SEC			BIT(9)	/*For sec. */
64*4882a593Smuzhiyun #define COMP_BEACON			BIT(10)	/*For beacon. */
65*4882a593Smuzhiyun #define COMP_RATE			BIT(11)	/*For rate. */
66*4882a593Smuzhiyun #define COMP_RXDESC			BIT(12)	/*For rx desc. */
67*4882a593Smuzhiyun #define COMP_DIG			BIT(13)	/*For DIG */
68*4882a593Smuzhiyun #define COMP_TXAGC			BIT(14)	/*For Tx power */
69*4882a593Smuzhiyun #define COMP_HIPWR			BIT(15)	/*For High Power Mechanism */
70*4882a593Smuzhiyun #define COMP_POWER			BIT(16)	/*For lps/ips/aspm. */
71*4882a593Smuzhiyun #define COMP_POWER_TRACKING	BIT(17)	/*For TX POWER TRACKING */
72*4882a593Smuzhiyun #define COMP_BB_POWERSAVING	BIT(18)
73*4882a593Smuzhiyun #define COMP_SWAS			BIT(19)	/*For SW Antenna Switch */
74*4882a593Smuzhiyun #define COMP_RF				BIT(20)	/*For RF. */
75*4882a593Smuzhiyun #define COMP_TURBO			BIT(21)	/*For EDCA TURBO. */
76*4882a593Smuzhiyun #define COMP_RATR			BIT(22)
77*4882a593Smuzhiyun #define COMP_CMD			BIT(23)
78*4882a593Smuzhiyun #define COMP_EFUSE			BIT(24)
79*4882a593Smuzhiyun #define COMP_QOS			BIT(25)
80*4882a593Smuzhiyun #define COMP_MAC80211		BIT(26)
81*4882a593Smuzhiyun #define COMP_REGD			BIT(27)
82*4882a593Smuzhiyun #define COMP_CHAN			BIT(28)
83*4882a593Smuzhiyun #define COMP_USB			BIT(29)
84*4882a593Smuzhiyun #define COMP_EASY_CONCURRENT	COMP_USB /* reuse of this bit is OK */
85*4882a593Smuzhiyun #define COMP_BT_COEXIST			BIT(30)
86*4882a593Smuzhiyun #define COMP_IQK			BIT(31)
87*4882a593Smuzhiyun #define COMP_TX_REPORT			BIT_ULL(32)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /*--------------------------------------------------------------
90*4882a593Smuzhiyun 		Define the rt_print components
91*4882a593Smuzhiyun --------------------------------------------------------------*/
92*4882a593Smuzhiyun /* Define EEPROM and EFUSE  check module bit*/
93*4882a593Smuzhiyun #define EEPROM_W			BIT(0)
94*4882a593Smuzhiyun #define EFUSE_PG			BIT(1)
95*4882a593Smuzhiyun #define EFUSE_READ_ALL			BIT(2)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* Define init check for module bit*/
98*4882a593Smuzhiyun #define	INIT_EEPROM			BIT(0)
99*4882a593Smuzhiyun #define	INIT_TXPOWER			BIT(1)
100*4882a593Smuzhiyun #define	INIT_IQK			BIT(2)
101*4882a593Smuzhiyun #define	INIT_RF				BIT(3)
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* Define PHY-BB/RF/MAC check module bit */
104*4882a593Smuzhiyun #define	PHY_BBR				BIT(0)
105*4882a593Smuzhiyun #define	PHY_BBW				BIT(1)
106*4882a593Smuzhiyun #define	PHY_RFR				BIT(2)
107*4882a593Smuzhiyun #define	PHY_RFW				BIT(3)
108*4882a593Smuzhiyun #define	PHY_MACR			BIT(4)
109*4882a593Smuzhiyun #define	PHY_MACW			BIT(5)
110*4882a593Smuzhiyun #define	PHY_ALLR			BIT(6)
111*4882a593Smuzhiyun #define	PHY_ALLW			BIT(7)
112*4882a593Smuzhiyun #define	PHY_TXPWR			BIT(8)
113*4882a593Smuzhiyun #define	PHY_PWRDIFF			BIT(9)
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* Define Dynamic Mechanism check module bit --> FDM */
116*4882a593Smuzhiyun #define WA_IOT				BIT(0)
117*4882a593Smuzhiyun #define DM_PWDB				BIT(1)
118*4882a593Smuzhiyun #define DM_MONITOR			BIT(2)
119*4882a593Smuzhiyun #define DM_DIG				BIT(3)
120*4882a593Smuzhiyun #define DM_EDCA_TURBO			BIT(4)
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun #define DM_PWDB				BIT(1)
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun enum dbgp_flag_e {
125*4882a593Smuzhiyun 	FQOS = 0,
126*4882a593Smuzhiyun 	FTX = 1,
127*4882a593Smuzhiyun 	FRX = 2,
128*4882a593Smuzhiyun 	FSEC = 3,
129*4882a593Smuzhiyun 	FMGNT = 4,
130*4882a593Smuzhiyun 	FMLME = 5,
131*4882a593Smuzhiyun 	FRESOURCE = 6,
132*4882a593Smuzhiyun 	FBEACON = 7,
133*4882a593Smuzhiyun 	FISR = 8,
134*4882a593Smuzhiyun 	FPHY = 9,
135*4882a593Smuzhiyun 	FMP = 10,
136*4882a593Smuzhiyun 	FEEPROM = 11,
137*4882a593Smuzhiyun 	FPWR = 12,
138*4882a593Smuzhiyun 	FDM = 13,
139*4882a593Smuzhiyun 	FDBGCTRL = 14,
140*4882a593Smuzhiyun 	FC2H = 15,
141*4882a593Smuzhiyun 	FBT = 16,
142*4882a593Smuzhiyun 	FINIT = 17,
143*4882a593Smuzhiyun 	FIOCTL = 18,
144*4882a593Smuzhiyun 	DBGP_TYPE_MAX
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun #ifdef CONFIG_RTLWIFI_DEBUG
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun struct rtl_priv;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun __printf(4, 5)
152*4882a593Smuzhiyun void _rtl_dbg_print(struct rtl_priv *rtlpriv, u64 comp, int level,
153*4882a593Smuzhiyun 		    const char *fmt, ...);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level,
156*4882a593Smuzhiyun 			 const char *titlestring,
157*4882a593Smuzhiyun 			 const void *hexdata, int hexdatalen);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun #define rtl_dbg(rtlpriv, comp, level, fmt, ...)				\
160*4882a593Smuzhiyun 	_rtl_dbg_print(rtlpriv, comp, level,				\
161*4882a593Smuzhiyun 		       fmt, ##__VA_ARGS__)
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun #define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...)			\
164*4882a593Smuzhiyun 	_rtl_dbg_print(rtlpriv, dbgtype, dbgflag, fmt, ##__VA_ARGS__)
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata,	\
167*4882a593Smuzhiyun 		      _hexdatalen)					\
168*4882a593Smuzhiyun 	_rtl_dbg_print_data(rtlpriv, _comp, _level,			\
169*4882a593Smuzhiyun 			    _titlestring, _hexdata, _hexdatalen)
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #else
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun struct rtl_priv;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun __printf(4, 5)
rtl_dbg(struct rtl_priv * rtlpriv,u64 comp,int level,const char * fmt,...)176*4882a593Smuzhiyun static inline void rtl_dbg(struct rtl_priv *rtlpriv,
177*4882a593Smuzhiyun 			   u64 comp, int level,
178*4882a593Smuzhiyun 			   const char *fmt, ...)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun __printf(4, 5)
RTPRINT(struct rtl_priv * rtlpriv,int dbgtype,int dbgflag,const char * fmt,...)183*4882a593Smuzhiyun static inline void RTPRINT(struct rtl_priv *rtlpriv,
184*4882a593Smuzhiyun 			   int dbgtype, int dbgflag,
185*4882a593Smuzhiyun 			   const char *fmt, ...)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
RT_PRINT_DATA(struct rtl_priv * rtlpriv,u64 comp,int level,const char * titlestring,const void * hexdata,size_t hexdatalen)189*4882a593Smuzhiyun static inline void RT_PRINT_DATA(struct rtl_priv *rtlpriv,
190*4882a593Smuzhiyun 				 u64 comp, int level,
191*4882a593Smuzhiyun 				 const char *titlestring,
192*4882a593Smuzhiyun 				 const void *hexdata, size_t hexdatalen)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun #endif
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #ifdef CONFIG_RTLWIFI_DEBUG
199*4882a593Smuzhiyun void rtl_debug_add_one(struct ieee80211_hw *hw);
200*4882a593Smuzhiyun void rtl_debug_remove_one(struct ieee80211_hw *hw);
201*4882a593Smuzhiyun void rtl_debugfs_add_topdir(void);
202*4882a593Smuzhiyun void rtl_debugfs_remove_topdir(void);
203*4882a593Smuzhiyun #else
204*4882a593Smuzhiyun #define rtl_debug_add_one(hw)
205*4882a593Smuzhiyun #define rtl_debug_remove_one(hw)
206*4882a593Smuzhiyun #define rtl_debugfs_add_topdir()
207*4882a593Smuzhiyun #define rtl_debugfs_remove_topdir()
208*4882a593Smuzhiyun #endif
209*4882a593Smuzhiyun #endif
210