1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Definitions for RTL8187 hardware
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6*4882a593Smuzhiyun * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Based on the r8187 driver, which is:
9*4882a593Smuzhiyun * Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef RTL8187_H
13*4882a593Smuzhiyun #define RTL8187_H
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/cache.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "rtl818x.h"
18*4882a593Smuzhiyun #include "leds.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define RTL8187_EEPROM_TXPWR_BASE 0x05
21*4882a593Smuzhiyun #define RTL8187_EEPROM_MAC_ADDR 0x07
22*4882a593Smuzhiyun #define RTL8187_EEPROM_TXPWR_CHAN_1 0x16 /* 3 channels */
23*4882a593Smuzhiyun #define RTL8187_EEPROM_TXPWR_CHAN_6 0x1B /* 2 channels */
24*4882a593Smuzhiyun #define RTL8187_EEPROM_TXPWR_CHAN_4 0x3D /* 2 channels */
25*4882a593Smuzhiyun #define RTL8187_EEPROM_SELECT_GPIO 0x3B
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define RTL8187_REQT_READ 0xC0
28*4882a593Smuzhiyun #define RTL8187_REQT_WRITE 0x40
29*4882a593Smuzhiyun #define RTL8187_REQ_GET_REG 0x05
30*4882a593Smuzhiyun #define RTL8187_REQ_SET_REG 0x05
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define RTL8187_MAX_RX 0x9C4
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define RFKILL_MASK_8187_89_97 0x2
35*4882a593Smuzhiyun #define RFKILL_MASK_8198 0x4
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define RETRY_COUNT 7
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct rtl8187_rx_info {
40*4882a593Smuzhiyun struct urb *urb;
41*4882a593Smuzhiyun struct ieee80211_hw *dev;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct rtl8187_rx_hdr {
45*4882a593Smuzhiyun __le32 flags;
46*4882a593Smuzhiyun u8 noise;
47*4882a593Smuzhiyun u8 signal;
48*4882a593Smuzhiyun u8 agc;
49*4882a593Smuzhiyun u8 reserved;
50*4882a593Smuzhiyun __le64 mac_time;
51*4882a593Smuzhiyun } __packed;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct rtl8187b_rx_hdr {
54*4882a593Smuzhiyun __le32 flags;
55*4882a593Smuzhiyun __le64 mac_time;
56*4882a593Smuzhiyun u8 sq;
57*4882a593Smuzhiyun u8 rssi;
58*4882a593Smuzhiyun u8 agc;
59*4882a593Smuzhiyun u8 flags2;
60*4882a593Smuzhiyun __le16 snr_long2end;
61*4882a593Smuzhiyun s8 pwdb_g12;
62*4882a593Smuzhiyun u8 fot;
63*4882a593Smuzhiyun } __packed;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* {rtl8187,rtl8187b}_tx_info is in skb */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct rtl8187_tx_hdr {
68*4882a593Smuzhiyun __le32 flags;
69*4882a593Smuzhiyun __le16 rts_duration;
70*4882a593Smuzhiyun __le16 len;
71*4882a593Smuzhiyun __le32 retry;
72*4882a593Smuzhiyun } __packed;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct rtl8187b_tx_hdr {
75*4882a593Smuzhiyun __le32 flags;
76*4882a593Smuzhiyun __le16 rts_duration;
77*4882a593Smuzhiyun __le16 len;
78*4882a593Smuzhiyun __le32 unused_1;
79*4882a593Smuzhiyun __le16 unused_2;
80*4882a593Smuzhiyun __le16 tx_duration;
81*4882a593Smuzhiyun __le32 unused_3;
82*4882a593Smuzhiyun __le32 retry;
83*4882a593Smuzhiyun __le32 unused_4[2];
84*4882a593Smuzhiyun } __packed;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun enum {
87*4882a593Smuzhiyun DEVICE_RTL8187,
88*4882a593Smuzhiyun DEVICE_RTL8187B
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct rtl8187_vif {
92*4882a593Smuzhiyun struct ieee80211_hw *dev;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* beaconing */
95*4882a593Smuzhiyun struct delayed_work beacon_work;
96*4882a593Smuzhiyun bool enable_beacon;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct rtl8187_priv {
100*4882a593Smuzhiyun /* common between rtl818x drivers */
101*4882a593Smuzhiyun struct rtl818x_csr *map;
102*4882a593Smuzhiyun const struct rtl818x_rf_ops *rf;
103*4882a593Smuzhiyun struct ieee80211_vif *vif;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* The mutex protects the TX loopback state.
106*4882a593Smuzhiyun * Any attempt to set channels concurrently locks the device.
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun struct mutex conf_mutex;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* rtl8187 specific */
111*4882a593Smuzhiyun struct ieee80211_channel channels[14];
112*4882a593Smuzhiyun struct ieee80211_rate rates[12];
113*4882a593Smuzhiyun struct ieee80211_supported_band band;
114*4882a593Smuzhiyun struct usb_device *udev;
115*4882a593Smuzhiyun u32 rx_conf;
116*4882a593Smuzhiyun struct usb_anchor anchored;
117*4882a593Smuzhiyun struct delayed_work work;
118*4882a593Smuzhiyun struct ieee80211_hw *dev;
119*4882a593Smuzhiyun #ifdef CONFIG_RTL8187_LEDS
120*4882a593Smuzhiyun struct rtl8187_led led_radio;
121*4882a593Smuzhiyun struct rtl8187_led led_tx;
122*4882a593Smuzhiyun struct rtl8187_led led_rx;
123*4882a593Smuzhiyun struct delayed_work led_on;
124*4882a593Smuzhiyun struct delayed_work led_off;
125*4882a593Smuzhiyun #endif
126*4882a593Smuzhiyun u16 txpwr_base;
127*4882a593Smuzhiyun u8 asic_rev;
128*4882a593Smuzhiyun u8 is_rtl8187b;
129*4882a593Smuzhiyun enum {
130*4882a593Smuzhiyun RTL8187BvB,
131*4882a593Smuzhiyun RTL8187BvD,
132*4882a593Smuzhiyun RTL8187BvE
133*4882a593Smuzhiyun } hw_rev;
134*4882a593Smuzhiyun struct sk_buff_head rx_queue;
135*4882a593Smuzhiyun u8 signal;
136*4882a593Smuzhiyun u8 noise;
137*4882a593Smuzhiyun u8 slot_time;
138*4882a593Smuzhiyun u8 aifsn[4];
139*4882a593Smuzhiyun u8 rfkill_mask;
140*4882a593Smuzhiyun struct {
141*4882a593Smuzhiyun union {
142*4882a593Smuzhiyun __le64 buf;
143*4882a593Smuzhiyun u8 dummy1[L1_CACHE_BYTES];
144*4882a593Smuzhiyun } ____cacheline_aligned;
145*4882a593Smuzhiyun struct sk_buff_head queue;
146*4882a593Smuzhiyun } b_tx_status; /* This queue is used by both -b and non-b devices */
147*4882a593Smuzhiyun struct mutex io_mutex;
148*4882a593Smuzhiyun union {
149*4882a593Smuzhiyun u8 bits8;
150*4882a593Smuzhiyun __le16 bits16;
151*4882a593Smuzhiyun __le32 bits32;
152*4882a593Smuzhiyun u8 dummy2[L1_CACHE_BYTES];
153*4882a593Smuzhiyun } *io_dmabuf ____cacheline_aligned;
154*4882a593Smuzhiyun bool rfkill_off;
155*4882a593Smuzhiyun u16 seqno;
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun u8 rtl818x_ioread8_idx(struct rtl8187_priv *priv,
161*4882a593Smuzhiyun u8 *addr, u8 idx);
162*4882a593Smuzhiyun
rtl818x_ioread8(struct rtl8187_priv * priv,u8 * addr)163*4882a593Smuzhiyun static inline u8 rtl818x_ioread8(struct rtl8187_priv *priv, u8 *addr)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun return rtl818x_ioread8_idx(priv, addr, 0);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun u16 rtl818x_ioread16_idx(struct rtl8187_priv *priv,
169*4882a593Smuzhiyun __le16 *addr, u8 idx);
170*4882a593Smuzhiyun
rtl818x_ioread16(struct rtl8187_priv * priv,__le16 * addr)171*4882a593Smuzhiyun static inline u16 rtl818x_ioread16(struct rtl8187_priv *priv, __le16 *addr)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun return rtl818x_ioread16_idx(priv, addr, 0);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun u32 rtl818x_ioread32_idx(struct rtl8187_priv *priv,
177*4882a593Smuzhiyun __le32 *addr, u8 idx);
178*4882a593Smuzhiyun
rtl818x_ioread32(struct rtl8187_priv * priv,__le32 * addr)179*4882a593Smuzhiyun static inline u32 rtl818x_ioread32(struct rtl8187_priv *priv, __le32 *addr)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun return rtl818x_ioread32_idx(priv, addr, 0);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun void rtl818x_iowrite8_idx(struct rtl8187_priv *priv,
185*4882a593Smuzhiyun u8 *addr, u8 val, u8 idx);
186*4882a593Smuzhiyun
rtl818x_iowrite8(struct rtl8187_priv * priv,u8 * addr,u8 val)187*4882a593Smuzhiyun static inline void rtl818x_iowrite8(struct rtl8187_priv *priv, u8 *addr, u8 val)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun rtl818x_iowrite8_idx(priv, addr, val, 0);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun void rtl818x_iowrite16_idx(struct rtl8187_priv *priv,
193*4882a593Smuzhiyun __le16 *addr, u16 val, u8 idx);
194*4882a593Smuzhiyun
rtl818x_iowrite16(struct rtl8187_priv * priv,__le16 * addr,u16 val)195*4882a593Smuzhiyun static inline void rtl818x_iowrite16(struct rtl8187_priv *priv, __le16 *addr,
196*4882a593Smuzhiyun u16 val)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun rtl818x_iowrite16_idx(priv, addr, val, 0);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun void rtl818x_iowrite32_idx(struct rtl8187_priv *priv,
202*4882a593Smuzhiyun __le32 *addr, u32 val, u8 idx);
203*4882a593Smuzhiyun
rtl818x_iowrite32(struct rtl8187_priv * priv,__le32 * addr,u32 val)204*4882a593Smuzhiyun static inline void rtl818x_iowrite32(struct rtl8187_priv *priv, __le32 *addr,
205*4882a593Smuzhiyun u32 val)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun rtl818x_iowrite32_idx(priv, addr, val, 0);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun #endif /* RTL8187_H */
211