xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Linux device driver for RTL8187
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6*4882a593Smuzhiyun  * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Based on the r8187 driver, which is:
9*4882a593Smuzhiyun  * Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The driver was extended to the RTL8187B in 2008 by:
12*4882a593Smuzhiyun  *	Herton Ronaldo Krzesinski <herton@mandriva.com.br>
13*4882a593Smuzhiyun  *	Hin-Tak Leung <htl10@users.sourceforge.net>
14*4882a593Smuzhiyun  *	Larry Finger <Larry.Finger@lwfinger.net>
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * Magic delays and register offsets below are taken from the original
17*4882a593Smuzhiyun  * r8187 driver sources.  Thanks to Realtek for their support!
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/usb.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/delay.h>
23*4882a593Smuzhiyun #include <linux/etherdevice.h>
24*4882a593Smuzhiyun #include <linux/eeprom_93cx6.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <net/mac80211.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include "rtl8187.h"
29*4882a593Smuzhiyun #include "rtl8225.h"
30*4882a593Smuzhiyun #ifdef CONFIG_RTL8187_LEDS
31*4882a593Smuzhiyun #include "leds.h"
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun #include "rfkill.h"
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
36*4882a593Smuzhiyun MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
37*4882a593Smuzhiyun MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
38*4882a593Smuzhiyun MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
39*4882a593Smuzhiyun MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
40*4882a593Smuzhiyun MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
41*4882a593Smuzhiyun MODULE_LICENSE("GPL");
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static const struct usb_device_id rtl8187_table[] = {
44*4882a593Smuzhiyun 	/* Asus */
45*4882a593Smuzhiyun 	{USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
46*4882a593Smuzhiyun 	/* Belkin */
47*4882a593Smuzhiyun 	{USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
48*4882a593Smuzhiyun 	/* Realtek */
49*4882a593Smuzhiyun 	{USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
50*4882a593Smuzhiyun 	{USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
51*4882a593Smuzhiyun 	{USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
52*4882a593Smuzhiyun 	{USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
53*4882a593Smuzhiyun 	/* Surecom */
54*4882a593Smuzhiyun 	{USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
55*4882a593Smuzhiyun 	/* Logitech */
56*4882a593Smuzhiyun 	{USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
57*4882a593Smuzhiyun 	/* Netgear */
58*4882a593Smuzhiyun 	{USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
59*4882a593Smuzhiyun 	{USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
60*4882a593Smuzhiyun 	{USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
61*4882a593Smuzhiyun 	/* HP */
62*4882a593Smuzhiyun 	{USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
63*4882a593Smuzhiyun 	/* Sitecom */
64*4882a593Smuzhiyun 	{USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
65*4882a593Smuzhiyun 	{USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
66*4882a593Smuzhiyun 	{USB_DEVICE(0x0df6, 0x0029), .driver_info = DEVICE_RTL8187B},
67*4882a593Smuzhiyun 	/* Sphairon Access Systems GmbH */
68*4882a593Smuzhiyun 	{USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
69*4882a593Smuzhiyun 	/* Dick Smith Electronics */
70*4882a593Smuzhiyun 	{USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
71*4882a593Smuzhiyun 	/* Abocom */
72*4882a593Smuzhiyun 	{USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
73*4882a593Smuzhiyun 	/* Qcom */
74*4882a593Smuzhiyun 	{USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
75*4882a593Smuzhiyun 	/* AirLive */
76*4882a593Smuzhiyun 	{USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
77*4882a593Smuzhiyun 	/* Linksys */
78*4882a593Smuzhiyun 	{USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
79*4882a593Smuzhiyun 	{}
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun MODULE_DEVICE_TABLE(usb, rtl8187_table);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun static const struct ieee80211_rate rtl818x_rates[] = {
85*4882a593Smuzhiyun 	{ .bitrate = 10, .hw_value = 0, },
86*4882a593Smuzhiyun 	{ .bitrate = 20, .hw_value = 1, },
87*4882a593Smuzhiyun 	{ .bitrate = 55, .hw_value = 2, },
88*4882a593Smuzhiyun 	{ .bitrate = 110, .hw_value = 3, },
89*4882a593Smuzhiyun 	{ .bitrate = 60, .hw_value = 4, },
90*4882a593Smuzhiyun 	{ .bitrate = 90, .hw_value = 5, },
91*4882a593Smuzhiyun 	{ .bitrate = 120, .hw_value = 6, },
92*4882a593Smuzhiyun 	{ .bitrate = 180, .hw_value = 7, },
93*4882a593Smuzhiyun 	{ .bitrate = 240, .hw_value = 8, },
94*4882a593Smuzhiyun 	{ .bitrate = 360, .hw_value = 9, },
95*4882a593Smuzhiyun 	{ .bitrate = 480, .hw_value = 10, },
96*4882a593Smuzhiyun 	{ .bitrate = 540, .hw_value = 11, },
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun static const struct ieee80211_channel rtl818x_channels[] = {
100*4882a593Smuzhiyun 	{ .center_freq = 2412 },
101*4882a593Smuzhiyun 	{ .center_freq = 2417 },
102*4882a593Smuzhiyun 	{ .center_freq = 2422 },
103*4882a593Smuzhiyun 	{ .center_freq = 2427 },
104*4882a593Smuzhiyun 	{ .center_freq = 2432 },
105*4882a593Smuzhiyun 	{ .center_freq = 2437 },
106*4882a593Smuzhiyun 	{ .center_freq = 2442 },
107*4882a593Smuzhiyun 	{ .center_freq = 2447 },
108*4882a593Smuzhiyun 	{ .center_freq = 2452 },
109*4882a593Smuzhiyun 	{ .center_freq = 2457 },
110*4882a593Smuzhiyun 	{ .center_freq = 2462 },
111*4882a593Smuzhiyun 	{ .center_freq = 2467 },
112*4882a593Smuzhiyun 	{ .center_freq = 2472 },
113*4882a593Smuzhiyun 	{ .center_freq = 2484 },
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
rtl8187_iowrite_async_cb(struct urb * urb)116*4882a593Smuzhiyun static void rtl8187_iowrite_async_cb(struct urb *urb)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	kfree(urb->context);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
rtl8187_iowrite_async(struct rtl8187_priv * priv,__le16 addr,void * data,u16 len)121*4882a593Smuzhiyun static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
122*4882a593Smuzhiyun 				  void *data, u16 len)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	struct usb_ctrlrequest *dr;
125*4882a593Smuzhiyun 	struct urb *urb;
126*4882a593Smuzhiyun 	struct rtl8187_async_write_data {
127*4882a593Smuzhiyun 		u8 data[4];
128*4882a593Smuzhiyun 		struct usb_ctrlrequest dr;
129*4882a593Smuzhiyun 	} *buf;
130*4882a593Smuzhiyun 	int rc;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
133*4882a593Smuzhiyun 	if (!buf)
134*4882a593Smuzhiyun 		return;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	urb = usb_alloc_urb(0, GFP_ATOMIC);
137*4882a593Smuzhiyun 	if (!urb) {
138*4882a593Smuzhiyun 		kfree(buf);
139*4882a593Smuzhiyun 		return;
140*4882a593Smuzhiyun 	}
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	dr = &buf->dr;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	dr->bRequestType = RTL8187_REQT_WRITE;
145*4882a593Smuzhiyun 	dr->bRequest = RTL8187_REQ_SET_REG;
146*4882a593Smuzhiyun 	dr->wValue = addr;
147*4882a593Smuzhiyun 	dr->wIndex = 0;
148*4882a593Smuzhiyun 	dr->wLength = cpu_to_le16(len);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	memcpy(buf, data, len);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
153*4882a593Smuzhiyun 			     (unsigned char *)dr, buf, len,
154*4882a593Smuzhiyun 			     rtl8187_iowrite_async_cb, buf);
155*4882a593Smuzhiyun 	usb_anchor_urb(urb, &priv->anchored);
156*4882a593Smuzhiyun 	rc = usb_submit_urb(urb, GFP_ATOMIC);
157*4882a593Smuzhiyun 	if (rc < 0) {
158*4882a593Smuzhiyun 		kfree(buf);
159*4882a593Smuzhiyun 		usb_unanchor_urb(urb);
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 	usb_free_urb(urb);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
rtl818x_iowrite32_async(struct rtl8187_priv * priv,__le32 * addr,u32 val)164*4882a593Smuzhiyun static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
165*4882a593Smuzhiyun 					   __le32 *addr, u32 val)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	__le32 buf = cpu_to_le32(val);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
170*4882a593Smuzhiyun 			      &buf, sizeof(buf));
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
rtl8187_write_phy(struct ieee80211_hw * dev,u8 addr,u32 data)173*4882a593Smuzhiyun void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	data <<= 8;
178*4882a593Smuzhiyun 	data |= addr | 0x80;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
181*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
182*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
183*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
rtl8187_tx_cb(struct urb * urb)186*4882a593Smuzhiyun static void rtl8187_tx_cb(struct urb *urb)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	struct sk_buff *skb = (struct sk_buff *)urb->context;
189*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
190*4882a593Smuzhiyun 	struct ieee80211_hw *hw = info->rate_driver_data[0];
191*4882a593Smuzhiyun 	struct rtl8187_priv *priv = hw->priv;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
194*4882a593Smuzhiyun 					  sizeof(struct rtl8187_tx_hdr));
195*4882a593Smuzhiyun 	ieee80211_tx_info_clear_status(info);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
198*4882a593Smuzhiyun 		if (priv->is_rtl8187b) {
199*4882a593Smuzhiyun 			skb_queue_tail(&priv->b_tx_status.queue, skb);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 			/* queue is "full", discard last items */
202*4882a593Smuzhiyun 			while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
203*4882a593Smuzhiyun 				struct sk_buff *old_skb;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 				dev_dbg(&priv->udev->dev,
206*4882a593Smuzhiyun 					"transmit status queue full\n");
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 				old_skb = skb_dequeue(&priv->b_tx_status.queue);
209*4882a593Smuzhiyun 				ieee80211_tx_status_irqsafe(hw, old_skb);
210*4882a593Smuzhiyun 			}
211*4882a593Smuzhiyun 			return;
212*4882a593Smuzhiyun 		} else {
213*4882a593Smuzhiyun 			info->flags |= IEEE80211_TX_STAT_ACK;
214*4882a593Smuzhiyun 		}
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 	if (priv->is_rtl8187b)
217*4882a593Smuzhiyun 		ieee80211_tx_status_irqsafe(hw, skb);
218*4882a593Smuzhiyun 	else {
219*4882a593Smuzhiyun 		/* Retry information for the RTI8187 is only available by
220*4882a593Smuzhiyun 		 * reading a register in the device. We are in interrupt mode
221*4882a593Smuzhiyun 		 * here, thus queue the skb and finish on a work queue. */
222*4882a593Smuzhiyun 		skb_queue_tail(&priv->b_tx_status.queue, skb);
223*4882a593Smuzhiyun 		ieee80211_queue_delayed_work(hw, &priv->work, 0);
224*4882a593Smuzhiyun 	}
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
rtl8187_tx(struct ieee80211_hw * dev,struct ieee80211_tx_control * control,struct sk_buff * skb)227*4882a593Smuzhiyun static void rtl8187_tx(struct ieee80211_hw *dev,
228*4882a593Smuzhiyun 		       struct ieee80211_tx_control *control,
229*4882a593Smuzhiyun 		       struct sk_buff *skb)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
232*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
233*4882a593Smuzhiyun 	struct ieee80211_hdr *tx_hdr =	(struct ieee80211_hdr *)(skb->data);
234*4882a593Smuzhiyun 	unsigned int ep;
235*4882a593Smuzhiyun 	void *buf;
236*4882a593Smuzhiyun 	struct urb *urb;
237*4882a593Smuzhiyun 	__le16 rts_dur = 0;
238*4882a593Smuzhiyun 	u32 flags;
239*4882a593Smuzhiyun 	int rc;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	urb = usb_alloc_urb(0, GFP_ATOMIC);
242*4882a593Smuzhiyun 	if (!urb) {
243*4882a593Smuzhiyun 		kfree_skb(skb);
244*4882a593Smuzhiyun 		return;
245*4882a593Smuzhiyun 	}
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	flags = skb->len;
248*4882a593Smuzhiyun 	flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
251*4882a593Smuzhiyun 	if (ieee80211_has_morefrags(tx_hdr->frame_control))
252*4882a593Smuzhiyun 		flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	/* HW will perform RTS-CTS when only RTS flags is set.
255*4882a593Smuzhiyun 	 * HW will perform CTS-to-self when both RTS and CTS flags are set.
256*4882a593Smuzhiyun 	 * RTS rate and RTS duration will be used also for CTS-to-self.
257*4882a593Smuzhiyun 	 */
258*4882a593Smuzhiyun 	if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
259*4882a593Smuzhiyun 		flags |= RTL818X_TX_DESC_FLAG_RTS;
260*4882a593Smuzhiyun 		flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
261*4882a593Smuzhiyun 		rts_dur = ieee80211_rts_duration(dev, priv->vif,
262*4882a593Smuzhiyun 						 skb->len, info);
263*4882a593Smuzhiyun 	} else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
264*4882a593Smuzhiyun 		flags |= RTL818X_TX_DESC_FLAG_RTS | RTL818X_TX_DESC_FLAG_CTS;
265*4882a593Smuzhiyun 		flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
266*4882a593Smuzhiyun 		rts_dur = ieee80211_ctstoself_duration(dev, priv->vif,
267*4882a593Smuzhiyun 						 skb->len, info);
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
271*4882a593Smuzhiyun 		if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
272*4882a593Smuzhiyun 			priv->seqno += 0x10;
273*4882a593Smuzhiyun 		tx_hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
274*4882a593Smuzhiyun 		tx_hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
275*4882a593Smuzhiyun 	}
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (!priv->is_rtl8187b) {
278*4882a593Smuzhiyun 		struct rtl8187_tx_hdr *hdr = skb_push(skb, sizeof(*hdr));
279*4882a593Smuzhiyun 		hdr->flags = cpu_to_le32(flags);
280*4882a593Smuzhiyun 		hdr->len = 0;
281*4882a593Smuzhiyun 		hdr->rts_duration = rts_dur;
282*4882a593Smuzhiyun 		hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
283*4882a593Smuzhiyun 		buf = hdr;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 		ep = 2;
286*4882a593Smuzhiyun 	} else {
287*4882a593Smuzhiyun 		/* fc needs to be calculated before skb_push() */
288*4882a593Smuzhiyun 		unsigned int epmap[4] = { 6, 7, 5, 4 };
289*4882a593Smuzhiyun 		u16 fc = le16_to_cpu(tx_hdr->frame_control);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 		struct rtl8187b_tx_hdr *hdr = skb_push(skb, sizeof(*hdr));
292*4882a593Smuzhiyun 		struct ieee80211_rate *txrate =
293*4882a593Smuzhiyun 			ieee80211_get_tx_rate(dev, info);
294*4882a593Smuzhiyun 		memset(hdr, 0, sizeof(*hdr));
295*4882a593Smuzhiyun 		hdr->flags = cpu_to_le32(flags);
296*4882a593Smuzhiyun 		hdr->rts_duration = rts_dur;
297*4882a593Smuzhiyun 		hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
298*4882a593Smuzhiyun 		hdr->tx_duration =
299*4882a593Smuzhiyun 			ieee80211_generic_frame_duration(dev, priv->vif,
300*4882a593Smuzhiyun 							 info->band,
301*4882a593Smuzhiyun 							 skb->len, txrate);
302*4882a593Smuzhiyun 		buf = hdr;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 		if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
305*4882a593Smuzhiyun 			ep = 12;
306*4882a593Smuzhiyun 		else
307*4882a593Smuzhiyun 			ep = epmap[skb_get_queue_mapping(skb)];
308*4882a593Smuzhiyun 	}
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	info->rate_driver_data[0] = dev;
311*4882a593Smuzhiyun 	info->rate_driver_data[1] = urb;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
314*4882a593Smuzhiyun 			  buf, skb->len, rtl8187_tx_cb, skb);
315*4882a593Smuzhiyun 	urb->transfer_flags |= URB_ZERO_PACKET;
316*4882a593Smuzhiyun 	usb_anchor_urb(urb, &priv->anchored);
317*4882a593Smuzhiyun 	rc = usb_submit_urb(urb, GFP_ATOMIC);
318*4882a593Smuzhiyun 	if (rc < 0) {
319*4882a593Smuzhiyun 		usb_unanchor_urb(urb);
320*4882a593Smuzhiyun 		kfree_skb(skb);
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 	usb_free_urb(urb);
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun 
rtl8187_rx_cb(struct urb * urb)325*4882a593Smuzhiyun static void rtl8187_rx_cb(struct urb *urb)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun 	struct sk_buff *skb = (struct sk_buff *)urb->context;
328*4882a593Smuzhiyun 	struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
329*4882a593Smuzhiyun 	struct ieee80211_hw *dev = info->dev;
330*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
331*4882a593Smuzhiyun 	struct ieee80211_rx_status rx_status = { 0 };
332*4882a593Smuzhiyun 	int rate, signal;
333*4882a593Smuzhiyun 	u32 flags;
334*4882a593Smuzhiyun 	unsigned long f;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	spin_lock_irqsave(&priv->rx_queue.lock, f);
337*4882a593Smuzhiyun 	__skb_unlink(skb, &priv->rx_queue);
338*4882a593Smuzhiyun 	spin_unlock_irqrestore(&priv->rx_queue.lock, f);
339*4882a593Smuzhiyun 	skb_put(skb, urb->actual_length);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	if (unlikely(urb->status)) {
342*4882a593Smuzhiyun 		dev_kfree_skb_irq(skb);
343*4882a593Smuzhiyun 		return;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	if (!priv->is_rtl8187b) {
347*4882a593Smuzhiyun 		struct rtl8187_rx_hdr *hdr =
348*4882a593Smuzhiyun 			(typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
349*4882a593Smuzhiyun 		flags = le32_to_cpu(hdr->flags);
350*4882a593Smuzhiyun 		/* As with the RTL8187B below, the AGC is used to calculate
351*4882a593Smuzhiyun 		 * signal strength. In this case, the scaling
352*4882a593Smuzhiyun 		 * constants are derived from the output of p54usb.
353*4882a593Smuzhiyun 		 */
354*4882a593Smuzhiyun 		signal = -4 - ((27 * hdr->agc) >> 6);
355*4882a593Smuzhiyun 		rx_status.antenna = (hdr->signal >> 7) & 1;
356*4882a593Smuzhiyun 		rx_status.mactime = le64_to_cpu(hdr->mac_time);
357*4882a593Smuzhiyun 	} else {
358*4882a593Smuzhiyun 		struct rtl8187b_rx_hdr *hdr =
359*4882a593Smuzhiyun 			(typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
360*4882a593Smuzhiyun 		/* The Realtek datasheet for the RTL8187B shows that the RX
361*4882a593Smuzhiyun 		 * header contains the following quantities: signal quality,
362*4882a593Smuzhiyun 		 * RSSI, AGC, the received power in dB, and the measured SNR.
363*4882a593Smuzhiyun 		 * In testing, none of these quantities show qualitative
364*4882a593Smuzhiyun 		 * agreement with AP signal strength, except for the AGC,
365*4882a593Smuzhiyun 		 * which is inversely proportional to the strength of the
366*4882a593Smuzhiyun 		 * signal. In the following, the signal strength
367*4882a593Smuzhiyun 		 * is derived from the AGC. The arbitrary scaling constants
368*4882a593Smuzhiyun 		 * are chosen to make the results close to the values obtained
369*4882a593Smuzhiyun 		 * for a BCM4312 using b43 as the driver. The noise is ignored
370*4882a593Smuzhiyun 		 * for now.
371*4882a593Smuzhiyun 		 */
372*4882a593Smuzhiyun 		flags = le32_to_cpu(hdr->flags);
373*4882a593Smuzhiyun 		signal = 14 - hdr->agc / 2;
374*4882a593Smuzhiyun 		rx_status.antenna = (hdr->rssi >> 7) & 1;
375*4882a593Smuzhiyun 		rx_status.mactime = le64_to_cpu(hdr->mac_time);
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	rx_status.signal = signal;
379*4882a593Smuzhiyun 	priv->signal = signal;
380*4882a593Smuzhiyun 	rate = (flags >> 20) & 0xF;
381*4882a593Smuzhiyun 	skb_trim(skb, flags & 0x0FFF);
382*4882a593Smuzhiyun 	rx_status.rate_idx = rate;
383*4882a593Smuzhiyun 	rx_status.freq = dev->conf.chandef.chan->center_freq;
384*4882a593Smuzhiyun 	rx_status.band = dev->conf.chandef.chan->band;
385*4882a593Smuzhiyun 	rx_status.flag |= RX_FLAG_MACTIME_START;
386*4882a593Smuzhiyun 	if (flags & RTL818X_RX_DESC_FLAG_SPLCP)
387*4882a593Smuzhiyun 		rx_status.enc_flags |= RX_ENC_FLAG_SHORTPRE;
388*4882a593Smuzhiyun 	if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
389*4882a593Smuzhiyun 		rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
390*4882a593Smuzhiyun 	memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
391*4882a593Smuzhiyun 	ieee80211_rx_irqsafe(dev, skb);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	skb = dev_alloc_skb(RTL8187_MAX_RX);
394*4882a593Smuzhiyun 	if (unlikely(!skb)) {
395*4882a593Smuzhiyun 		/* TODO check rx queue length and refill *somewhere* */
396*4882a593Smuzhiyun 		return;
397*4882a593Smuzhiyun 	}
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	info = (struct rtl8187_rx_info *)skb->cb;
400*4882a593Smuzhiyun 	info->urb = urb;
401*4882a593Smuzhiyun 	info->dev = dev;
402*4882a593Smuzhiyun 	urb->transfer_buffer = skb_tail_pointer(skb);
403*4882a593Smuzhiyun 	urb->context = skb;
404*4882a593Smuzhiyun 	skb_queue_tail(&priv->rx_queue, skb);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	usb_anchor_urb(urb, &priv->anchored);
407*4882a593Smuzhiyun 	if (usb_submit_urb(urb, GFP_ATOMIC)) {
408*4882a593Smuzhiyun 		usb_unanchor_urb(urb);
409*4882a593Smuzhiyun 		skb_unlink(skb, &priv->rx_queue);
410*4882a593Smuzhiyun 		dev_kfree_skb_irq(skb);
411*4882a593Smuzhiyun 	}
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun 
rtl8187_init_urbs(struct ieee80211_hw * dev)414*4882a593Smuzhiyun static int rtl8187_init_urbs(struct ieee80211_hw *dev)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
417*4882a593Smuzhiyun 	struct urb *entry = NULL;
418*4882a593Smuzhiyun 	struct sk_buff *skb;
419*4882a593Smuzhiyun 	struct rtl8187_rx_info *info;
420*4882a593Smuzhiyun 	int ret = 0;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	while (skb_queue_len(&priv->rx_queue) < 32) {
423*4882a593Smuzhiyun 		skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
424*4882a593Smuzhiyun 		if (!skb) {
425*4882a593Smuzhiyun 			ret = -ENOMEM;
426*4882a593Smuzhiyun 			goto err;
427*4882a593Smuzhiyun 		}
428*4882a593Smuzhiyun 		entry = usb_alloc_urb(0, GFP_KERNEL);
429*4882a593Smuzhiyun 		if (!entry) {
430*4882a593Smuzhiyun 			ret = -ENOMEM;
431*4882a593Smuzhiyun 			goto err;
432*4882a593Smuzhiyun 		}
433*4882a593Smuzhiyun 		usb_fill_bulk_urb(entry, priv->udev,
434*4882a593Smuzhiyun 				  usb_rcvbulkpipe(priv->udev,
435*4882a593Smuzhiyun 				  priv->is_rtl8187b ? 3 : 1),
436*4882a593Smuzhiyun 				  skb_tail_pointer(skb),
437*4882a593Smuzhiyun 				  RTL8187_MAX_RX, rtl8187_rx_cb, skb);
438*4882a593Smuzhiyun 		info = (struct rtl8187_rx_info *)skb->cb;
439*4882a593Smuzhiyun 		info->urb = entry;
440*4882a593Smuzhiyun 		info->dev = dev;
441*4882a593Smuzhiyun 		skb_queue_tail(&priv->rx_queue, skb);
442*4882a593Smuzhiyun 		usb_anchor_urb(entry, &priv->anchored);
443*4882a593Smuzhiyun 		ret = usb_submit_urb(entry, GFP_KERNEL);
444*4882a593Smuzhiyun 		if (ret) {
445*4882a593Smuzhiyun 			skb_unlink(skb, &priv->rx_queue);
446*4882a593Smuzhiyun 			usb_unanchor_urb(entry);
447*4882a593Smuzhiyun 			usb_put_urb(entry);
448*4882a593Smuzhiyun 			goto err;
449*4882a593Smuzhiyun 		}
450*4882a593Smuzhiyun 		usb_put_urb(entry);
451*4882a593Smuzhiyun 	}
452*4882a593Smuzhiyun 	return ret;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun err:
455*4882a593Smuzhiyun 	kfree_skb(skb);
456*4882a593Smuzhiyun 	usb_kill_anchored_urbs(&priv->anchored);
457*4882a593Smuzhiyun 	return ret;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
rtl8187b_status_cb(struct urb * urb)460*4882a593Smuzhiyun static void rtl8187b_status_cb(struct urb *urb)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun 	struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
463*4882a593Smuzhiyun 	struct rtl8187_priv *priv = hw->priv;
464*4882a593Smuzhiyun 	u64 val;
465*4882a593Smuzhiyun 	unsigned int cmd_type;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	if (unlikely(urb->status))
468*4882a593Smuzhiyun 		return;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	/*
471*4882a593Smuzhiyun 	 * Read from status buffer:
472*4882a593Smuzhiyun 	 *
473*4882a593Smuzhiyun 	 * bits [30:31] = cmd type:
474*4882a593Smuzhiyun 	 * - 0 indicates tx beacon interrupt
475*4882a593Smuzhiyun 	 * - 1 indicates tx close descriptor
476*4882a593Smuzhiyun 	 *
477*4882a593Smuzhiyun 	 * In the case of tx beacon interrupt:
478*4882a593Smuzhiyun 	 * [0:9] = Last Beacon CW
479*4882a593Smuzhiyun 	 * [10:29] = reserved
480*4882a593Smuzhiyun 	 * [30:31] = 00b
481*4882a593Smuzhiyun 	 * [32:63] = Last Beacon TSF
482*4882a593Smuzhiyun 	 *
483*4882a593Smuzhiyun 	 * If it's tx close descriptor:
484*4882a593Smuzhiyun 	 * [0:7] = Packet Retry Count
485*4882a593Smuzhiyun 	 * [8:14] = RTS Retry Count
486*4882a593Smuzhiyun 	 * [15] = TOK
487*4882a593Smuzhiyun 	 * [16:27] = Sequence No
488*4882a593Smuzhiyun 	 * [28] = LS
489*4882a593Smuzhiyun 	 * [29] = FS
490*4882a593Smuzhiyun 	 * [30:31] = 01b
491*4882a593Smuzhiyun 	 * [32:47] = unused (reserved?)
492*4882a593Smuzhiyun 	 * [48:63] = MAC Used Time
493*4882a593Smuzhiyun 	 */
494*4882a593Smuzhiyun 	val = le64_to_cpu(priv->b_tx_status.buf);
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	cmd_type = (val >> 30) & 0x3;
497*4882a593Smuzhiyun 	if (cmd_type == 1) {
498*4882a593Smuzhiyun 		unsigned int pkt_rc, seq_no;
499*4882a593Smuzhiyun 		bool tok;
500*4882a593Smuzhiyun 		struct sk_buff *skb, *iter;
501*4882a593Smuzhiyun 		struct ieee80211_hdr *ieee80211hdr;
502*4882a593Smuzhiyun 		unsigned long flags;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 		pkt_rc = val & 0xFF;
505*4882a593Smuzhiyun 		tok = val & (1 << 15);
506*4882a593Smuzhiyun 		seq_no = (val >> 16) & 0xFFF;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 		spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
509*4882a593Smuzhiyun 		skb = NULL;
510*4882a593Smuzhiyun 		skb_queue_reverse_walk(&priv->b_tx_status.queue, iter) {
511*4882a593Smuzhiyun 			ieee80211hdr = (struct ieee80211_hdr *)iter->data;
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 			/*
514*4882a593Smuzhiyun 			 * While testing, it was discovered that the seq_no
515*4882a593Smuzhiyun 			 * doesn't actually contains the sequence number.
516*4882a593Smuzhiyun 			 * Instead of returning just the 12 bits of sequence
517*4882a593Smuzhiyun 			 * number, hardware is returning entire sequence control
518*4882a593Smuzhiyun 			 * (fragment number plus sequence number) in a 12 bit
519*4882a593Smuzhiyun 			 * only field overflowing after some time. As a
520*4882a593Smuzhiyun 			 * workaround, just consider the lower bits, and expect
521*4882a593Smuzhiyun 			 * it's unlikely we wrongly ack some sent data
522*4882a593Smuzhiyun 			 */
523*4882a593Smuzhiyun 			if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
524*4882a593Smuzhiyun 			     & 0xFFF) == seq_no) {
525*4882a593Smuzhiyun 				skb = iter;
526*4882a593Smuzhiyun 				break;
527*4882a593Smuzhiyun 			}
528*4882a593Smuzhiyun 		}
529*4882a593Smuzhiyun 		if (skb) {
530*4882a593Smuzhiyun 			struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 			__skb_unlink(skb, &priv->b_tx_status.queue);
533*4882a593Smuzhiyun 			if (tok)
534*4882a593Smuzhiyun 				info->flags |= IEEE80211_TX_STAT_ACK;
535*4882a593Smuzhiyun 			info->status.rates[0].count = pkt_rc + 1;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 			ieee80211_tx_status_irqsafe(hw, skb);
538*4882a593Smuzhiyun 		}
539*4882a593Smuzhiyun 		spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
540*4882a593Smuzhiyun 	}
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	usb_anchor_urb(urb, &priv->anchored);
543*4882a593Smuzhiyun 	if (usb_submit_urb(urb, GFP_ATOMIC))
544*4882a593Smuzhiyun 		usb_unanchor_urb(urb);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun 
rtl8187b_init_status_urb(struct ieee80211_hw * dev)547*4882a593Smuzhiyun static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
550*4882a593Smuzhiyun 	struct urb *entry;
551*4882a593Smuzhiyun 	int ret = 0;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	entry = usb_alloc_urb(0, GFP_KERNEL);
554*4882a593Smuzhiyun 	if (!entry)
555*4882a593Smuzhiyun 		return -ENOMEM;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
558*4882a593Smuzhiyun 			  &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
559*4882a593Smuzhiyun 			  rtl8187b_status_cb, dev);
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	usb_anchor_urb(entry, &priv->anchored);
562*4882a593Smuzhiyun 	ret = usb_submit_urb(entry, GFP_KERNEL);
563*4882a593Smuzhiyun 	if (ret)
564*4882a593Smuzhiyun 		usb_unanchor_urb(entry);
565*4882a593Smuzhiyun 	usb_free_urb(entry);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	return ret;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun 
rtl8187_set_anaparam(struct rtl8187_priv * priv,bool rfon)570*4882a593Smuzhiyun static void rtl8187_set_anaparam(struct rtl8187_priv *priv, bool rfon)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun 	u32 anaparam, anaparam2;
573*4882a593Smuzhiyun 	u8 anaparam3, reg;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	if (!priv->is_rtl8187b) {
576*4882a593Smuzhiyun 		if (rfon) {
577*4882a593Smuzhiyun 			anaparam = RTL8187_RTL8225_ANAPARAM_ON;
578*4882a593Smuzhiyun 			anaparam2 = RTL8187_RTL8225_ANAPARAM2_ON;
579*4882a593Smuzhiyun 		} else {
580*4882a593Smuzhiyun 			anaparam = RTL8187_RTL8225_ANAPARAM_OFF;
581*4882a593Smuzhiyun 			anaparam2 = RTL8187_RTL8225_ANAPARAM2_OFF;
582*4882a593Smuzhiyun 		}
583*4882a593Smuzhiyun 	} else {
584*4882a593Smuzhiyun 		if (rfon) {
585*4882a593Smuzhiyun 			anaparam = RTL8187B_RTL8225_ANAPARAM_ON;
586*4882a593Smuzhiyun 			anaparam2 = RTL8187B_RTL8225_ANAPARAM2_ON;
587*4882a593Smuzhiyun 			anaparam3 = RTL8187B_RTL8225_ANAPARAM3_ON;
588*4882a593Smuzhiyun 		} else {
589*4882a593Smuzhiyun 			anaparam = RTL8187B_RTL8225_ANAPARAM_OFF;
590*4882a593Smuzhiyun 			anaparam2 = RTL8187B_RTL8225_ANAPARAM2_OFF;
591*4882a593Smuzhiyun 			anaparam3 = RTL8187B_RTL8225_ANAPARAM3_OFF;
592*4882a593Smuzhiyun 		}
593*4882a593Smuzhiyun 	}
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
596*4882a593Smuzhiyun 			 RTL818X_EEPROM_CMD_CONFIG);
597*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
598*4882a593Smuzhiyun 	reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
599*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
600*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
601*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
602*4882a593Smuzhiyun 	if (priv->is_rtl8187b)
603*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->ANAPARAM3A, anaparam3);
604*4882a593Smuzhiyun 	reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
605*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
606*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
607*4882a593Smuzhiyun 			 RTL818X_EEPROM_CMD_NORMAL);
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun 
rtl8187_cmd_reset(struct ieee80211_hw * dev)610*4882a593Smuzhiyun static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
613*4882a593Smuzhiyun 	u8 reg;
614*4882a593Smuzhiyun 	int i;
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CMD);
617*4882a593Smuzhiyun 	reg &= (1 << 1);
618*4882a593Smuzhiyun 	reg |= RTL818X_CMD_RESET;
619*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CMD, reg);
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	i = 10;
622*4882a593Smuzhiyun 	do {
623*4882a593Smuzhiyun 		msleep(2);
624*4882a593Smuzhiyun 		if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
625*4882a593Smuzhiyun 		      RTL818X_CMD_RESET))
626*4882a593Smuzhiyun 			break;
627*4882a593Smuzhiyun 	} while (--i);
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	if (!i) {
630*4882a593Smuzhiyun 		wiphy_err(dev->wiphy, "Reset timeout!\n");
631*4882a593Smuzhiyun 		return -ETIMEDOUT;
632*4882a593Smuzhiyun 	}
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	/* reload registers from eeprom */
635*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	i = 10;
638*4882a593Smuzhiyun 	do {
639*4882a593Smuzhiyun 		msleep(4);
640*4882a593Smuzhiyun 		if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
641*4882a593Smuzhiyun 		      RTL818X_EEPROM_CMD_CONFIG))
642*4882a593Smuzhiyun 			break;
643*4882a593Smuzhiyun 	} while (--i);
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	if (!i) {
646*4882a593Smuzhiyun 		wiphy_err(dev->wiphy, "eeprom reset timeout!\n");
647*4882a593Smuzhiyun 		return -ETIMEDOUT;
648*4882a593Smuzhiyun 	}
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	return 0;
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun 
rtl8187_init_hw(struct ieee80211_hw * dev)653*4882a593Smuzhiyun static int rtl8187_init_hw(struct ieee80211_hw *dev)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
656*4882a593Smuzhiyun 	u8 reg;
657*4882a593Smuzhiyun 	int res;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	/* reset */
660*4882a593Smuzhiyun 	rtl8187_set_anaparam(priv, true);
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	msleep(200);
665*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
666*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
667*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
668*4882a593Smuzhiyun 	msleep(200);
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	res = rtl8187_cmd_reset(dev);
671*4882a593Smuzhiyun 	if (res)
672*4882a593Smuzhiyun 		return res;
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	rtl8187_set_anaparam(priv, true);
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	/* setup card */
677*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
678*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
681*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->GPIO0, 1);
682*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
687*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
688*4882a593Smuzhiyun 	reg &= 0x3F;
689*4882a593Smuzhiyun 	reg |= 0x80;
690*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
695*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
696*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun 	// TODO: set RESP_RATE and BRSR properly
699*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
700*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	/* host_usb_init */
703*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
704*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
705*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
706*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
707*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
708*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x20);
709*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
710*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
711*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
712*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
713*4882a593Smuzhiyun 	msleep(100);
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
716*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
717*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
718*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
719*4882a593Smuzhiyun 			 RTL818X_EEPROM_CMD_CONFIG);
720*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
721*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
722*4882a593Smuzhiyun 			 RTL818X_EEPROM_CMD_NORMAL);
723*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
724*4882a593Smuzhiyun 	msleep(100);
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun 	priv->rf->init(dev);
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
729*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
730*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
731*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
732*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
733*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
734*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	return 0;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun static const u8 rtl8187b_reg_table[][3] = {
740*4882a593Smuzhiyun 	{0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
741*4882a593Smuzhiyun 	{0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
742*4882a593Smuzhiyun 	{0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
743*4882a593Smuzhiyun 	{0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	{0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
746*4882a593Smuzhiyun 	{0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
747*4882a593Smuzhiyun 	{0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1},
748*4882a593Smuzhiyun 	{0xF2, 0x02, 1}, {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1},
749*4882a593Smuzhiyun 	{0xF6, 0x06, 1}, {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	{0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
752*4882a593Smuzhiyun 	{0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
753*4882a593Smuzhiyun 	{0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
754*4882a593Smuzhiyun 	{0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
755*4882a593Smuzhiyun 	{0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
756*4882a593Smuzhiyun 	{0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
757*4882a593Smuzhiyun 	{0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2},
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 	{0x5B, 0x40, 0}, {0x84, 0x88, 0}, {0x85, 0x24, 0}, {0x88, 0x54, 0},
760*4882a593Smuzhiyun 	{0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, {0x8D, 0x00, 0}, {0x94, 0x1B, 0},
761*4882a593Smuzhiyun 	{0x95, 0x12, 0}, {0x96, 0x00, 0}, {0x97, 0x06, 0}, {0x9D, 0x1A, 0},
762*4882a593Smuzhiyun 	{0x9F, 0x10, 0}, {0xB4, 0x22, 0}, {0xBE, 0x80, 0}, {0xDB, 0x00, 0},
763*4882a593Smuzhiyun 	{0xEE, 0x00, 0}, {0x4C, 0x00, 2},
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	{0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
766*4882a593Smuzhiyun 	{0x8F, 0x00, 0}
767*4882a593Smuzhiyun };
768*4882a593Smuzhiyun 
rtl8187b_init_hw(struct ieee80211_hw * dev)769*4882a593Smuzhiyun static int rtl8187b_init_hw(struct ieee80211_hw *dev)
770*4882a593Smuzhiyun {
771*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
772*4882a593Smuzhiyun 	int res, i;
773*4882a593Smuzhiyun 	u8 reg;
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun 	rtl8187_set_anaparam(priv, true);
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 	/* Reset PLL sequence on 8187B. Realtek note: reduces power
778*4882a593Smuzhiyun 	 * consumption about 30 mA */
779*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
780*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
781*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
782*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	res = rtl8187_cmd_reset(dev);
785*4882a593Smuzhiyun 	if (res)
786*4882a593Smuzhiyun 		return res;
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	rtl8187_set_anaparam(priv, true);
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun 	/* BRSR (Basic Rate Set Register) on 8187B looks to be the same as
791*4882a593Smuzhiyun 	 * RESP_RATE on 8187L in Realtek sources: each bit should be each
792*4882a593Smuzhiyun 	 * one of the 12 rates, all are enabled */
793*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
796*4882a593Smuzhiyun 	reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
797*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	/* Auto Rate Fallback Register (ARFR): 1M-54M setting */
800*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
801*4882a593Smuzhiyun 	rtl818x_iowrite8_idx(priv, (u8 *)0xFFE2, 0x00, 1);
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
806*4882a593Smuzhiyun 			 RTL818X_EEPROM_CMD_CONFIG);
807*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
808*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
809*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
810*4882a593Smuzhiyun 			 RTL818X_EEPROM_CMD_NORMAL);
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
813*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
814*4882a593Smuzhiyun 		rtl818x_iowrite8_idx(priv,
815*4882a593Smuzhiyun 				     (u8 *)(uintptr_t)
816*4882a593Smuzhiyun 				     (rtl8187b_reg_table[i][0] | 0xFF00),
817*4882a593Smuzhiyun 				     rtl8187b_reg_table[i][1],
818*4882a593Smuzhiyun 				     rtl8187b_reg_table[i][2]);
819*4882a593Smuzhiyun 	}
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
822*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun 	rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
825*4882a593Smuzhiyun 	rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
826*4882a593Smuzhiyun 	rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	/* RFSW_CTRL register */
831*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
834*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
835*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
836*4882a593Smuzhiyun 	msleep(100);
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	priv->rf->init(dev);
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
841*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CMD, reg);
842*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
845*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
846*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
847*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
848*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
849*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
850*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
853*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
854*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
855*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
856*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
857*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
858*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
859*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
860*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
861*4882a593Smuzhiyun 	rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
862*4882a593Smuzhiyun 	rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
863*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
864*4882a593Smuzhiyun 	rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 	rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	priv->slot_time = 0x9;
871*4882a593Smuzhiyun 	priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
872*4882a593Smuzhiyun 	priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
873*4882a593Smuzhiyun 	priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
874*4882a593Smuzhiyun 	priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
875*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	/* ENEDCA flag must always be set, transmit issues? */
878*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun 	return 0;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun 
rtl8187_work(struct work_struct * work)883*4882a593Smuzhiyun static void rtl8187_work(struct work_struct *work)
884*4882a593Smuzhiyun {
885*4882a593Smuzhiyun 	/* The RTL8187 returns the retry count through register 0xFFFA. In
886*4882a593Smuzhiyun 	 * addition, it appears to be a cumulative retry count, not the
887*4882a593Smuzhiyun 	 * value for the current TX packet. When multiple TX entries are
888*4882a593Smuzhiyun 	 * waiting in the queue, the retry count will be the total for all.
889*4882a593Smuzhiyun 	 * The "error" may matter for purposes of rate setting, but there is
890*4882a593Smuzhiyun 	 * no other choice with this hardware.
891*4882a593Smuzhiyun 	 */
892*4882a593Smuzhiyun 	struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
893*4882a593Smuzhiyun 				    work.work);
894*4882a593Smuzhiyun 	struct ieee80211_tx_info *info;
895*4882a593Smuzhiyun 	struct ieee80211_hw *dev = priv->dev;
896*4882a593Smuzhiyun 	static u16 retry;
897*4882a593Smuzhiyun 	u16 tmp;
898*4882a593Smuzhiyun 	u16 avg_retry;
899*4882a593Smuzhiyun 	int length;
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	mutex_lock(&priv->conf_mutex);
902*4882a593Smuzhiyun 	tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
903*4882a593Smuzhiyun 	length = skb_queue_len(&priv->b_tx_status.queue);
904*4882a593Smuzhiyun 	if (unlikely(!length))
905*4882a593Smuzhiyun 		length = 1;
906*4882a593Smuzhiyun 	if (unlikely(tmp < retry))
907*4882a593Smuzhiyun 		tmp = retry;
908*4882a593Smuzhiyun 	avg_retry = (tmp - retry) / length;
909*4882a593Smuzhiyun 	while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
910*4882a593Smuzhiyun 		struct sk_buff *old_skb;
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 		old_skb = skb_dequeue(&priv->b_tx_status.queue);
913*4882a593Smuzhiyun 		info = IEEE80211_SKB_CB(old_skb);
914*4882a593Smuzhiyun 		info->status.rates[0].count = avg_retry + 1;
915*4882a593Smuzhiyun 		if (info->status.rates[0].count > RETRY_COUNT)
916*4882a593Smuzhiyun 			info->flags &= ~IEEE80211_TX_STAT_ACK;
917*4882a593Smuzhiyun 		ieee80211_tx_status_irqsafe(dev, old_skb);
918*4882a593Smuzhiyun 	}
919*4882a593Smuzhiyun 	retry = tmp;
920*4882a593Smuzhiyun 	mutex_unlock(&priv->conf_mutex);
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun 
rtl8187_start(struct ieee80211_hw * dev)923*4882a593Smuzhiyun static int rtl8187_start(struct ieee80211_hw *dev)
924*4882a593Smuzhiyun {
925*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
926*4882a593Smuzhiyun 	u32 reg;
927*4882a593Smuzhiyun 	int ret;
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	mutex_lock(&priv->conf_mutex);
930*4882a593Smuzhiyun 
931*4882a593Smuzhiyun 	ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
932*4882a593Smuzhiyun 				     rtl8187b_init_hw(dev);
933*4882a593Smuzhiyun 	if (ret)
934*4882a593Smuzhiyun 		goto rtl8187_start_exit;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	init_usb_anchor(&priv->anchored);
937*4882a593Smuzhiyun 	priv->dev = dev;
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	if (priv->is_rtl8187b) {
940*4882a593Smuzhiyun 		reg = RTL818X_RX_CONF_MGMT |
941*4882a593Smuzhiyun 		      RTL818X_RX_CONF_DATA |
942*4882a593Smuzhiyun 		      RTL818X_RX_CONF_BROADCAST |
943*4882a593Smuzhiyun 		      RTL818X_RX_CONF_NICMAC |
944*4882a593Smuzhiyun 		      RTL818X_RX_CONF_BSSID |
945*4882a593Smuzhiyun 		      (7 << 13 /* RX FIFO threshold NONE */) |
946*4882a593Smuzhiyun 		      (7 << 10 /* MAX RX DMA */) |
947*4882a593Smuzhiyun 		      RTL818X_RX_CONF_RX_AUTORESETPHY |
948*4882a593Smuzhiyun 		      RTL818X_RX_CONF_ONLYERLPKT;
949*4882a593Smuzhiyun 		priv->rx_conf = reg;
950*4882a593Smuzhiyun 		rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 		reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
953*4882a593Smuzhiyun 		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
954*4882a593Smuzhiyun 		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
955*4882a593Smuzhiyun 		reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
956*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 		rtl818x_iowrite32(priv, &priv->map->TX_CONF,
959*4882a593Smuzhiyun 				  RTL818X_TX_CONF_HW_SEQNUM |
960*4882a593Smuzhiyun 				  RTL818X_TX_CONF_DISREQQSIZE |
961*4882a593Smuzhiyun 				  (RETRY_COUNT << 8  /* short retry limit */) |
962*4882a593Smuzhiyun 				  (RETRY_COUNT << 0  /* long retry limit */) |
963*4882a593Smuzhiyun 				  (7 << 21 /* MAX TX DMA */));
964*4882a593Smuzhiyun 		ret = rtl8187_init_urbs(dev);
965*4882a593Smuzhiyun 		if (ret)
966*4882a593Smuzhiyun 			goto rtl8187_start_exit;
967*4882a593Smuzhiyun 		ret = rtl8187b_init_status_urb(dev);
968*4882a593Smuzhiyun 		if (ret)
969*4882a593Smuzhiyun 			usb_kill_anchored_urbs(&priv->anchored);
970*4882a593Smuzhiyun 		goto rtl8187_start_exit;
971*4882a593Smuzhiyun 	}
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
976*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 	ret = rtl8187_init_urbs(dev);
979*4882a593Smuzhiyun 	if (ret)
980*4882a593Smuzhiyun 		goto rtl8187_start_exit;
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun 	reg = RTL818X_RX_CONF_ONLYERLPKT |
983*4882a593Smuzhiyun 	      RTL818X_RX_CONF_RX_AUTORESETPHY |
984*4882a593Smuzhiyun 	      RTL818X_RX_CONF_BSSID |
985*4882a593Smuzhiyun 	      RTL818X_RX_CONF_MGMT |
986*4882a593Smuzhiyun 	      RTL818X_RX_CONF_DATA |
987*4882a593Smuzhiyun 	      (7 << 13 /* RX FIFO threshold NONE */) |
988*4882a593Smuzhiyun 	      (7 << 10 /* MAX RX DMA */) |
989*4882a593Smuzhiyun 	      RTL818X_RX_CONF_BROADCAST |
990*4882a593Smuzhiyun 	      RTL818X_RX_CONF_NICMAC;
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	priv->rx_conf = reg;
993*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
996*4882a593Smuzhiyun 	reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
997*4882a593Smuzhiyun 	reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
998*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
1001*4882a593Smuzhiyun 	reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
1002*4882a593Smuzhiyun 	reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
1003*4882a593Smuzhiyun 	reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
1004*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	reg  = RTL818X_TX_CONF_CW_MIN |
1007*4882a593Smuzhiyun 	       (7 << 21 /* MAX TX DMA */) |
1008*4882a593Smuzhiyun 	       RTL818X_TX_CONF_NO_ICV;
1009*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CMD);
1012*4882a593Smuzhiyun 	reg |= RTL818X_CMD_TX_ENABLE;
1013*4882a593Smuzhiyun 	reg |= RTL818X_CMD_RX_ENABLE;
1014*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1015*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->work, rtl8187_work);
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun rtl8187_start_exit:
1018*4882a593Smuzhiyun 	mutex_unlock(&priv->conf_mutex);
1019*4882a593Smuzhiyun 	return ret;
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun 
rtl8187_stop(struct ieee80211_hw * dev)1022*4882a593Smuzhiyun static void rtl8187_stop(struct ieee80211_hw *dev)
1023*4882a593Smuzhiyun {
1024*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1025*4882a593Smuzhiyun 	struct sk_buff *skb;
1026*4882a593Smuzhiyun 	u32 reg;
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	mutex_lock(&priv->conf_mutex);
1029*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CMD);
1032*4882a593Smuzhiyun 	reg &= ~RTL818X_CMD_TX_ENABLE;
1033*4882a593Smuzhiyun 	reg &= ~RTL818X_CMD_RX_ENABLE;
1034*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun 	priv->rf->stop(dev);
1037*4882a593Smuzhiyun 	rtl8187_set_anaparam(priv, false);
1038*4882a593Smuzhiyun 
1039*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1040*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1041*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1042*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1045*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	usb_kill_anchored_urbs(&priv->anchored);
1048*4882a593Smuzhiyun 	mutex_unlock(&priv->conf_mutex);
1049*4882a593Smuzhiyun 
1050*4882a593Smuzhiyun 	if (!priv->is_rtl8187b)
1051*4882a593Smuzhiyun 		cancel_delayed_work_sync(&priv->work);
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun 
rtl8187_get_tsf(struct ieee80211_hw * dev,struct ieee80211_vif * vif)1054*4882a593Smuzhiyun static u64 rtl8187_get_tsf(struct ieee80211_hw *dev, struct ieee80211_vif *vif)
1055*4882a593Smuzhiyun {
1056*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun 	return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1059*4882a593Smuzhiyun 	       (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 
rtl8187_beacon_work(struct work_struct * work)1063*4882a593Smuzhiyun static void rtl8187_beacon_work(struct work_struct *work)
1064*4882a593Smuzhiyun {
1065*4882a593Smuzhiyun 	struct rtl8187_vif *vif_priv =
1066*4882a593Smuzhiyun 		container_of(work, struct rtl8187_vif, beacon_work.work);
1067*4882a593Smuzhiyun 	struct ieee80211_vif *vif =
1068*4882a593Smuzhiyun 		container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1069*4882a593Smuzhiyun 	struct ieee80211_hw *dev = vif_priv->dev;
1070*4882a593Smuzhiyun 	struct ieee80211_mgmt *mgmt;
1071*4882a593Smuzhiyun 	struct sk_buff *skb;
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	/* don't overflow the tx ring */
1074*4882a593Smuzhiyun 	if (ieee80211_queue_stopped(dev, 0))
1075*4882a593Smuzhiyun 		goto resched;
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	/* grab a fresh beacon */
1078*4882a593Smuzhiyun 	skb = ieee80211_beacon_get(dev, vif);
1079*4882a593Smuzhiyun 	if (!skb)
1080*4882a593Smuzhiyun 		goto resched;
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun 	/*
1083*4882a593Smuzhiyun 	 * update beacon timestamp w/ TSF value
1084*4882a593Smuzhiyun 	 * TODO: make hardware update beacon timestamp
1085*4882a593Smuzhiyun 	 */
1086*4882a593Smuzhiyun 	mgmt = (struct ieee80211_mgmt *)skb->data;
1087*4882a593Smuzhiyun 	mgmt->u.beacon.timestamp = cpu_to_le64(rtl8187_get_tsf(dev, vif));
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	/* TODO: use actual beacon queue */
1090*4882a593Smuzhiyun 	skb_set_queue_mapping(skb, 0);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	rtl8187_tx(dev, NULL, skb);
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun resched:
1095*4882a593Smuzhiyun 	/*
1096*4882a593Smuzhiyun 	 * schedule next beacon
1097*4882a593Smuzhiyun 	 * TODO: use hardware support for beacon timing
1098*4882a593Smuzhiyun 	 */
1099*4882a593Smuzhiyun 	schedule_delayed_work(&vif_priv->beacon_work,
1100*4882a593Smuzhiyun 			usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 
rtl8187_add_interface(struct ieee80211_hw * dev,struct ieee80211_vif * vif)1104*4882a593Smuzhiyun static int rtl8187_add_interface(struct ieee80211_hw *dev,
1105*4882a593Smuzhiyun 				 struct ieee80211_vif *vif)
1106*4882a593Smuzhiyun {
1107*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1108*4882a593Smuzhiyun 	struct rtl8187_vif *vif_priv;
1109*4882a593Smuzhiyun 	int i;
1110*4882a593Smuzhiyun 	int ret = -EOPNOTSUPP;
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	mutex_lock(&priv->conf_mutex);
1113*4882a593Smuzhiyun 	if (priv->vif)
1114*4882a593Smuzhiyun 		goto exit;
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	switch (vif->type) {
1117*4882a593Smuzhiyun 	case NL80211_IFTYPE_STATION:
1118*4882a593Smuzhiyun 	case NL80211_IFTYPE_ADHOC:
1119*4882a593Smuzhiyun 		break;
1120*4882a593Smuzhiyun 	default:
1121*4882a593Smuzhiyun 		goto exit;
1122*4882a593Smuzhiyun 	}
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	ret = 0;
1125*4882a593Smuzhiyun 	priv->vif = vif;
1126*4882a593Smuzhiyun 
1127*4882a593Smuzhiyun 	/* Initialize driver private area */
1128*4882a593Smuzhiyun 	vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
1129*4882a593Smuzhiyun 	vif_priv->dev = dev;
1130*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8187_beacon_work);
1131*4882a593Smuzhiyun 	vif_priv->enable_beacon = false;
1132*4882a593Smuzhiyun 
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1135*4882a593Smuzhiyun 	for (i = 0; i < ETH_ALEN; i++)
1136*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->MAC[i],
1137*4882a593Smuzhiyun 				 ((u8 *)vif->addr)[i]);
1138*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun exit:
1141*4882a593Smuzhiyun 	mutex_unlock(&priv->conf_mutex);
1142*4882a593Smuzhiyun 	return ret;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun 
rtl8187_remove_interface(struct ieee80211_hw * dev,struct ieee80211_vif * vif)1145*4882a593Smuzhiyun static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1146*4882a593Smuzhiyun 				     struct ieee80211_vif *vif)
1147*4882a593Smuzhiyun {
1148*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1149*4882a593Smuzhiyun 	mutex_lock(&priv->conf_mutex);
1150*4882a593Smuzhiyun 	priv->vif = NULL;
1151*4882a593Smuzhiyun 	mutex_unlock(&priv->conf_mutex);
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun 
rtl8187_config(struct ieee80211_hw * dev,u32 changed)1154*4882a593Smuzhiyun static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
1155*4882a593Smuzhiyun {
1156*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1157*4882a593Smuzhiyun 	struct ieee80211_conf *conf = &dev->conf;
1158*4882a593Smuzhiyun 	u32 reg;
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	mutex_lock(&priv->conf_mutex);
1161*4882a593Smuzhiyun 	reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1162*4882a593Smuzhiyun 	/* Enable TX loopback on MAC level to avoid TX during channel
1163*4882a593Smuzhiyun 	 * changes, as this has be seen to causes problems and the
1164*4882a593Smuzhiyun 	 * card will stop work until next reset
1165*4882a593Smuzhiyun 	 */
1166*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1167*4882a593Smuzhiyun 			  reg | RTL818X_TX_CONF_LOOPBACK_MAC);
1168*4882a593Smuzhiyun 	priv->rf->set_chan(dev, conf);
1169*4882a593Smuzhiyun 	msleep(10);
1170*4882a593Smuzhiyun 	rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1173*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1174*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1175*4882a593Smuzhiyun 	rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
1176*4882a593Smuzhiyun 	mutex_unlock(&priv->conf_mutex);
1177*4882a593Smuzhiyun 	return 0;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun /*
1181*4882a593Smuzhiyun  * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1182*4882a593Smuzhiyun  * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1183*4882a593Smuzhiyun  */
1184*4882a593Smuzhiyun static __le32 *rtl8187b_ac_addr[4] = {
1185*4882a593Smuzhiyun 	(__le32 *) 0xFFF0, /* AC_VO */
1186*4882a593Smuzhiyun 	(__le32 *) 0xFFF4, /* AC_VI */
1187*4882a593Smuzhiyun 	(__le32 *) 0xFFFC, /* AC_BK */
1188*4882a593Smuzhiyun 	(__le32 *) 0xFFF8, /* AC_BE */
1189*4882a593Smuzhiyun };
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun #define SIFS_TIME 0xa
1192*4882a593Smuzhiyun 
rtl8187_conf_erp(struct rtl8187_priv * priv,bool use_short_slot,bool use_short_preamble)1193*4882a593Smuzhiyun static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1194*4882a593Smuzhiyun 			     bool use_short_preamble)
1195*4882a593Smuzhiyun {
1196*4882a593Smuzhiyun 	if (priv->is_rtl8187b) {
1197*4882a593Smuzhiyun 		u8 difs, eifs;
1198*4882a593Smuzhiyun 		u16 ack_timeout;
1199*4882a593Smuzhiyun 		int queue;
1200*4882a593Smuzhiyun 
1201*4882a593Smuzhiyun 		if (use_short_slot) {
1202*4882a593Smuzhiyun 			priv->slot_time = 0x9;
1203*4882a593Smuzhiyun 			difs = 0x1c;
1204*4882a593Smuzhiyun 			eifs = 0x53;
1205*4882a593Smuzhiyun 		} else {
1206*4882a593Smuzhiyun 			priv->slot_time = 0x14;
1207*4882a593Smuzhiyun 			difs = 0x32;
1208*4882a593Smuzhiyun 			eifs = 0x5b;
1209*4882a593Smuzhiyun 		}
1210*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1211*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1212*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 		/*
1215*4882a593Smuzhiyun 		 * BRSR+1 on 8187B is in fact EIFS register
1216*4882a593Smuzhiyun 		 * Value in units of 4 us
1217*4882a593Smuzhiyun 		 */
1218*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 		/*
1221*4882a593Smuzhiyun 		 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1222*4882a593Smuzhiyun 		 * register. In units of 4 us like eifs register
1223*4882a593Smuzhiyun 		 * ack_timeout = ack duration + plcp + difs + preamble
1224*4882a593Smuzhiyun 		 */
1225*4882a593Smuzhiyun 		ack_timeout = 112 + 48 + difs;
1226*4882a593Smuzhiyun 		if (use_short_preamble)
1227*4882a593Smuzhiyun 			ack_timeout += 72;
1228*4882a593Smuzhiyun 		else
1229*4882a593Smuzhiyun 			ack_timeout += 144;
1230*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1231*4882a593Smuzhiyun 				 DIV_ROUND_UP(ack_timeout, 4));
1232*4882a593Smuzhiyun 
1233*4882a593Smuzhiyun 		for (queue = 0; queue < 4; queue++)
1234*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1235*4882a593Smuzhiyun 					 priv->aifsn[queue] * priv->slot_time +
1236*4882a593Smuzhiyun 					 SIFS_TIME);
1237*4882a593Smuzhiyun 	} else {
1238*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1239*4882a593Smuzhiyun 		if (use_short_slot) {
1240*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1241*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1242*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
1243*4882a593Smuzhiyun 		} else {
1244*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1245*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1246*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
1247*4882a593Smuzhiyun 		}
1248*4882a593Smuzhiyun 	}
1249*4882a593Smuzhiyun }
1250*4882a593Smuzhiyun 
rtl8187_bss_info_changed(struct ieee80211_hw * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * info,u32 changed)1251*4882a593Smuzhiyun static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1252*4882a593Smuzhiyun 				     struct ieee80211_vif *vif,
1253*4882a593Smuzhiyun 				     struct ieee80211_bss_conf *info,
1254*4882a593Smuzhiyun 				     u32 changed)
1255*4882a593Smuzhiyun {
1256*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1257*4882a593Smuzhiyun 	struct rtl8187_vif *vif_priv;
1258*4882a593Smuzhiyun 	int i;
1259*4882a593Smuzhiyun 	u8 reg;
1260*4882a593Smuzhiyun 
1261*4882a593Smuzhiyun 	vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	if (changed & BSS_CHANGED_BSSID) {
1264*4882a593Smuzhiyun 		mutex_lock(&priv->conf_mutex);
1265*4882a593Smuzhiyun 		for (i = 0; i < ETH_ALEN; i++)
1266*4882a593Smuzhiyun 			rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1267*4882a593Smuzhiyun 					 info->bssid[i]);
1268*4882a593Smuzhiyun 
1269*4882a593Smuzhiyun 		if (priv->is_rtl8187b)
1270*4882a593Smuzhiyun 			reg = RTL818X_MSR_ENEDCA;
1271*4882a593Smuzhiyun 		else
1272*4882a593Smuzhiyun 			reg = 0;
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 		if (is_valid_ether_addr(info->bssid)) {
1275*4882a593Smuzhiyun 			if (vif->type == NL80211_IFTYPE_ADHOC)
1276*4882a593Smuzhiyun 				reg |= RTL818X_MSR_ADHOC;
1277*4882a593Smuzhiyun 			else
1278*4882a593Smuzhiyun 				reg |= RTL818X_MSR_INFRA;
1279*4882a593Smuzhiyun 		}
1280*4882a593Smuzhiyun 		else
1281*4882a593Smuzhiyun 			reg |= RTL818X_MSR_NO_LINK;
1282*4882a593Smuzhiyun 
1283*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 		mutex_unlock(&priv->conf_mutex);
1286*4882a593Smuzhiyun 	}
1287*4882a593Smuzhiyun 
1288*4882a593Smuzhiyun 	if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1289*4882a593Smuzhiyun 		rtl8187_conf_erp(priv, info->use_short_slot,
1290*4882a593Smuzhiyun 				 info->use_short_preamble);
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	if (changed & BSS_CHANGED_BEACON_ENABLED)
1293*4882a593Smuzhiyun 		vif_priv->enable_beacon = info->enable_beacon;
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 	if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1296*4882a593Smuzhiyun 		cancel_delayed_work_sync(&vif_priv->beacon_work);
1297*4882a593Smuzhiyun 		if (vif_priv->enable_beacon)
1298*4882a593Smuzhiyun 			schedule_work(&vif_priv->beacon_work.work);
1299*4882a593Smuzhiyun 	}
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun }
1302*4882a593Smuzhiyun 
rtl8187_prepare_multicast(struct ieee80211_hw * dev,struct netdev_hw_addr_list * mc_list)1303*4882a593Smuzhiyun static u64 rtl8187_prepare_multicast(struct ieee80211_hw *dev,
1304*4882a593Smuzhiyun 				     struct netdev_hw_addr_list *mc_list)
1305*4882a593Smuzhiyun {
1306*4882a593Smuzhiyun 	return netdev_hw_addr_list_count(mc_list);
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun 
rtl8187_configure_filter(struct ieee80211_hw * dev,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1309*4882a593Smuzhiyun static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1310*4882a593Smuzhiyun 				     unsigned int changed_flags,
1311*4882a593Smuzhiyun 				     unsigned int *total_flags,
1312*4882a593Smuzhiyun 				     u64 multicast)
1313*4882a593Smuzhiyun {
1314*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	if (changed_flags & FIF_FCSFAIL)
1317*4882a593Smuzhiyun 		priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1318*4882a593Smuzhiyun 	if (changed_flags & FIF_CONTROL)
1319*4882a593Smuzhiyun 		priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1320*4882a593Smuzhiyun 	if (*total_flags & FIF_OTHER_BSS ||
1321*4882a593Smuzhiyun 	    *total_flags & FIF_ALLMULTI || multicast > 0)
1322*4882a593Smuzhiyun 		priv->rx_conf |= RTL818X_RX_CONF_MONITOR;
1323*4882a593Smuzhiyun 	else
1324*4882a593Smuzhiyun 		priv->rx_conf &= ~RTL818X_RX_CONF_MONITOR;
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun 	*total_flags = 0;
1327*4882a593Smuzhiyun 
1328*4882a593Smuzhiyun 	if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1329*4882a593Smuzhiyun 		*total_flags |= FIF_FCSFAIL;
1330*4882a593Smuzhiyun 	if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1331*4882a593Smuzhiyun 		*total_flags |= FIF_CONTROL;
1332*4882a593Smuzhiyun 	if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) {
1333*4882a593Smuzhiyun 		*total_flags |= FIF_OTHER_BSS;
1334*4882a593Smuzhiyun 		*total_flags |= FIF_ALLMULTI;
1335*4882a593Smuzhiyun 	}
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun 
rtl8187_conf_tx(struct ieee80211_hw * dev,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1340*4882a593Smuzhiyun static int rtl8187_conf_tx(struct ieee80211_hw *dev,
1341*4882a593Smuzhiyun 			   struct ieee80211_vif *vif, u16 queue,
1342*4882a593Smuzhiyun 			   const struct ieee80211_tx_queue_params *params)
1343*4882a593Smuzhiyun {
1344*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1345*4882a593Smuzhiyun 	u8 cw_min, cw_max;
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if (queue > 3)
1348*4882a593Smuzhiyun 		return -EINVAL;
1349*4882a593Smuzhiyun 
1350*4882a593Smuzhiyun 	cw_min = fls(params->cw_min);
1351*4882a593Smuzhiyun 	cw_max = fls(params->cw_max);
1352*4882a593Smuzhiyun 
1353*4882a593Smuzhiyun 	if (priv->is_rtl8187b) {
1354*4882a593Smuzhiyun 		priv->aifsn[queue] = params->aifs;
1355*4882a593Smuzhiyun 
1356*4882a593Smuzhiyun 		/*
1357*4882a593Smuzhiyun 		 * This is the structure of AC_*_PARAM registers in 8187B:
1358*4882a593Smuzhiyun 		 * - TXOP limit field, bit offset = 16
1359*4882a593Smuzhiyun 		 * - ECWmax, bit offset = 12
1360*4882a593Smuzhiyun 		 * - ECWmin, bit offset = 8
1361*4882a593Smuzhiyun 		 * - AIFS, bit offset = 0
1362*4882a593Smuzhiyun 		 */
1363*4882a593Smuzhiyun 		rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1364*4882a593Smuzhiyun 				  (params->txop << 16) | (cw_max << 12) |
1365*4882a593Smuzhiyun 				  (cw_min << 8) | (params->aifs *
1366*4882a593Smuzhiyun 				  priv->slot_time + SIFS_TIME));
1367*4882a593Smuzhiyun 	} else {
1368*4882a593Smuzhiyun 		if (queue != 0)
1369*4882a593Smuzhiyun 			return -EINVAL;
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 		rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1372*4882a593Smuzhiyun 				 cw_min | (cw_max << 4));
1373*4882a593Smuzhiyun 	}
1374*4882a593Smuzhiyun 	return 0;
1375*4882a593Smuzhiyun }
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 
1378*4882a593Smuzhiyun static const struct ieee80211_ops rtl8187_ops = {
1379*4882a593Smuzhiyun 	.tx			= rtl8187_tx,
1380*4882a593Smuzhiyun 	.start			= rtl8187_start,
1381*4882a593Smuzhiyun 	.stop			= rtl8187_stop,
1382*4882a593Smuzhiyun 	.add_interface		= rtl8187_add_interface,
1383*4882a593Smuzhiyun 	.remove_interface	= rtl8187_remove_interface,
1384*4882a593Smuzhiyun 	.config			= rtl8187_config,
1385*4882a593Smuzhiyun 	.bss_info_changed	= rtl8187_bss_info_changed,
1386*4882a593Smuzhiyun 	.prepare_multicast	= rtl8187_prepare_multicast,
1387*4882a593Smuzhiyun 	.configure_filter	= rtl8187_configure_filter,
1388*4882a593Smuzhiyun 	.conf_tx		= rtl8187_conf_tx,
1389*4882a593Smuzhiyun 	.rfkill_poll		= rtl8187_rfkill_poll,
1390*4882a593Smuzhiyun 	.get_tsf		= rtl8187_get_tsf,
1391*4882a593Smuzhiyun };
1392*4882a593Smuzhiyun 
rtl8187_eeprom_register_read(struct eeprom_93cx6 * eeprom)1393*4882a593Smuzhiyun static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1394*4882a593Smuzhiyun {
1395*4882a593Smuzhiyun 	struct ieee80211_hw *dev = eeprom->data;
1396*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1397*4882a593Smuzhiyun 	u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1398*4882a593Smuzhiyun 
1399*4882a593Smuzhiyun 	eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1400*4882a593Smuzhiyun 	eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1401*4882a593Smuzhiyun 	eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1402*4882a593Smuzhiyun 	eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun 
rtl8187_eeprom_register_write(struct eeprom_93cx6 * eeprom)1405*4882a593Smuzhiyun static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1406*4882a593Smuzhiyun {
1407*4882a593Smuzhiyun 	struct ieee80211_hw *dev = eeprom->data;
1408*4882a593Smuzhiyun 	struct rtl8187_priv *priv = dev->priv;
1409*4882a593Smuzhiyun 	u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun 	if (eeprom->reg_data_in)
1412*4882a593Smuzhiyun 		reg |= RTL818X_EEPROM_CMD_WRITE;
1413*4882a593Smuzhiyun 	if (eeprom->reg_data_out)
1414*4882a593Smuzhiyun 		reg |= RTL818X_EEPROM_CMD_READ;
1415*4882a593Smuzhiyun 	if (eeprom->reg_data_clock)
1416*4882a593Smuzhiyun 		reg |= RTL818X_EEPROM_CMD_CK;
1417*4882a593Smuzhiyun 	if (eeprom->reg_chip_select)
1418*4882a593Smuzhiyun 		reg |= RTL818X_EEPROM_CMD_CS;
1419*4882a593Smuzhiyun 
1420*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1421*4882a593Smuzhiyun 	udelay(10);
1422*4882a593Smuzhiyun }
1423*4882a593Smuzhiyun 
rtl8187_probe(struct usb_interface * intf,const struct usb_device_id * id)1424*4882a593Smuzhiyun static int rtl8187_probe(struct usb_interface *intf,
1425*4882a593Smuzhiyun 				   const struct usb_device_id *id)
1426*4882a593Smuzhiyun {
1427*4882a593Smuzhiyun 	struct usb_device *udev = interface_to_usbdev(intf);
1428*4882a593Smuzhiyun 	struct ieee80211_hw *dev;
1429*4882a593Smuzhiyun 	struct rtl8187_priv *priv;
1430*4882a593Smuzhiyun 	struct eeprom_93cx6 eeprom;
1431*4882a593Smuzhiyun 	struct ieee80211_channel *channel;
1432*4882a593Smuzhiyun 	const char *chip_name;
1433*4882a593Smuzhiyun 	u16 txpwr, reg;
1434*4882a593Smuzhiyun 	u16 product_id = le16_to_cpu(udev->descriptor.idProduct);
1435*4882a593Smuzhiyun 	int err, i;
1436*4882a593Smuzhiyun 	u8 mac_addr[ETH_ALEN];
1437*4882a593Smuzhiyun 
1438*4882a593Smuzhiyun 	dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1439*4882a593Smuzhiyun 	if (!dev) {
1440*4882a593Smuzhiyun 		printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1441*4882a593Smuzhiyun 		return -ENOMEM;
1442*4882a593Smuzhiyun 	}
1443*4882a593Smuzhiyun 
1444*4882a593Smuzhiyun 	priv = dev->priv;
1445*4882a593Smuzhiyun 	priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun 	/* allocate "DMA aware" buffer for register accesses */
1448*4882a593Smuzhiyun 	priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1449*4882a593Smuzhiyun 	if (!priv->io_dmabuf) {
1450*4882a593Smuzhiyun 		err = -ENOMEM;
1451*4882a593Smuzhiyun 		goto err_free_dev;
1452*4882a593Smuzhiyun 	}
1453*4882a593Smuzhiyun 	mutex_init(&priv->io_mutex);
1454*4882a593Smuzhiyun 	mutex_init(&priv->conf_mutex);
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 	SET_IEEE80211_DEV(dev, &intf->dev);
1457*4882a593Smuzhiyun 	usb_set_intfdata(intf, dev);
1458*4882a593Smuzhiyun 	priv->udev = udev;
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 	usb_get_dev(udev);
1461*4882a593Smuzhiyun 
1462*4882a593Smuzhiyun 	skb_queue_head_init(&priv->rx_queue);
1463*4882a593Smuzhiyun 
1464*4882a593Smuzhiyun 	BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1465*4882a593Smuzhiyun 	BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1466*4882a593Smuzhiyun 
1467*4882a593Smuzhiyun 	memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1468*4882a593Smuzhiyun 	memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1469*4882a593Smuzhiyun 	priv->map = (struct rtl818x_csr *)0xFF00;
1470*4882a593Smuzhiyun 
1471*4882a593Smuzhiyun 	priv->band.band = NL80211_BAND_2GHZ;
1472*4882a593Smuzhiyun 	priv->band.channels = priv->channels;
1473*4882a593Smuzhiyun 	priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1474*4882a593Smuzhiyun 	priv->band.bitrates = priv->rates;
1475*4882a593Smuzhiyun 	priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1476*4882a593Smuzhiyun 	dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band;
1477*4882a593Smuzhiyun 
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	ieee80211_hw_set(dev, RX_INCLUDES_FCS);
1480*4882a593Smuzhiyun 	ieee80211_hw_set(dev, HOST_BROADCAST_PS_BUFFERING);
1481*4882a593Smuzhiyun 	ieee80211_hw_set(dev, SIGNAL_DBM);
1482*4882a593Smuzhiyun 	/* Initialize rate-control variables */
1483*4882a593Smuzhiyun 	dev->max_rates = 1;
1484*4882a593Smuzhiyun 	dev->max_rate_tries = RETRY_COUNT;
1485*4882a593Smuzhiyun 
1486*4882a593Smuzhiyun 	eeprom.data = dev;
1487*4882a593Smuzhiyun 	eeprom.register_read = rtl8187_eeprom_register_read;
1488*4882a593Smuzhiyun 	eeprom.register_write = rtl8187_eeprom_register_write;
1489*4882a593Smuzhiyun 	if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1490*4882a593Smuzhiyun 		eeprom.width = PCI_EEPROM_WIDTH_93C66;
1491*4882a593Smuzhiyun 	else
1492*4882a593Smuzhiyun 		eeprom.width = PCI_EEPROM_WIDTH_93C46;
1493*4882a593Smuzhiyun 
1494*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1495*4882a593Smuzhiyun 	udelay(10);
1496*4882a593Smuzhiyun 
1497*4882a593Smuzhiyun 	eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1498*4882a593Smuzhiyun 			       (__le16 __force *)mac_addr, 3);
1499*4882a593Smuzhiyun 	if (!is_valid_ether_addr(mac_addr)) {
1500*4882a593Smuzhiyun 		printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1501*4882a593Smuzhiyun 		       "generated MAC address\n");
1502*4882a593Smuzhiyun 		eth_random_addr(mac_addr);
1503*4882a593Smuzhiyun 	}
1504*4882a593Smuzhiyun 	SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1505*4882a593Smuzhiyun 
1506*4882a593Smuzhiyun 	channel = priv->channels;
1507*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
1508*4882a593Smuzhiyun 		eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1509*4882a593Smuzhiyun 				  &txpwr);
1510*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr & 0xFF;
1511*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr >> 8;
1512*4882a593Smuzhiyun 	}
1513*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1514*4882a593Smuzhiyun 		eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1515*4882a593Smuzhiyun 				  &txpwr);
1516*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr & 0xFF;
1517*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr >> 8;
1518*4882a593Smuzhiyun 	}
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1521*4882a593Smuzhiyun 			  &priv->txpwr_base);
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1524*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
1525*4882a593Smuzhiyun 	/* 0 means asic B-cut, we should use SW 3 wire
1526*4882a593Smuzhiyun 	 * bit-by-bit banging for radio. 1 means we can use
1527*4882a593Smuzhiyun 	 * USB specific request to write radio registers */
1528*4882a593Smuzhiyun 	priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
1529*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
1530*4882a593Smuzhiyun 	rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun 	if (!priv->is_rtl8187b) {
1533*4882a593Smuzhiyun 		u32 reg32;
1534*4882a593Smuzhiyun 		reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1535*4882a593Smuzhiyun 		reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1536*4882a593Smuzhiyun 		switch (reg32) {
1537*4882a593Smuzhiyun 		case RTL818X_TX_CONF_R8187vD_B:
1538*4882a593Smuzhiyun 			/* Some RTL8187B devices have a USB ID of 0x8187
1539*4882a593Smuzhiyun 			 * detect them here */
1540*4882a593Smuzhiyun 			chip_name = "RTL8187BvB(early)";
1541*4882a593Smuzhiyun 			priv->is_rtl8187b = 1;
1542*4882a593Smuzhiyun 			priv->hw_rev = RTL8187BvB;
1543*4882a593Smuzhiyun 			break;
1544*4882a593Smuzhiyun 		case RTL818X_TX_CONF_R8187vD:
1545*4882a593Smuzhiyun 			chip_name = "RTL8187vD";
1546*4882a593Smuzhiyun 			break;
1547*4882a593Smuzhiyun 		default:
1548*4882a593Smuzhiyun 			chip_name = "RTL8187vB (default)";
1549*4882a593Smuzhiyun 		}
1550*4882a593Smuzhiyun        } else {
1551*4882a593Smuzhiyun 		/*
1552*4882a593Smuzhiyun 		 * Force USB request to write radio registers for 8187B, Realtek
1553*4882a593Smuzhiyun 		 * only uses it in their sources
1554*4882a593Smuzhiyun 		 */
1555*4882a593Smuzhiyun 		/*if (priv->asic_rev == 0) {
1556*4882a593Smuzhiyun 			printk(KERN_WARNING "rtl8187: Forcing use of USB "
1557*4882a593Smuzhiyun 			       "requests to write to radio registers\n");
1558*4882a593Smuzhiyun 			priv->asic_rev = 1;
1559*4882a593Smuzhiyun 		}*/
1560*4882a593Smuzhiyun 		switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1561*4882a593Smuzhiyun 		case RTL818X_R8187B_B:
1562*4882a593Smuzhiyun 			chip_name = "RTL8187BvB";
1563*4882a593Smuzhiyun 			priv->hw_rev = RTL8187BvB;
1564*4882a593Smuzhiyun 			break;
1565*4882a593Smuzhiyun 		case RTL818X_R8187B_D:
1566*4882a593Smuzhiyun 			chip_name = "RTL8187BvD";
1567*4882a593Smuzhiyun 			priv->hw_rev = RTL8187BvD;
1568*4882a593Smuzhiyun 			break;
1569*4882a593Smuzhiyun 		case RTL818X_R8187B_E:
1570*4882a593Smuzhiyun 			chip_name = "RTL8187BvE";
1571*4882a593Smuzhiyun 			priv->hw_rev = RTL8187BvE;
1572*4882a593Smuzhiyun 			break;
1573*4882a593Smuzhiyun 		default:
1574*4882a593Smuzhiyun 			chip_name = "RTL8187BvB (default)";
1575*4882a593Smuzhiyun 			priv->hw_rev = RTL8187BvB;
1576*4882a593Smuzhiyun 		}
1577*4882a593Smuzhiyun 	}
1578*4882a593Smuzhiyun 
1579*4882a593Smuzhiyun 	if (!priv->is_rtl8187b) {
1580*4882a593Smuzhiyun 		for (i = 0; i < 2; i++) {
1581*4882a593Smuzhiyun 			eeprom_93cx6_read(&eeprom,
1582*4882a593Smuzhiyun 					  RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1583*4882a593Smuzhiyun 					  &txpwr);
1584*4882a593Smuzhiyun 			(*channel++).hw_value = txpwr & 0xFF;
1585*4882a593Smuzhiyun 			(*channel++).hw_value = txpwr >> 8;
1586*4882a593Smuzhiyun 		}
1587*4882a593Smuzhiyun 	} else {
1588*4882a593Smuzhiyun 		eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1589*4882a593Smuzhiyun 				  &txpwr);
1590*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr & 0xFF;
1591*4882a593Smuzhiyun 
1592*4882a593Smuzhiyun 		eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1593*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr & 0xFF;
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun 		eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1596*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr & 0xFF;
1597*4882a593Smuzhiyun 		(*channel++).hw_value = txpwr >> 8;
1598*4882a593Smuzhiyun 	}
1599*4882a593Smuzhiyun 	/* Handle the differing rfkill GPIO bit in different models */
1600*4882a593Smuzhiyun 	priv->rfkill_mask = RFKILL_MASK_8187_89_97;
1601*4882a593Smuzhiyun 	if (product_id == 0x8197 || product_id == 0x8198) {
1602*4882a593Smuzhiyun 		eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_SELECT_GPIO, &reg);
1603*4882a593Smuzhiyun 		if (reg & 0xFF00)
1604*4882a593Smuzhiyun 			priv->rfkill_mask = RFKILL_MASK_8198;
1605*4882a593Smuzhiyun 	}
1606*4882a593Smuzhiyun 	dev->vif_data_size = sizeof(struct rtl8187_vif);
1607*4882a593Smuzhiyun 	dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1608*4882a593Smuzhiyun 				      BIT(NL80211_IFTYPE_ADHOC) ;
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 	wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1611*4882a593Smuzhiyun 
1612*4882a593Smuzhiyun 	if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1613*4882a593Smuzhiyun 		printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1614*4882a593Smuzhiyun 		       " info!\n");
1615*4882a593Smuzhiyun 
1616*4882a593Smuzhiyun 	priv->rf = rtl8187_detect_rf(dev);
1617*4882a593Smuzhiyun 	dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1618*4882a593Smuzhiyun 				  sizeof(struct rtl8187_tx_hdr) :
1619*4882a593Smuzhiyun 				  sizeof(struct rtl8187b_tx_hdr);
1620*4882a593Smuzhiyun 	if (!priv->is_rtl8187b)
1621*4882a593Smuzhiyun 		dev->queues = 1;
1622*4882a593Smuzhiyun 	else
1623*4882a593Smuzhiyun 		dev->queues = 4;
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 	err = ieee80211_register_hw(dev);
1626*4882a593Smuzhiyun 	if (err) {
1627*4882a593Smuzhiyun 		printk(KERN_ERR "rtl8187: Cannot register device\n");
1628*4882a593Smuzhiyun 		goto err_free_dmabuf;
1629*4882a593Smuzhiyun 	}
1630*4882a593Smuzhiyun 	skb_queue_head_init(&priv->b_tx_status.queue);
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 	wiphy_info(dev->wiphy, "hwaddr %pM, %s V%d + %s, rfkill mask %d\n",
1633*4882a593Smuzhiyun 		   mac_addr, chip_name, priv->asic_rev, priv->rf->name,
1634*4882a593Smuzhiyun 		   priv->rfkill_mask);
1635*4882a593Smuzhiyun 
1636*4882a593Smuzhiyun #ifdef CONFIG_RTL8187_LEDS
1637*4882a593Smuzhiyun 	eeprom_93cx6_read(&eeprom, 0x3F, &reg);
1638*4882a593Smuzhiyun 	reg &= 0xFF;
1639*4882a593Smuzhiyun 	rtl8187_leds_init(dev, reg);
1640*4882a593Smuzhiyun #endif
1641*4882a593Smuzhiyun 	rtl8187_rfkill_init(dev);
1642*4882a593Smuzhiyun 
1643*4882a593Smuzhiyun 	return 0;
1644*4882a593Smuzhiyun 
1645*4882a593Smuzhiyun  err_free_dmabuf:
1646*4882a593Smuzhiyun 	kfree(priv->io_dmabuf);
1647*4882a593Smuzhiyun 	usb_set_intfdata(intf, NULL);
1648*4882a593Smuzhiyun 	usb_put_dev(udev);
1649*4882a593Smuzhiyun  err_free_dev:
1650*4882a593Smuzhiyun 	ieee80211_free_hw(dev);
1651*4882a593Smuzhiyun 	return err;
1652*4882a593Smuzhiyun }
1653*4882a593Smuzhiyun 
rtl8187_disconnect(struct usb_interface * intf)1654*4882a593Smuzhiyun static void rtl8187_disconnect(struct usb_interface *intf)
1655*4882a593Smuzhiyun {
1656*4882a593Smuzhiyun 	struct ieee80211_hw *dev = usb_get_intfdata(intf);
1657*4882a593Smuzhiyun 	struct rtl8187_priv *priv;
1658*4882a593Smuzhiyun 
1659*4882a593Smuzhiyun 	if (!dev)
1660*4882a593Smuzhiyun 		return;
1661*4882a593Smuzhiyun 
1662*4882a593Smuzhiyun #ifdef CONFIG_RTL8187_LEDS
1663*4882a593Smuzhiyun 	rtl8187_leds_exit(dev);
1664*4882a593Smuzhiyun #endif
1665*4882a593Smuzhiyun 	rtl8187_rfkill_exit(dev);
1666*4882a593Smuzhiyun 	ieee80211_unregister_hw(dev);
1667*4882a593Smuzhiyun 
1668*4882a593Smuzhiyun 	priv = dev->priv;
1669*4882a593Smuzhiyun 	usb_reset_device(priv->udev);
1670*4882a593Smuzhiyun 	usb_put_dev(interface_to_usbdev(intf));
1671*4882a593Smuzhiyun 	kfree(priv->io_dmabuf);
1672*4882a593Smuzhiyun 	ieee80211_free_hw(dev);
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun 
1675*4882a593Smuzhiyun static struct usb_driver rtl8187_driver = {
1676*4882a593Smuzhiyun 	.name		= KBUILD_MODNAME,
1677*4882a593Smuzhiyun 	.id_table	= rtl8187_table,
1678*4882a593Smuzhiyun 	.probe		= rtl8187_probe,
1679*4882a593Smuzhiyun 	.disconnect	= rtl8187_disconnect,
1680*4882a593Smuzhiyun 	.disable_hub_initiated_lpm = 1,
1681*4882a593Smuzhiyun };
1682*4882a593Smuzhiyun 
1683*4882a593Smuzhiyun module_usb_driver(rtl8187_driver);
1684