1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef RTL8180_H
3*4882a593Smuzhiyun #define RTL8180_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include "rtl818x.h"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define MAX_RX_SIZE IEEE80211_MAX_RTS_THRESHOLD
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define RF_PARAM_ANALOGPHY (1 << 0)
10*4882a593Smuzhiyun #define RF_PARAM_ANTBDEFAULT (1 << 1)
11*4882a593Smuzhiyun #define RF_PARAM_CARRIERSENSE1 (1 << 2)
12*4882a593Smuzhiyun #define RF_PARAM_CARRIERSENSE2 (1 << 3)
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define BB_ANTATTEN_CHAN14 0x0C
15*4882a593Smuzhiyun #define BB_ANTENNA_B 0x40
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define BB_HOST_BANG (1 << 30)
18*4882a593Smuzhiyun #define BB_HOST_BANG_EN (1 << 2)
19*4882a593Smuzhiyun #define BB_HOST_BANG_CLK (1 << 1)
20*4882a593Smuzhiyun #define BB_HOST_BANG_DATA 1
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define ANAPARAM_TXDACOFF_SHIFT 27
23*4882a593Smuzhiyun #define ANAPARAM_PWR0_SHIFT 28
24*4882a593Smuzhiyun #define ANAPARAM_PWR0_MASK (0x07 << ANAPARAM_PWR0_SHIFT)
25*4882a593Smuzhiyun #define ANAPARAM_PWR1_SHIFT 20
26*4882a593Smuzhiyun #define ANAPARAM_PWR1_MASK (0x7F << ANAPARAM_PWR1_SHIFT)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* rtl8180/rtl8185 have 3 queue + beacon queue.
29*4882a593Smuzhiyun * mac80211 can use just one, + beacon = 2 tot.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define RTL8180_NR_TX_QUEUES 2
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* rtl8187SE have 6 queues + beacon queues
34*4882a593Smuzhiyun * mac80211 can use 4 QoS data queue, + beacon = 5 tot
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define RTL8187SE_NR_TX_QUEUES 5
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* for array static allocation, it is the max of above */
39*4882a593Smuzhiyun #define RTL818X_NR_TX_QUEUES 5
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct rtl8180_tx_desc {
42*4882a593Smuzhiyun __le32 flags;
43*4882a593Smuzhiyun __le16 rts_duration;
44*4882a593Smuzhiyun __le16 plcp_len;
45*4882a593Smuzhiyun __le32 tx_buf;
46*4882a593Smuzhiyun union{
47*4882a593Smuzhiyun __le32 frame_len;
48*4882a593Smuzhiyun struct {
49*4882a593Smuzhiyun __le16 frame_len_se;
50*4882a593Smuzhiyun __le16 frame_duration;
51*4882a593Smuzhiyun } __packed;
52*4882a593Smuzhiyun } __packed;
53*4882a593Smuzhiyun __le32 next_tx_desc;
54*4882a593Smuzhiyun u8 cw;
55*4882a593Smuzhiyun u8 retry_limit;
56*4882a593Smuzhiyun u8 agc;
57*4882a593Smuzhiyun u8 flags2;
58*4882a593Smuzhiyun /* rsvd for 8180/8185.
59*4882a593Smuzhiyun * valid for 8187se but we dont use it
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun u32 reserved;
62*4882a593Smuzhiyun /* all rsvd for 8180/8185 */
63*4882a593Smuzhiyun __le16 flags3;
64*4882a593Smuzhiyun __le16 frag_qsize;
65*4882a593Smuzhiyun } __packed;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct rtl818x_rx_cmd_desc {
68*4882a593Smuzhiyun __le32 flags;
69*4882a593Smuzhiyun u32 reserved;
70*4882a593Smuzhiyun __le32 rx_buf;
71*4882a593Smuzhiyun } __packed;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun struct rtl8180_rx_desc {
74*4882a593Smuzhiyun __le32 flags;
75*4882a593Smuzhiyun __le32 flags2;
76*4882a593Smuzhiyun __le64 tsft;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun } __packed;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun struct rtl8187se_rx_desc {
81*4882a593Smuzhiyun __le32 flags;
82*4882a593Smuzhiyun __le64 tsft;
83*4882a593Smuzhiyun __le32 flags2;
84*4882a593Smuzhiyun __le32 flags3;
85*4882a593Smuzhiyun u32 reserved[3];
86*4882a593Smuzhiyun } __packed;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct rtl8180_tx_ring {
89*4882a593Smuzhiyun struct rtl8180_tx_desc *desc;
90*4882a593Smuzhiyun dma_addr_t dma;
91*4882a593Smuzhiyun unsigned int idx;
92*4882a593Smuzhiyun unsigned int entries;
93*4882a593Smuzhiyun struct sk_buff_head queue;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct rtl8180_vif {
97*4882a593Smuzhiyun struct ieee80211_hw *dev;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* beaconing */
100*4882a593Smuzhiyun struct delayed_work beacon_work;
101*4882a593Smuzhiyun bool enable_beacon;
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun struct rtl8180_priv {
105*4882a593Smuzhiyun /* common between rtl818x drivers */
106*4882a593Smuzhiyun struct rtl818x_csr __iomem *map;
107*4882a593Smuzhiyun const struct rtl818x_rf_ops *rf;
108*4882a593Smuzhiyun struct ieee80211_vif *vif;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* rtl8180 driver specific */
111*4882a593Smuzhiyun bool map_pio;
112*4882a593Smuzhiyun spinlock_t lock;
113*4882a593Smuzhiyun void *rx_ring;
114*4882a593Smuzhiyun u8 rx_ring_sz;
115*4882a593Smuzhiyun dma_addr_t rx_ring_dma;
116*4882a593Smuzhiyun unsigned int rx_idx;
117*4882a593Smuzhiyun struct sk_buff *rx_buf[32];
118*4882a593Smuzhiyun struct rtl8180_tx_ring tx_ring[RTL818X_NR_TX_QUEUES];
119*4882a593Smuzhiyun struct ieee80211_channel channels[14];
120*4882a593Smuzhiyun struct ieee80211_rate rates[12];
121*4882a593Smuzhiyun struct ieee80211_supported_band band;
122*4882a593Smuzhiyun struct ieee80211_tx_queue_params queue_param[4];
123*4882a593Smuzhiyun struct pci_dev *pdev;
124*4882a593Smuzhiyun u32 rx_conf;
125*4882a593Smuzhiyun u8 slot_time;
126*4882a593Smuzhiyun u16 ack_time;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun enum {
129*4882a593Smuzhiyun RTL818X_CHIP_FAMILY_RTL8180,
130*4882a593Smuzhiyun RTL818X_CHIP_FAMILY_RTL8185,
131*4882a593Smuzhiyun RTL818X_CHIP_FAMILY_RTL8187SE,
132*4882a593Smuzhiyun } chip_family;
133*4882a593Smuzhiyun u32 anaparam;
134*4882a593Smuzhiyun u16 rfparam;
135*4882a593Smuzhiyun u8 csthreshold;
136*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN];
137*4882a593Smuzhiyun u8 rf_type;
138*4882a593Smuzhiyun u8 xtal_out;
139*4882a593Smuzhiyun u8 xtal_in;
140*4882a593Smuzhiyun u8 xtal_cal;
141*4882a593Smuzhiyun u8 thermal_meter_val;
142*4882a593Smuzhiyun u8 thermal_meter_en;
143*4882a593Smuzhiyun u8 antenna_diversity_en;
144*4882a593Smuzhiyun u8 antenna_diversity_default;
145*4882a593Smuzhiyun /* sequence # */
146*4882a593Smuzhiyun u16 seqno;
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);
150*4882a593Smuzhiyun void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam);
151*4882a593Smuzhiyun void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2);
152*4882a593Smuzhiyun
rtl818x_ioread8(struct rtl8180_priv * priv,const u8 __iomem * addr)153*4882a593Smuzhiyun static inline u8 rtl818x_ioread8(struct rtl8180_priv *priv, const u8 __iomem *addr)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun return ioread8(addr);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
rtl818x_ioread16(struct rtl8180_priv * priv,const __le16 __iomem * addr)158*4882a593Smuzhiyun static inline u16 rtl818x_ioread16(struct rtl8180_priv *priv, const __le16 __iomem *addr)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun return ioread16(addr);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
rtl818x_ioread32(struct rtl8180_priv * priv,const __le32 __iomem * addr)163*4882a593Smuzhiyun static inline u32 rtl818x_ioread32(struct rtl8180_priv *priv, const __le32 __iomem *addr)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun return ioread32(addr);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
rtl818x_iowrite8(struct rtl8180_priv * priv,u8 __iomem * addr,u8 val)168*4882a593Smuzhiyun static inline void rtl818x_iowrite8(struct rtl8180_priv *priv,
169*4882a593Smuzhiyun u8 __iomem *addr, u8 val)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun iowrite8(val, addr);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
rtl818x_iowrite16(struct rtl8180_priv * priv,__le16 __iomem * addr,u16 val)174*4882a593Smuzhiyun static inline void rtl818x_iowrite16(struct rtl8180_priv *priv,
175*4882a593Smuzhiyun __le16 __iomem *addr, u16 val)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun iowrite16(val, addr);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
rtl818x_iowrite32(struct rtl8180_priv * priv,__le32 __iomem * addr,u32 val)180*4882a593Smuzhiyun static inline void rtl818x_iowrite32(struct rtl8180_priv *priv,
181*4882a593Smuzhiyun __le32 __iomem *addr, u32 val)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun iowrite32(val, addr);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun #endif /* RTL8180_H */
187