1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 4*4882a593Smuzhiyun <http://rt2x00.serialmonkey.com> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun Module: rt2x00 10*4882a593Smuzhiyun Abstract: rt2x00 generic register information. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef RT2X00REG_H 14*4882a593Smuzhiyun #define RT2X00REG_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * RX crypto status 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun enum rx_crypto { 20*4882a593Smuzhiyun RX_CRYPTO_SUCCESS = 0, 21*4882a593Smuzhiyun RX_CRYPTO_FAIL_ICV = 1, 22*4882a593Smuzhiyun RX_CRYPTO_FAIL_MIC = 2, 23*4882a593Smuzhiyun RX_CRYPTO_FAIL_KEY = 3, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Antenna values 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun enum antenna { 30*4882a593Smuzhiyun ANTENNA_SW_DIVERSITY = 0, 31*4882a593Smuzhiyun ANTENNA_A = 1, 32*4882a593Smuzhiyun ANTENNA_B = 2, 33*4882a593Smuzhiyun ANTENNA_HW_DIVERSITY = 3, 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * Led mode values. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun enum led_mode { 40*4882a593Smuzhiyun LED_MODE_DEFAULT = 0, 41*4882a593Smuzhiyun LED_MODE_TXRX_ACTIVITY = 1, 42*4882a593Smuzhiyun LED_MODE_SIGNAL_STRENGTH = 2, 43*4882a593Smuzhiyun LED_MODE_ASUS = 3, 44*4882a593Smuzhiyun LED_MODE_ALPHA = 4, 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * TSF sync values 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun enum tsf_sync { 51*4882a593Smuzhiyun TSF_SYNC_NONE = 0, 52*4882a593Smuzhiyun TSF_SYNC_INFRA = 1, 53*4882a593Smuzhiyun TSF_SYNC_ADHOC = 2, 54*4882a593Smuzhiyun TSF_SYNC_AP_NONE = 3, 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Device states 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun enum dev_state { 61*4882a593Smuzhiyun STATE_DEEP_SLEEP = 0, 62*4882a593Smuzhiyun STATE_SLEEP = 1, 63*4882a593Smuzhiyun STATE_STANDBY = 2, 64*4882a593Smuzhiyun STATE_AWAKE = 3, 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * Additional device states, these values are 68*4882a593Smuzhiyun * not strict since they are not directly passed 69*4882a593Smuzhiyun * into the device. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun STATE_RADIO_ON, 72*4882a593Smuzhiyun STATE_RADIO_OFF, 73*4882a593Smuzhiyun STATE_RADIO_IRQ_ON, 74*4882a593Smuzhiyun STATE_RADIO_IRQ_OFF, 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * IFS backoff values 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun enum ifs { 81*4882a593Smuzhiyun IFS_BACKOFF = 0, 82*4882a593Smuzhiyun IFS_SIFS = 1, 83*4882a593Smuzhiyun IFS_NEW_BACKOFF = 2, 84*4882a593Smuzhiyun IFS_NONE = 3, 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * IFS backoff values for HT devices 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun enum txop { 91*4882a593Smuzhiyun TXOP_HTTXOP = 0, 92*4882a593Smuzhiyun TXOP_PIFS = 1, 93*4882a593Smuzhiyun TXOP_SIFS = 2, 94*4882a593Smuzhiyun TXOP_BACKOFF = 3, 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * Cipher types for hardware encryption 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun enum cipher { 101*4882a593Smuzhiyun CIPHER_NONE = 0, 102*4882a593Smuzhiyun CIPHER_WEP64 = 1, 103*4882a593Smuzhiyun CIPHER_WEP128 = 2, 104*4882a593Smuzhiyun CIPHER_TKIP = 3, 105*4882a593Smuzhiyun CIPHER_AES = 4, 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * The following fields were added by rt61pci and rt73usb. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun CIPHER_CKIP64 = 5, 110*4882a593Smuzhiyun CIPHER_CKIP128 = 6, 111*4882a593Smuzhiyun CIPHER_TKIP_NO_MIC = 7, /* Don't send to device */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Max cipher type. 115*4882a593Smuzhiyun * Note that CIPHER_NONE isn't counted, and CKIP64 and CKIP128 116*4882a593Smuzhiyun * are excluded due to limitations in mac80211. 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun CIPHER_MAX = 4, 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* 122*4882a593Smuzhiyun * Rate modulations 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun enum rate_modulation { 125*4882a593Smuzhiyun RATE_MODE_CCK = 0, 126*4882a593Smuzhiyun RATE_MODE_OFDM = 1, 127*4882a593Smuzhiyun RATE_MODE_HT_MIX = 2, 128*4882a593Smuzhiyun RATE_MODE_HT_GREENFIELD = 3, 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * Firmware validation error codes 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun enum firmware_errors { 135*4882a593Smuzhiyun FW_OK, 136*4882a593Smuzhiyun FW_BAD_CRC, 137*4882a593Smuzhiyun FW_BAD_LENGTH, 138*4882a593Smuzhiyun FW_BAD_VERSION, 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* 142*4882a593Smuzhiyun * Register handlers. 143*4882a593Smuzhiyun * We store the position of a register field inside a field structure, 144*4882a593Smuzhiyun * This will simplify the process of setting and reading a certain field 145*4882a593Smuzhiyun * inside the register while making sure the process remains byte order safe. 146*4882a593Smuzhiyun */ 147*4882a593Smuzhiyun struct rt2x00_field8 { 148*4882a593Smuzhiyun u8 bit_offset; 149*4882a593Smuzhiyun u8 bit_mask; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun struct rt2x00_field16 { 153*4882a593Smuzhiyun u16 bit_offset; 154*4882a593Smuzhiyun u16 bit_mask; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun struct rt2x00_field32 { 158*4882a593Smuzhiyun u32 bit_offset; 159*4882a593Smuzhiyun u32 bit_mask; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* 163*4882a593Smuzhiyun * Power of two check, this will check 164*4882a593Smuzhiyun * if the mask that has been given contains and contiguous set of bits. 165*4882a593Smuzhiyun * Note that we cannot use the is_power_of_2() function since this 166*4882a593Smuzhiyun * check must be done at compile-time. 167*4882a593Smuzhiyun */ 168*4882a593Smuzhiyun #define is_power_of_two(x) ( !((x) & ((x)-1)) ) 169*4882a593Smuzhiyun #define low_bit_mask(x) ( ((x)-1) & ~(x) ) 170*4882a593Smuzhiyun #define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x)) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* 173*4882a593Smuzhiyun * Macros to find first set bit in a variable. 174*4882a593Smuzhiyun * These macros behave the same as the __ffs() functions but 175*4882a593Smuzhiyun * the most important difference that this is done during 176*4882a593Smuzhiyun * compile-time rather then run-time. 177*4882a593Smuzhiyun */ 178*4882a593Smuzhiyun #define compile_ffs2(__x) \ 179*4882a593Smuzhiyun __builtin_choose_expr(((__x) & 0x1), 0, 1) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define compile_ffs4(__x) \ 182*4882a593Smuzhiyun __builtin_choose_expr(((__x) & 0x3), \ 183*4882a593Smuzhiyun (compile_ffs2((__x))), \ 184*4882a593Smuzhiyun (compile_ffs2((__x) >> 2) + 2)) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define compile_ffs8(__x) \ 187*4882a593Smuzhiyun __builtin_choose_expr(((__x) & 0xf), \ 188*4882a593Smuzhiyun (compile_ffs4((__x))), \ 189*4882a593Smuzhiyun (compile_ffs4((__x) >> 4) + 4)) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define compile_ffs16(__x) \ 192*4882a593Smuzhiyun __builtin_choose_expr(((__x) & 0xff), \ 193*4882a593Smuzhiyun (compile_ffs8((__x))), \ 194*4882a593Smuzhiyun (compile_ffs8((__x) >> 8) + 8)) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define compile_ffs32(__x) \ 197*4882a593Smuzhiyun __builtin_choose_expr(((__x) & 0xffff), \ 198*4882a593Smuzhiyun (compile_ffs16((__x))), \ 199*4882a593Smuzhiyun (compile_ffs16((__x) >> 16) + 16)) 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* 202*4882a593Smuzhiyun * This macro will check the requirements for the FIELD{8,16,32} macros 203*4882a593Smuzhiyun * The mask should be a constant non-zero contiguous set of bits which 204*4882a593Smuzhiyun * does not exceed the given typelimit. 205*4882a593Smuzhiyun */ 206*4882a593Smuzhiyun #define FIELD_CHECK(__mask, __type) \ 207*4882a593Smuzhiyun BUILD_BUG_ON(!(__mask) || \ 208*4882a593Smuzhiyun !is_valid_mask(__mask) || \ 209*4882a593Smuzhiyun (__mask) != (__type)(__mask)) \ 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #define FIELD8(__mask) \ 212*4882a593Smuzhiyun ({ \ 213*4882a593Smuzhiyun FIELD_CHECK(__mask, u8); \ 214*4882a593Smuzhiyun (struct rt2x00_field8) { \ 215*4882a593Smuzhiyun compile_ffs8(__mask), (__mask) \ 216*4882a593Smuzhiyun }; \ 217*4882a593Smuzhiyun }) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #define FIELD16(__mask) \ 220*4882a593Smuzhiyun ({ \ 221*4882a593Smuzhiyun FIELD_CHECK(__mask, u16); \ 222*4882a593Smuzhiyun (struct rt2x00_field16) { \ 223*4882a593Smuzhiyun compile_ffs16(__mask), (__mask) \ 224*4882a593Smuzhiyun }; \ 225*4882a593Smuzhiyun }) 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define FIELD32(__mask) \ 228*4882a593Smuzhiyun ({ \ 229*4882a593Smuzhiyun FIELD_CHECK(__mask, u32); \ 230*4882a593Smuzhiyun (struct rt2x00_field32) { \ 231*4882a593Smuzhiyun compile_ffs32(__mask), (__mask) \ 232*4882a593Smuzhiyun }; \ 233*4882a593Smuzhiyun }) 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define SET_FIELD(__reg, __type, __field, __value)\ 236*4882a593Smuzhiyun ({ \ 237*4882a593Smuzhiyun typecheck(__type, __field); \ 238*4882a593Smuzhiyun *(__reg) &= ~((__field).bit_mask); \ 239*4882a593Smuzhiyun *(__reg) |= ((__value) << \ 240*4882a593Smuzhiyun ((__field).bit_offset)) & \ 241*4882a593Smuzhiyun ((__field).bit_mask); \ 242*4882a593Smuzhiyun }) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define GET_FIELD(__reg, __type, __field) \ 245*4882a593Smuzhiyun ({ \ 246*4882a593Smuzhiyun typecheck(__type, __field); \ 247*4882a593Smuzhiyun ((__reg) & ((__field).bit_mask)) >> \ 248*4882a593Smuzhiyun ((__field).bit_offset); \ 249*4882a593Smuzhiyun }) 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define rt2x00_set_field32(__reg, __field, __value) \ 252*4882a593Smuzhiyun SET_FIELD(__reg, struct rt2x00_field32, __field, __value) 253*4882a593Smuzhiyun #define rt2x00_get_field32(__reg, __field) \ 254*4882a593Smuzhiyun GET_FIELD(__reg, struct rt2x00_field32, __field) 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun #define rt2x00_set_field16(__reg, __field, __value) \ 257*4882a593Smuzhiyun SET_FIELD(__reg, struct rt2x00_field16, __field, __value) 258*4882a593Smuzhiyun #define rt2x00_get_field16(__reg, __field) \ 259*4882a593Smuzhiyun GET_FIELD(__reg, struct rt2x00_field16, __field) 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define rt2x00_set_field8(__reg, __field, __value) \ 262*4882a593Smuzhiyun SET_FIELD(__reg, struct rt2x00_field8, __field, __value) 263*4882a593Smuzhiyun #define rt2x00_get_field8(__reg, __field) \ 264*4882a593Smuzhiyun GET_FIELD(__reg, struct rt2x00_field8, __field) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #endif /* RT2X00REG_H */ 267