1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4*4882a593Smuzhiyun Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
5*4882a593Smuzhiyun Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6*4882a593Smuzhiyun <http://rt2x00.serialmonkey.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun Module: rt2x00lib
12*4882a593Smuzhiyun Abstract: rt2x00 queue specific routines.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/dma-mapping.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "rt2x00.h"
21*4882a593Smuzhiyun #include "rt2x00lib.h"
22*4882a593Smuzhiyun
rt2x00queue_alloc_rxskb(struct queue_entry * entry,gfp_t gfp)23*4882a593Smuzhiyun struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry, gfp_t gfp)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct data_queue *queue = entry->queue;
26*4882a593Smuzhiyun struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
27*4882a593Smuzhiyun struct sk_buff *skb;
28*4882a593Smuzhiyun struct skb_frame_desc *skbdesc;
29*4882a593Smuzhiyun unsigned int frame_size;
30*4882a593Smuzhiyun unsigned int head_size = 0;
31*4882a593Smuzhiyun unsigned int tail_size = 0;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * The frame size includes descriptor size, because the
35*4882a593Smuzhiyun * hardware directly receive the frame into the skbuffer.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun frame_size = queue->data_size + queue->desc_size + queue->winfo_size;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * The payload should be aligned to a 4-byte boundary,
41*4882a593Smuzhiyun * this means we need at least 3 bytes for moving the frame
42*4882a593Smuzhiyun * into the correct offset.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun head_size = 4;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * For IV/EIV/ICV assembly we must make sure there is
48*4882a593Smuzhiyun * at least 8 bytes bytes available in headroom for IV/EIV
49*4882a593Smuzhiyun * and 8 bytes for ICV data as tailroon.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun if (rt2x00_has_cap_hw_crypto(rt2x00dev)) {
52*4882a593Smuzhiyun head_size += 8;
53*4882a593Smuzhiyun tail_size += 8;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Allocate skbuffer.
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun skb = __dev_alloc_skb(frame_size + head_size + tail_size, gfp);
60*4882a593Smuzhiyun if (!skb)
61*4882a593Smuzhiyun return NULL;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * Make sure we not have a frame with the requested bytes
65*4882a593Smuzhiyun * available in the head and tail.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun skb_reserve(skb, head_size);
68*4882a593Smuzhiyun skb_put(skb, frame_size);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Populate skbdesc.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun skbdesc = get_skb_frame_desc(skb);
74*4882a593Smuzhiyun memset(skbdesc, 0, sizeof(*skbdesc));
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (rt2x00_has_cap_flag(rt2x00dev, REQUIRE_DMA)) {
77*4882a593Smuzhiyun dma_addr_t skb_dma;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len,
80*4882a593Smuzhiyun DMA_FROM_DEVICE);
81*4882a593Smuzhiyun if (unlikely(dma_mapping_error(rt2x00dev->dev, skb_dma))) {
82*4882a593Smuzhiyun dev_kfree_skb_any(skb);
83*4882a593Smuzhiyun return NULL;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun skbdesc->skb_dma = skb_dma;
87*4882a593Smuzhiyun skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return skb;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
rt2x00queue_map_txskb(struct queue_entry * entry)93*4882a593Smuzhiyun int rt2x00queue_map_txskb(struct queue_entry *entry)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct device *dev = entry->queue->rt2x00dev->dev;
96*4882a593Smuzhiyun struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun skbdesc->skb_dma =
99*4882a593Smuzhiyun dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (unlikely(dma_mapping_error(dev, skbdesc->skb_dma)))
102*4882a593Smuzhiyun return -ENOMEM;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
105*4882a593Smuzhiyun rt2x00lib_dmadone(entry);
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
109*4882a593Smuzhiyun
rt2x00queue_unmap_skb(struct queue_entry * entry)110*4882a593Smuzhiyun void rt2x00queue_unmap_skb(struct queue_entry *entry)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct device *dev = entry->queue->rt2x00dev->dev;
113*4882a593Smuzhiyun struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
116*4882a593Smuzhiyun dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
117*4882a593Smuzhiyun DMA_FROM_DEVICE);
118*4882a593Smuzhiyun skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
119*4882a593Smuzhiyun } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
120*4882a593Smuzhiyun dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
121*4882a593Smuzhiyun DMA_TO_DEVICE);
122*4882a593Smuzhiyun skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
126*4882a593Smuzhiyun
rt2x00queue_free_skb(struct queue_entry * entry)127*4882a593Smuzhiyun void rt2x00queue_free_skb(struct queue_entry *entry)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun if (!entry->skb)
130*4882a593Smuzhiyun return;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun rt2x00queue_unmap_skb(entry);
133*4882a593Smuzhiyun dev_kfree_skb_any(entry->skb);
134*4882a593Smuzhiyun entry->skb = NULL;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
rt2x00queue_align_frame(struct sk_buff * skb)137*4882a593Smuzhiyun void rt2x00queue_align_frame(struct sk_buff *skb)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun unsigned int frame_length = skb->len;
140*4882a593Smuzhiyun unsigned int align = ALIGN_SIZE(skb, 0);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (!align)
143*4882a593Smuzhiyun return;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun skb_push(skb, align);
146*4882a593Smuzhiyun memmove(skb->data, skb->data + align, frame_length);
147*4882a593Smuzhiyun skb_trim(skb, frame_length);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun * H/W needs L2 padding between the header and the paylod if header size
152*4882a593Smuzhiyun * is not 4 bytes aligned.
153*4882a593Smuzhiyun */
rt2x00queue_insert_l2pad(struct sk_buff * skb,unsigned int hdr_len)154*4882a593Smuzhiyun void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int hdr_len)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun unsigned int l2pad = (skb->len > hdr_len) ? L2PAD_SIZE(hdr_len) : 0;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun if (!l2pad)
159*4882a593Smuzhiyun return;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun skb_push(skb, l2pad);
162*4882a593Smuzhiyun memmove(skb->data, skb->data + l2pad, hdr_len);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
rt2x00queue_remove_l2pad(struct sk_buff * skb,unsigned int hdr_len)165*4882a593Smuzhiyun void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int hdr_len)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun unsigned int l2pad = (skb->len > hdr_len) ? L2PAD_SIZE(hdr_len) : 0;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (!l2pad)
170*4882a593Smuzhiyun return;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun memmove(skb->data + l2pad, skb->data, hdr_len);
173*4882a593Smuzhiyun skb_pull(skb, l2pad);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev * rt2x00dev,struct sk_buff * skb,struct txentry_desc * txdesc)176*4882a593Smuzhiyun static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev,
177*4882a593Smuzhiyun struct sk_buff *skb,
178*4882a593Smuzhiyun struct txentry_desc *txdesc)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
181*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
182*4882a593Smuzhiyun struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
183*4882a593Smuzhiyun u16 seqno;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
186*4882a593Smuzhiyun return;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (!rt2x00_has_cap_flag(rt2x00dev, REQUIRE_SW_SEQNO)) {
191*4882a593Smuzhiyun /*
192*4882a593Smuzhiyun * rt2800 has a H/W (or F/W) bug, device incorrectly increase
193*4882a593Smuzhiyun * seqno on retransmitted data (non-QOS) and management frames.
194*4882a593Smuzhiyun * To workaround the problem let's generate seqno in software.
195*4882a593Smuzhiyun * Except for beacons which are transmitted periodically by H/W
196*4882a593Smuzhiyun * hence hardware has to assign seqno for them.
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun if (ieee80211_is_beacon(hdr->frame_control)) {
199*4882a593Smuzhiyun __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
200*4882a593Smuzhiyun /* H/W will generate sequence number */
201*4882a593Smuzhiyun return;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun __clear_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /*
208*4882a593Smuzhiyun * The hardware is not able to insert a sequence number. Assign a
209*4882a593Smuzhiyun * software generated one here.
210*4882a593Smuzhiyun *
211*4882a593Smuzhiyun * This is wrong because beacons are not getting sequence
212*4882a593Smuzhiyun * numbers assigned properly.
213*4882a593Smuzhiyun *
214*4882a593Smuzhiyun * A secondary problem exists for drivers that cannot toggle
215*4882a593Smuzhiyun * sequence counting per-frame, since those will override the
216*4882a593Smuzhiyun * sequence counter given by mac80211.
217*4882a593Smuzhiyun */
218*4882a593Smuzhiyun if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
219*4882a593Smuzhiyun seqno = atomic_add_return(0x10, &intf->seqno);
220*4882a593Smuzhiyun else
221*4882a593Smuzhiyun seqno = atomic_read(&intf->seqno);
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
224*4882a593Smuzhiyun hdr->seq_ctrl |= cpu_to_le16(seqno);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev * rt2x00dev,struct sk_buff * skb,struct txentry_desc * txdesc,const struct rt2x00_rate * hwrate)227*4882a593Smuzhiyun static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev,
228*4882a593Smuzhiyun struct sk_buff *skb,
229*4882a593Smuzhiyun struct txentry_desc *txdesc,
230*4882a593Smuzhiyun const struct rt2x00_rate *hwrate)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
233*4882a593Smuzhiyun struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
234*4882a593Smuzhiyun unsigned int data_length;
235*4882a593Smuzhiyun unsigned int duration;
236*4882a593Smuzhiyun unsigned int residual;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /*
239*4882a593Smuzhiyun * Determine with what IFS priority this frame should be send.
240*4882a593Smuzhiyun * Set ifs to IFS_SIFS when the this is not the first fragment,
241*4882a593Smuzhiyun * or this fragment came after RTS/CTS.
242*4882a593Smuzhiyun */
243*4882a593Smuzhiyun if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
244*4882a593Smuzhiyun txdesc->u.plcp.ifs = IFS_BACKOFF;
245*4882a593Smuzhiyun else
246*4882a593Smuzhiyun txdesc->u.plcp.ifs = IFS_SIFS;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
249*4882a593Smuzhiyun data_length = skb->len + 4;
250*4882a593Smuzhiyun data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun /*
253*4882a593Smuzhiyun * PLCP setup
254*4882a593Smuzhiyun * Length calculation depends on OFDM/CCK rate.
255*4882a593Smuzhiyun */
256*4882a593Smuzhiyun txdesc->u.plcp.signal = hwrate->plcp;
257*4882a593Smuzhiyun txdesc->u.plcp.service = 0x04;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (hwrate->flags & DEV_RATE_OFDM) {
260*4882a593Smuzhiyun txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f;
261*4882a593Smuzhiyun txdesc->u.plcp.length_low = data_length & 0x3f;
262*4882a593Smuzhiyun } else {
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * Convert length to microseconds.
265*4882a593Smuzhiyun */
266*4882a593Smuzhiyun residual = GET_DURATION_RES(data_length, hwrate->bitrate);
267*4882a593Smuzhiyun duration = GET_DURATION(data_length, hwrate->bitrate);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (residual != 0) {
270*4882a593Smuzhiyun duration++;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /*
273*4882a593Smuzhiyun * Check if we need to set the Length Extension
274*4882a593Smuzhiyun */
275*4882a593Smuzhiyun if (hwrate->bitrate == 110 && residual <= 30)
276*4882a593Smuzhiyun txdesc->u.plcp.service |= 0x80;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun txdesc->u.plcp.length_high = (duration >> 8) & 0xff;
280*4882a593Smuzhiyun txdesc->u.plcp.length_low = duration & 0xff;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /*
283*4882a593Smuzhiyun * When preamble is enabled we should set the
284*4882a593Smuzhiyun * preamble bit for the signal.
285*4882a593Smuzhiyun */
286*4882a593Smuzhiyun if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
287*4882a593Smuzhiyun txdesc->u.plcp.signal |= 0x08;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev * rt2x00dev,struct sk_buff * skb,struct txentry_desc * txdesc,struct ieee80211_sta * sta,const struct rt2x00_rate * hwrate)291*4882a593Smuzhiyun static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev,
292*4882a593Smuzhiyun struct sk_buff *skb,
293*4882a593Smuzhiyun struct txentry_desc *txdesc,
294*4882a593Smuzhiyun struct ieee80211_sta *sta,
295*4882a593Smuzhiyun const struct rt2x00_rate *hwrate)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
298*4882a593Smuzhiyun struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
299*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
300*4882a593Smuzhiyun struct rt2x00_sta *sta_priv = NULL;
301*4882a593Smuzhiyun u8 density = 0;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if (sta) {
304*4882a593Smuzhiyun sta_priv = sta_to_rt2x00_sta(sta);
305*4882a593Smuzhiyun txdesc->u.ht.wcid = sta_priv->wcid;
306*4882a593Smuzhiyun density = sta->ht_cap.ampdu_density;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /*
310*4882a593Smuzhiyun * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the
311*4882a593Smuzhiyun * mcs rate to be used
312*4882a593Smuzhiyun */
313*4882a593Smuzhiyun if (txrate->flags & IEEE80211_TX_RC_MCS) {
314*4882a593Smuzhiyun txdesc->u.ht.mcs = txrate->idx;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /*
317*4882a593Smuzhiyun * MIMO PS should be set to 1 for STA's using dynamic SM PS
318*4882a593Smuzhiyun * when using more then one tx stream (>MCS7).
319*4882a593Smuzhiyun */
320*4882a593Smuzhiyun if (sta && txdesc->u.ht.mcs > 7 &&
321*4882a593Smuzhiyun sta->smps_mode == IEEE80211_SMPS_DYNAMIC)
322*4882a593Smuzhiyun __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags);
323*4882a593Smuzhiyun } else {
324*4882a593Smuzhiyun txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs);
325*4882a593Smuzhiyun if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
326*4882a593Smuzhiyun txdesc->u.ht.mcs |= 0x08;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if (test_bit(CONFIG_HT_DISABLED, &rt2x00dev->flags)) {
330*4882a593Smuzhiyun if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
331*4882a593Smuzhiyun txdesc->u.ht.txop = TXOP_SIFS;
332*4882a593Smuzhiyun else
333*4882a593Smuzhiyun txdesc->u.ht.txop = TXOP_BACKOFF;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /* Left zero on all other settings. */
336*4882a593Smuzhiyun return;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /*
340*4882a593Smuzhiyun * Only one STBC stream is supported for now.
341*4882a593Smuzhiyun */
342*4882a593Smuzhiyun if (tx_info->flags & IEEE80211_TX_CTL_STBC)
343*4882a593Smuzhiyun txdesc->u.ht.stbc = 1;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /*
346*4882a593Smuzhiyun * This frame is eligible for an AMPDU, however, don't aggregate
347*4882a593Smuzhiyun * frames that are intended to probe a specific tx rate.
348*4882a593Smuzhiyun */
349*4882a593Smuzhiyun if (tx_info->flags & IEEE80211_TX_CTL_AMPDU &&
350*4882a593Smuzhiyun !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
351*4882a593Smuzhiyun __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
352*4882a593Smuzhiyun txdesc->u.ht.mpdu_density = density;
353*4882a593Smuzhiyun txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /*
357*4882a593Smuzhiyun * Set 40Mhz mode if necessary (for legacy rates this will
358*4882a593Smuzhiyun * duplicate the frame to both channels).
359*4882a593Smuzhiyun */
360*4882a593Smuzhiyun if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH ||
361*4882a593Smuzhiyun txrate->flags & IEEE80211_TX_RC_DUP_DATA)
362*4882a593Smuzhiyun __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
363*4882a593Smuzhiyun if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
364*4882a593Smuzhiyun __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /*
367*4882a593Smuzhiyun * Determine IFS values
368*4882a593Smuzhiyun * - Use TXOP_BACKOFF for management frames except beacons
369*4882a593Smuzhiyun * - Use TXOP_SIFS for fragment bursts
370*4882a593Smuzhiyun * - Use TXOP_HTTXOP for everything else
371*4882a593Smuzhiyun *
372*4882a593Smuzhiyun * Note: rt2800 devices won't use CTS protection (if used)
373*4882a593Smuzhiyun * for frames not transmitted with TXOP_HTTXOP
374*4882a593Smuzhiyun */
375*4882a593Smuzhiyun if (ieee80211_is_mgmt(hdr->frame_control) &&
376*4882a593Smuzhiyun !ieee80211_is_beacon(hdr->frame_control))
377*4882a593Smuzhiyun txdesc->u.ht.txop = TXOP_BACKOFF;
378*4882a593Smuzhiyun else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
379*4882a593Smuzhiyun txdesc->u.ht.txop = TXOP_SIFS;
380*4882a593Smuzhiyun else
381*4882a593Smuzhiyun txdesc->u.ht.txop = TXOP_HTTXOP;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
rt2x00queue_create_tx_descriptor(struct rt2x00_dev * rt2x00dev,struct sk_buff * skb,struct txentry_desc * txdesc,struct ieee80211_sta * sta)384*4882a593Smuzhiyun static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev,
385*4882a593Smuzhiyun struct sk_buff *skb,
386*4882a593Smuzhiyun struct txentry_desc *txdesc,
387*4882a593Smuzhiyun struct ieee80211_sta *sta)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
390*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
391*4882a593Smuzhiyun struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
392*4882a593Smuzhiyun struct ieee80211_rate *rate;
393*4882a593Smuzhiyun const struct rt2x00_rate *hwrate = NULL;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun memset(txdesc, 0, sizeof(*txdesc));
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun /*
398*4882a593Smuzhiyun * Header and frame information.
399*4882a593Smuzhiyun */
400*4882a593Smuzhiyun txdesc->length = skb->len;
401*4882a593Smuzhiyun txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb);
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun /*
404*4882a593Smuzhiyun * Check whether this frame is to be acked.
405*4882a593Smuzhiyun */
406*4882a593Smuzhiyun if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
407*4882a593Smuzhiyun __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /*
410*4882a593Smuzhiyun * Check if this is a RTS/CTS frame
411*4882a593Smuzhiyun */
412*4882a593Smuzhiyun if (ieee80211_is_rts(hdr->frame_control) ||
413*4882a593Smuzhiyun ieee80211_is_cts(hdr->frame_control)) {
414*4882a593Smuzhiyun __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
415*4882a593Smuzhiyun if (ieee80211_is_rts(hdr->frame_control))
416*4882a593Smuzhiyun __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
417*4882a593Smuzhiyun else
418*4882a593Smuzhiyun __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
419*4882a593Smuzhiyun if (tx_info->control.rts_cts_rate_idx >= 0)
420*4882a593Smuzhiyun rate =
421*4882a593Smuzhiyun ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun /*
425*4882a593Smuzhiyun * Determine retry information.
426*4882a593Smuzhiyun */
427*4882a593Smuzhiyun txdesc->retry_limit = tx_info->control.rates[0].count - 1;
428*4882a593Smuzhiyun if (txdesc->retry_limit >= rt2x00dev->long_retry)
429*4882a593Smuzhiyun __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /*
432*4882a593Smuzhiyun * Check if more fragments are pending
433*4882a593Smuzhiyun */
434*4882a593Smuzhiyun if (ieee80211_has_morefrags(hdr->frame_control)) {
435*4882a593Smuzhiyun __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
436*4882a593Smuzhiyun __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun /*
440*4882a593Smuzhiyun * Check if more frames (!= fragments) are pending
441*4882a593Smuzhiyun */
442*4882a593Smuzhiyun if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
443*4882a593Smuzhiyun __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /*
446*4882a593Smuzhiyun * Beacons and probe responses require the tsf timestamp
447*4882a593Smuzhiyun * to be inserted into the frame.
448*4882a593Smuzhiyun */
449*4882a593Smuzhiyun if (ieee80211_is_beacon(hdr->frame_control) ||
450*4882a593Smuzhiyun ieee80211_is_probe_resp(hdr->frame_control))
451*4882a593Smuzhiyun __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
454*4882a593Smuzhiyun !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags))
455*4882a593Smuzhiyun __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /*
458*4882a593Smuzhiyun * Determine rate modulation.
459*4882a593Smuzhiyun */
460*4882a593Smuzhiyun if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
461*4882a593Smuzhiyun txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
462*4882a593Smuzhiyun else if (txrate->flags & IEEE80211_TX_RC_MCS)
463*4882a593Smuzhiyun txdesc->rate_mode = RATE_MODE_HT_MIX;
464*4882a593Smuzhiyun else {
465*4882a593Smuzhiyun rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
466*4882a593Smuzhiyun hwrate = rt2x00_get_rate(rate->hw_value);
467*4882a593Smuzhiyun if (hwrate->flags & DEV_RATE_OFDM)
468*4882a593Smuzhiyun txdesc->rate_mode = RATE_MODE_OFDM;
469*4882a593Smuzhiyun else
470*4882a593Smuzhiyun txdesc->rate_mode = RATE_MODE_CCK;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun /*
474*4882a593Smuzhiyun * Apply TX descriptor handling by components
475*4882a593Smuzhiyun */
476*4882a593Smuzhiyun rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc);
477*4882a593Smuzhiyun rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun if (rt2x00_has_cap_flag(rt2x00dev, REQUIRE_HT_TX_DESC))
480*4882a593Smuzhiyun rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc,
481*4882a593Smuzhiyun sta, hwrate);
482*4882a593Smuzhiyun else
483*4882a593Smuzhiyun rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc,
484*4882a593Smuzhiyun hwrate);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
rt2x00queue_write_tx_data(struct queue_entry * entry,struct txentry_desc * txdesc)487*4882a593Smuzhiyun static int rt2x00queue_write_tx_data(struct queue_entry *entry,
488*4882a593Smuzhiyun struct txentry_desc *txdesc)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun /*
493*4882a593Smuzhiyun * This should not happen, we already checked the entry
494*4882a593Smuzhiyun * was ours. When the hardware disagrees there has been
495*4882a593Smuzhiyun * a queue corruption!
496*4882a593Smuzhiyun */
497*4882a593Smuzhiyun if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
498*4882a593Smuzhiyun rt2x00dev->ops->lib->get_entry_state(entry))) {
499*4882a593Smuzhiyun rt2x00_err(rt2x00dev,
500*4882a593Smuzhiyun "Corrupt queue %d, accessing entry which is not ours\n"
501*4882a593Smuzhiyun "Please file bug report to %s\n",
502*4882a593Smuzhiyun entry->queue->qid, DRV_PROJECT);
503*4882a593Smuzhiyun return -EINVAL;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /*
507*4882a593Smuzhiyun * Add the requested extra tx headroom in front of the skb.
508*4882a593Smuzhiyun */
509*4882a593Smuzhiyun skb_push(entry->skb, rt2x00dev->extra_tx_headroom);
510*4882a593Smuzhiyun memset(entry->skb->data, 0, rt2x00dev->extra_tx_headroom);
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun /*
513*4882a593Smuzhiyun * Call the driver's write_tx_data function, if it exists.
514*4882a593Smuzhiyun */
515*4882a593Smuzhiyun if (rt2x00dev->ops->lib->write_tx_data)
516*4882a593Smuzhiyun rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun /*
519*4882a593Smuzhiyun * Map the skb to DMA.
520*4882a593Smuzhiyun */
521*4882a593Smuzhiyun if (rt2x00_has_cap_flag(rt2x00dev, REQUIRE_DMA) &&
522*4882a593Smuzhiyun rt2x00queue_map_txskb(entry))
523*4882a593Smuzhiyun return -ENOMEM;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun return 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
rt2x00queue_write_tx_descriptor(struct queue_entry * entry,struct txentry_desc * txdesc)528*4882a593Smuzhiyun static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
529*4882a593Smuzhiyun struct txentry_desc *txdesc)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun struct data_queue *queue = entry->queue;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /*
536*4882a593Smuzhiyun * All processing on the frame has been completed, this means
537*4882a593Smuzhiyun * it is now ready to be dumped to userspace through debugfs.
538*4882a593Smuzhiyun */
539*4882a593Smuzhiyun rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry);
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun
rt2x00queue_kick_tx_queue(struct data_queue * queue,struct txentry_desc * txdesc)542*4882a593Smuzhiyun static void rt2x00queue_kick_tx_queue(struct data_queue *queue,
543*4882a593Smuzhiyun struct txentry_desc *txdesc)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun /*
546*4882a593Smuzhiyun * Check if we need to kick the queue, there are however a few rules
547*4882a593Smuzhiyun * 1) Don't kick unless this is the last in frame in a burst.
548*4882a593Smuzhiyun * When the burst flag is set, this frame is always followed
549*4882a593Smuzhiyun * by another frame which in some way are related to eachother.
550*4882a593Smuzhiyun * This is true for fragments, RTS or CTS-to-self frames.
551*4882a593Smuzhiyun * 2) Rule 1 can be broken when the available entries
552*4882a593Smuzhiyun * in the queue are less then a certain threshold.
553*4882a593Smuzhiyun */
554*4882a593Smuzhiyun if (rt2x00queue_threshold(queue) ||
555*4882a593Smuzhiyun !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
556*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->kick_queue(queue);
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
rt2x00queue_bar_check(struct queue_entry * entry)559*4882a593Smuzhiyun static void rt2x00queue_bar_check(struct queue_entry *entry)
560*4882a593Smuzhiyun {
561*4882a593Smuzhiyun struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
562*4882a593Smuzhiyun struct ieee80211_bar *bar = (void *) (entry->skb->data +
563*4882a593Smuzhiyun rt2x00dev->extra_tx_headroom);
564*4882a593Smuzhiyun struct rt2x00_bar_list_entry *bar_entry;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun if (likely(!ieee80211_is_back_req(bar->frame_control)))
567*4882a593Smuzhiyun return;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun bar_entry = kmalloc(sizeof(*bar_entry), GFP_ATOMIC);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /*
572*4882a593Smuzhiyun * If the alloc fails we still send the BAR out but just don't track
573*4882a593Smuzhiyun * it in our bar list. And as a result we will report it to mac80211
574*4882a593Smuzhiyun * back as failed.
575*4882a593Smuzhiyun */
576*4882a593Smuzhiyun if (!bar_entry)
577*4882a593Smuzhiyun return;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun bar_entry->entry = entry;
580*4882a593Smuzhiyun bar_entry->block_acked = 0;
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun /*
583*4882a593Smuzhiyun * Copy the relevant parts of the 802.11 BAR into out check list
584*4882a593Smuzhiyun * such that we can use RCU for less-overhead in the RX path since
585*4882a593Smuzhiyun * sending BARs and processing the according BlockAck should be
586*4882a593Smuzhiyun * the exception.
587*4882a593Smuzhiyun */
588*4882a593Smuzhiyun memcpy(bar_entry->ra, bar->ra, sizeof(bar->ra));
589*4882a593Smuzhiyun memcpy(bar_entry->ta, bar->ta, sizeof(bar->ta));
590*4882a593Smuzhiyun bar_entry->control = bar->control;
591*4882a593Smuzhiyun bar_entry->start_seq_num = bar->start_seq_num;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun /*
594*4882a593Smuzhiyun * Insert BAR into our BAR check list.
595*4882a593Smuzhiyun */
596*4882a593Smuzhiyun spin_lock_bh(&rt2x00dev->bar_list_lock);
597*4882a593Smuzhiyun list_add_tail_rcu(&bar_entry->list, &rt2x00dev->bar_list);
598*4882a593Smuzhiyun spin_unlock_bh(&rt2x00dev->bar_list_lock);
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
rt2x00queue_write_tx_frame(struct data_queue * queue,struct sk_buff * skb,struct ieee80211_sta * sta,bool local)601*4882a593Smuzhiyun int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
602*4882a593Smuzhiyun struct ieee80211_sta *sta, bool local)
603*4882a593Smuzhiyun {
604*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info;
605*4882a593Smuzhiyun struct queue_entry *entry;
606*4882a593Smuzhiyun struct txentry_desc txdesc;
607*4882a593Smuzhiyun struct skb_frame_desc *skbdesc;
608*4882a593Smuzhiyun u8 rate_idx, rate_flags;
609*4882a593Smuzhiyun int ret = 0;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun /*
612*4882a593Smuzhiyun * Copy all TX descriptor information into txdesc,
613*4882a593Smuzhiyun * after that we are free to use the skb->cb array
614*4882a593Smuzhiyun * for our information.
615*4882a593Smuzhiyun */
616*4882a593Smuzhiyun rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun /*
619*4882a593Smuzhiyun * All information is retrieved from the skb->cb array,
620*4882a593Smuzhiyun * now we should claim ownership of the driver part of that
621*4882a593Smuzhiyun * array, preserving the bitrate index and flags.
622*4882a593Smuzhiyun */
623*4882a593Smuzhiyun tx_info = IEEE80211_SKB_CB(skb);
624*4882a593Smuzhiyun rate_idx = tx_info->control.rates[0].idx;
625*4882a593Smuzhiyun rate_flags = tx_info->control.rates[0].flags;
626*4882a593Smuzhiyun skbdesc = get_skb_frame_desc(skb);
627*4882a593Smuzhiyun memset(skbdesc, 0, sizeof(*skbdesc));
628*4882a593Smuzhiyun skbdesc->tx_rate_idx = rate_idx;
629*4882a593Smuzhiyun skbdesc->tx_rate_flags = rate_flags;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun if (local)
632*4882a593Smuzhiyun skbdesc->flags |= SKBDESC_NOT_MAC80211;
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun /*
635*4882a593Smuzhiyun * When hardware encryption is supported, and this frame
636*4882a593Smuzhiyun * is to be encrypted, we should strip the IV/EIV data from
637*4882a593Smuzhiyun * the frame so we can provide it to the driver separately.
638*4882a593Smuzhiyun */
639*4882a593Smuzhiyun if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
640*4882a593Smuzhiyun !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
641*4882a593Smuzhiyun if (rt2x00_has_cap_flag(queue->rt2x00dev, REQUIRE_COPY_IV))
642*4882a593Smuzhiyun rt2x00crypto_tx_copy_iv(skb, &txdesc);
643*4882a593Smuzhiyun else
644*4882a593Smuzhiyun rt2x00crypto_tx_remove_iv(skb, &txdesc);
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /*
648*4882a593Smuzhiyun * When DMA allocation is required we should guarantee to the
649*4882a593Smuzhiyun * driver that the DMA is aligned to a 4-byte boundary.
650*4882a593Smuzhiyun * However some drivers require L2 padding to pad the payload
651*4882a593Smuzhiyun * rather then the header. This could be a requirement for
652*4882a593Smuzhiyun * PCI and USB devices, while header alignment only is valid
653*4882a593Smuzhiyun * for PCI devices.
654*4882a593Smuzhiyun */
655*4882a593Smuzhiyun if (rt2x00_has_cap_flag(queue->rt2x00dev, REQUIRE_L2PAD))
656*4882a593Smuzhiyun rt2x00queue_insert_l2pad(skb, txdesc.header_length);
657*4882a593Smuzhiyun else if (rt2x00_has_cap_flag(queue->rt2x00dev, REQUIRE_DMA))
658*4882a593Smuzhiyun rt2x00queue_align_frame(skb);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun /*
661*4882a593Smuzhiyun * That function must be called with bh disabled.
662*4882a593Smuzhiyun */
663*4882a593Smuzhiyun spin_lock(&queue->tx_lock);
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (unlikely(rt2x00queue_full(queue))) {
666*4882a593Smuzhiyun rt2x00_dbg(queue->rt2x00dev, "Dropping frame due to full tx queue %d\n",
667*4882a593Smuzhiyun queue->qid);
668*4882a593Smuzhiyun ret = -ENOBUFS;
669*4882a593Smuzhiyun goto out;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun entry = rt2x00queue_get_entry(queue, Q_INDEX);
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
675*4882a593Smuzhiyun &entry->flags))) {
676*4882a593Smuzhiyun rt2x00_err(queue->rt2x00dev,
677*4882a593Smuzhiyun "Arrived at non-free entry in the non-full queue %d\n"
678*4882a593Smuzhiyun "Please file bug report to %s\n",
679*4882a593Smuzhiyun queue->qid, DRV_PROJECT);
680*4882a593Smuzhiyun ret = -EINVAL;
681*4882a593Smuzhiyun goto out;
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun entry->skb = skb;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun /*
687*4882a593Smuzhiyun * It could be possible that the queue was corrupted and this
688*4882a593Smuzhiyun * call failed. Since we always return NETDEV_TX_OK to mac80211,
689*4882a593Smuzhiyun * this frame will simply be dropped.
690*4882a593Smuzhiyun */
691*4882a593Smuzhiyun if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
692*4882a593Smuzhiyun clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
693*4882a593Smuzhiyun entry->skb = NULL;
694*4882a593Smuzhiyun ret = -EIO;
695*4882a593Smuzhiyun goto out;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun /*
699*4882a593Smuzhiyun * Put BlockAckReqs into our check list for driver BA processing.
700*4882a593Smuzhiyun */
701*4882a593Smuzhiyun rt2x00queue_bar_check(entry);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun set_bit(ENTRY_DATA_PENDING, &entry->flags);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun rt2x00queue_index_inc(entry, Q_INDEX);
706*4882a593Smuzhiyun rt2x00queue_write_tx_descriptor(entry, &txdesc);
707*4882a593Smuzhiyun rt2x00queue_kick_tx_queue(queue, &txdesc);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun out:
710*4882a593Smuzhiyun /*
711*4882a593Smuzhiyun * Pausing queue has to be serialized with rt2x00lib_txdone(), so we
712*4882a593Smuzhiyun * do this under queue->tx_lock. Bottom halve was already disabled
713*4882a593Smuzhiyun * before ieee80211_xmit() call.
714*4882a593Smuzhiyun */
715*4882a593Smuzhiyun if (rt2x00queue_threshold(queue))
716*4882a593Smuzhiyun rt2x00queue_pause_queue(queue);
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun spin_unlock(&queue->tx_lock);
719*4882a593Smuzhiyun return ret;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
rt2x00queue_clear_beacon(struct rt2x00_dev * rt2x00dev,struct ieee80211_vif * vif)722*4882a593Smuzhiyun int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
723*4882a593Smuzhiyun struct ieee80211_vif *vif)
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun struct rt2x00_intf *intf = vif_to_intf(vif);
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun if (unlikely(!intf->beacon))
728*4882a593Smuzhiyun return -ENOBUFS;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun /*
731*4882a593Smuzhiyun * Clean up the beacon skb.
732*4882a593Smuzhiyun */
733*4882a593Smuzhiyun rt2x00queue_free_skb(intf->beacon);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun /*
736*4882a593Smuzhiyun * Clear beacon (single bssid devices don't need to clear the beacon
737*4882a593Smuzhiyun * since the beacon queue will get stopped anyway).
738*4882a593Smuzhiyun */
739*4882a593Smuzhiyun if (rt2x00dev->ops->lib->clear_beacon)
740*4882a593Smuzhiyun rt2x00dev->ops->lib->clear_beacon(intf->beacon);
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun return 0;
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
rt2x00queue_update_beacon(struct rt2x00_dev * rt2x00dev,struct ieee80211_vif * vif)745*4882a593Smuzhiyun int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
746*4882a593Smuzhiyun struct ieee80211_vif *vif)
747*4882a593Smuzhiyun {
748*4882a593Smuzhiyun struct rt2x00_intf *intf = vif_to_intf(vif);
749*4882a593Smuzhiyun struct skb_frame_desc *skbdesc;
750*4882a593Smuzhiyun struct txentry_desc txdesc;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun if (unlikely(!intf->beacon))
753*4882a593Smuzhiyun return -ENOBUFS;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun /*
756*4882a593Smuzhiyun * Clean up the beacon skb.
757*4882a593Smuzhiyun */
758*4882a593Smuzhiyun rt2x00queue_free_skb(intf->beacon);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
761*4882a593Smuzhiyun if (!intf->beacon->skb)
762*4882a593Smuzhiyun return -ENOMEM;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun /*
765*4882a593Smuzhiyun * Copy all TX descriptor information into txdesc,
766*4882a593Smuzhiyun * after that we are free to use the skb->cb array
767*4882a593Smuzhiyun * for our information.
768*4882a593Smuzhiyun */
769*4882a593Smuzhiyun rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc, NULL);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun /*
772*4882a593Smuzhiyun * Fill in skb descriptor
773*4882a593Smuzhiyun */
774*4882a593Smuzhiyun skbdesc = get_skb_frame_desc(intf->beacon->skb);
775*4882a593Smuzhiyun memset(skbdesc, 0, sizeof(*skbdesc));
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun /*
778*4882a593Smuzhiyun * Send beacon to hardware.
779*4882a593Smuzhiyun */
780*4882a593Smuzhiyun rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun return 0;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
rt2x00queue_for_each_entry(struct data_queue * queue,enum queue_index start,enum queue_index end,void * data,bool (* fn)(struct queue_entry * entry,void * data))786*4882a593Smuzhiyun bool rt2x00queue_for_each_entry(struct data_queue *queue,
787*4882a593Smuzhiyun enum queue_index start,
788*4882a593Smuzhiyun enum queue_index end,
789*4882a593Smuzhiyun void *data,
790*4882a593Smuzhiyun bool (*fn)(struct queue_entry *entry,
791*4882a593Smuzhiyun void *data))
792*4882a593Smuzhiyun {
793*4882a593Smuzhiyun unsigned long irqflags;
794*4882a593Smuzhiyun unsigned int index_start;
795*4882a593Smuzhiyun unsigned int index_end;
796*4882a593Smuzhiyun unsigned int i;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
799*4882a593Smuzhiyun rt2x00_err(queue->rt2x00dev,
800*4882a593Smuzhiyun "Entry requested from invalid index range (%d - %d)\n",
801*4882a593Smuzhiyun start, end);
802*4882a593Smuzhiyun return true;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun /*
806*4882a593Smuzhiyun * Only protect the range we are going to loop over,
807*4882a593Smuzhiyun * if during our loop a extra entry is set to pending
808*4882a593Smuzhiyun * it should not be kicked during this run, since it
809*4882a593Smuzhiyun * is part of another TX operation.
810*4882a593Smuzhiyun */
811*4882a593Smuzhiyun spin_lock_irqsave(&queue->index_lock, irqflags);
812*4882a593Smuzhiyun index_start = queue->index[start];
813*4882a593Smuzhiyun index_end = queue->index[end];
814*4882a593Smuzhiyun spin_unlock_irqrestore(&queue->index_lock, irqflags);
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun /*
817*4882a593Smuzhiyun * Start from the TX done pointer, this guarantees that we will
818*4882a593Smuzhiyun * send out all frames in the correct order.
819*4882a593Smuzhiyun */
820*4882a593Smuzhiyun if (index_start < index_end) {
821*4882a593Smuzhiyun for (i = index_start; i < index_end; i++) {
822*4882a593Smuzhiyun if (fn(&queue->entries[i], data))
823*4882a593Smuzhiyun return true;
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun } else {
826*4882a593Smuzhiyun for (i = index_start; i < queue->limit; i++) {
827*4882a593Smuzhiyun if (fn(&queue->entries[i], data))
828*4882a593Smuzhiyun return true;
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun for (i = 0; i < index_end; i++) {
832*4882a593Smuzhiyun if (fn(&queue->entries[i], data))
833*4882a593Smuzhiyun return true;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun return false;
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
840*4882a593Smuzhiyun
rt2x00queue_get_entry(struct data_queue * queue,enum queue_index index)841*4882a593Smuzhiyun struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
842*4882a593Smuzhiyun enum queue_index index)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun struct queue_entry *entry;
845*4882a593Smuzhiyun unsigned long irqflags;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun if (unlikely(index >= Q_INDEX_MAX)) {
848*4882a593Smuzhiyun rt2x00_err(queue->rt2x00dev, "Entry requested from invalid index type (%d)\n",
849*4882a593Smuzhiyun index);
850*4882a593Smuzhiyun return NULL;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun spin_lock_irqsave(&queue->index_lock, irqflags);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun entry = &queue->entries[queue->index[index]];
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun spin_unlock_irqrestore(&queue->index_lock, irqflags);
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun return entry;
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
862*4882a593Smuzhiyun
rt2x00queue_index_inc(struct queue_entry * entry,enum queue_index index)863*4882a593Smuzhiyun void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index)
864*4882a593Smuzhiyun {
865*4882a593Smuzhiyun struct data_queue *queue = entry->queue;
866*4882a593Smuzhiyun unsigned long irqflags;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun if (unlikely(index >= Q_INDEX_MAX)) {
869*4882a593Smuzhiyun rt2x00_err(queue->rt2x00dev,
870*4882a593Smuzhiyun "Index change on invalid index type (%d)\n", index);
871*4882a593Smuzhiyun return;
872*4882a593Smuzhiyun }
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun spin_lock_irqsave(&queue->index_lock, irqflags);
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun queue->index[index]++;
877*4882a593Smuzhiyun if (queue->index[index] >= queue->limit)
878*4882a593Smuzhiyun queue->index[index] = 0;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun entry->last_action = jiffies;
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun if (index == Q_INDEX) {
883*4882a593Smuzhiyun queue->length++;
884*4882a593Smuzhiyun } else if (index == Q_INDEX_DONE) {
885*4882a593Smuzhiyun queue->length--;
886*4882a593Smuzhiyun queue->count++;
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun spin_unlock_irqrestore(&queue->index_lock, irqflags);
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
rt2x00queue_pause_queue_nocheck(struct data_queue * queue)892*4882a593Smuzhiyun static void rt2x00queue_pause_queue_nocheck(struct data_queue *queue)
893*4882a593Smuzhiyun {
894*4882a593Smuzhiyun switch (queue->qid) {
895*4882a593Smuzhiyun case QID_AC_VO:
896*4882a593Smuzhiyun case QID_AC_VI:
897*4882a593Smuzhiyun case QID_AC_BE:
898*4882a593Smuzhiyun case QID_AC_BK:
899*4882a593Smuzhiyun /*
900*4882a593Smuzhiyun * For TX queues, we have to disable the queue
901*4882a593Smuzhiyun * inside mac80211.
902*4882a593Smuzhiyun */
903*4882a593Smuzhiyun ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
904*4882a593Smuzhiyun break;
905*4882a593Smuzhiyun default:
906*4882a593Smuzhiyun break;
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun }
rt2x00queue_pause_queue(struct data_queue * queue)909*4882a593Smuzhiyun void rt2x00queue_pause_queue(struct data_queue *queue)
910*4882a593Smuzhiyun {
911*4882a593Smuzhiyun if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
912*4882a593Smuzhiyun !test_bit(QUEUE_STARTED, &queue->flags) ||
913*4882a593Smuzhiyun test_and_set_bit(QUEUE_PAUSED, &queue->flags))
914*4882a593Smuzhiyun return;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun rt2x00queue_pause_queue_nocheck(queue);
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue);
919*4882a593Smuzhiyun
rt2x00queue_unpause_queue(struct data_queue * queue)920*4882a593Smuzhiyun void rt2x00queue_unpause_queue(struct data_queue *queue)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
923*4882a593Smuzhiyun !test_bit(QUEUE_STARTED, &queue->flags) ||
924*4882a593Smuzhiyun !test_and_clear_bit(QUEUE_PAUSED, &queue->flags))
925*4882a593Smuzhiyun return;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun switch (queue->qid) {
928*4882a593Smuzhiyun case QID_AC_VO:
929*4882a593Smuzhiyun case QID_AC_VI:
930*4882a593Smuzhiyun case QID_AC_BE:
931*4882a593Smuzhiyun case QID_AC_BK:
932*4882a593Smuzhiyun /*
933*4882a593Smuzhiyun * For TX queues, we have to enable the queue
934*4882a593Smuzhiyun * inside mac80211.
935*4882a593Smuzhiyun */
936*4882a593Smuzhiyun ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
937*4882a593Smuzhiyun break;
938*4882a593Smuzhiyun case QID_RX:
939*4882a593Smuzhiyun /*
940*4882a593Smuzhiyun * For RX we need to kick the queue now in order to
941*4882a593Smuzhiyun * receive frames.
942*4882a593Smuzhiyun */
943*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->kick_queue(queue);
944*4882a593Smuzhiyun default:
945*4882a593Smuzhiyun break;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue);
949*4882a593Smuzhiyun
rt2x00queue_start_queue(struct data_queue * queue)950*4882a593Smuzhiyun void rt2x00queue_start_queue(struct data_queue *queue)
951*4882a593Smuzhiyun {
952*4882a593Smuzhiyun mutex_lock(&queue->status_lock);
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
955*4882a593Smuzhiyun test_and_set_bit(QUEUE_STARTED, &queue->flags)) {
956*4882a593Smuzhiyun mutex_unlock(&queue->status_lock);
957*4882a593Smuzhiyun return;
958*4882a593Smuzhiyun }
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun set_bit(QUEUE_PAUSED, &queue->flags);
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->start_queue(queue);
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun rt2x00queue_unpause_queue(queue);
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun mutex_unlock(&queue->status_lock);
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_start_queue);
969*4882a593Smuzhiyun
rt2x00queue_stop_queue(struct data_queue * queue)970*4882a593Smuzhiyun void rt2x00queue_stop_queue(struct data_queue *queue)
971*4882a593Smuzhiyun {
972*4882a593Smuzhiyun mutex_lock(&queue->status_lock);
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) {
975*4882a593Smuzhiyun mutex_unlock(&queue->status_lock);
976*4882a593Smuzhiyun return;
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun rt2x00queue_pause_queue_nocheck(queue);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->stop_queue(queue);
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun mutex_unlock(&queue->status_lock);
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue);
986*4882a593Smuzhiyun
rt2x00queue_flush_queue(struct data_queue * queue,bool drop)987*4882a593Smuzhiyun void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
988*4882a593Smuzhiyun {
989*4882a593Smuzhiyun bool tx_queue =
990*4882a593Smuzhiyun (queue->qid == QID_AC_VO) ||
991*4882a593Smuzhiyun (queue->qid == QID_AC_VI) ||
992*4882a593Smuzhiyun (queue->qid == QID_AC_BE) ||
993*4882a593Smuzhiyun (queue->qid == QID_AC_BK);
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun if (rt2x00queue_empty(queue))
996*4882a593Smuzhiyun return;
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun /*
999*4882a593Smuzhiyun * If we are not supposed to drop any pending
1000*4882a593Smuzhiyun * frames, this means we must force a start (=kick)
1001*4882a593Smuzhiyun * to the queue to make sure the hardware will
1002*4882a593Smuzhiyun * start transmitting.
1003*4882a593Smuzhiyun */
1004*4882a593Smuzhiyun if (!drop && tx_queue)
1005*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->kick_queue(queue);
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun /*
1008*4882a593Smuzhiyun * Check if driver supports flushing, if that is the case we can
1009*4882a593Smuzhiyun * defer the flushing to the driver. Otherwise we must use the
1010*4882a593Smuzhiyun * alternative which just waits for the queue to become empty.
1011*4882a593Smuzhiyun */
1012*4882a593Smuzhiyun if (likely(queue->rt2x00dev->ops->lib->flush_queue))
1013*4882a593Smuzhiyun queue->rt2x00dev->ops->lib->flush_queue(queue, drop);
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun /*
1016*4882a593Smuzhiyun * The queue flush has failed...
1017*4882a593Smuzhiyun */
1018*4882a593Smuzhiyun if (unlikely(!rt2x00queue_empty(queue)))
1019*4882a593Smuzhiyun rt2x00_warn(queue->rt2x00dev, "Queue %d failed to flush\n",
1020*4882a593Smuzhiyun queue->qid);
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue);
1023*4882a593Smuzhiyun
rt2x00queue_start_queues(struct rt2x00_dev * rt2x00dev)1024*4882a593Smuzhiyun void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev)
1025*4882a593Smuzhiyun {
1026*4882a593Smuzhiyun struct data_queue *queue;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun /*
1029*4882a593Smuzhiyun * rt2x00queue_start_queue will call ieee80211_wake_queue
1030*4882a593Smuzhiyun * for each queue after is has been properly initialized.
1031*4882a593Smuzhiyun */
1032*4882a593Smuzhiyun tx_queue_for_each(rt2x00dev, queue)
1033*4882a593Smuzhiyun rt2x00queue_start_queue(queue);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun rt2x00queue_start_queue(rt2x00dev->rx);
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_start_queues);
1038*4882a593Smuzhiyun
rt2x00queue_stop_queues(struct rt2x00_dev * rt2x00dev)1039*4882a593Smuzhiyun void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
1040*4882a593Smuzhiyun {
1041*4882a593Smuzhiyun struct data_queue *queue;
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun /*
1044*4882a593Smuzhiyun * rt2x00queue_stop_queue will call ieee80211_stop_queue
1045*4882a593Smuzhiyun * as well, but we are completely shutting doing everything
1046*4882a593Smuzhiyun * now, so it is much safer to stop all TX queues at once,
1047*4882a593Smuzhiyun * and use rt2x00queue_stop_queue for cleaning up.
1048*4882a593Smuzhiyun */
1049*4882a593Smuzhiyun ieee80211_stop_queues(rt2x00dev->hw);
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun tx_queue_for_each(rt2x00dev, queue)
1052*4882a593Smuzhiyun rt2x00queue_stop_queue(queue);
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun rt2x00queue_stop_queue(rt2x00dev->rx);
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues);
1057*4882a593Smuzhiyun
rt2x00queue_flush_queues(struct rt2x00_dev * rt2x00dev,bool drop)1058*4882a593Smuzhiyun void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop)
1059*4882a593Smuzhiyun {
1060*4882a593Smuzhiyun struct data_queue *queue;
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun tx_queue_for_each(rt2x00dev, queue)
1063*4882a593Smuzhiyun rt2x00queue_flush_queue(queue, drop);
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun rt2x00queue_flush_queue(rt2x00dev->rx, drop);
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues);
1068*4882a593Smuzhiyun
rt2x00queue_reset(struct data_queue * queue)1069*4882a593Smuzhiyun static void rt2x00queue_reset(struct data_queue *queue)
1070*4882a593Smuzhiyun {
1071*4882a593Smuzhiyun unsigned long irqflags;
1072*4882a593Smuzhiyun unsigned int i;
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun spin_lock_irqsave(&queue->index_lock, irqflags);
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun queue->count = 0;
1077*4882a593Smuzhiyun queue->length = 0;
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun for (i = 0; i < Q_INDEX_MAX; i++)
1080*4882a593Smuzhiyun queue->index[i] = 0;
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun spin_unlock_irqrestore(&queue->index_lock, irqflags);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
rt2x00queue_init_queues(struct rt2x00_dev * rt2x00dev)1085*4882a593Smuzhiyun void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
1086*4882a593Smuzhiyun {
1087*4882a593Smuzhiyun struct data_queue *queue;
1088*4882a593Smuzhiyun unsigned int i;
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun queue_for_each(rt2x00dev, queue) {
1091*4882a593Smuzhiyun rt2x00queue_reset(queue);
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun for (i = 0; i < queue->limit; i++)
1094*4882a593Smuzhiyun rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun
rt2x00queue_alloc_entries(struct data_queue * queue)1098*4882a593Smuzhiyun static int rt2x00queue_alloc_entries(struct data_queue *queue)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun struct queue_entry *entries;
1101*4882a593Smuzhiyun unsigned int entry_size;
1102*4882a593Smuzhiyun unsigned int i;
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun rt2x00queue_reset(queue);
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun /*
1107*4882a593Smuzhiyun * Allocate all queue entries.
1108*4882a593Smuzhiyun */
1109*4882a593Smuzhiyun entry_size = sizeof(*entries) + queue->priv_size;
1110*4882a593Smuzhiyun entries = kcalloc(queue->limit, entry_size, GFP_KERNEL);
1111*4882a593Smuzhiyun if (!entries)
1112*4882a593Smuzhiyun return -ENOMEM;
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
1115*4882a593Smuzhiyun (((char *)(__base)) + ((__limit) * (__esize)) + \
1116*4882a593Smuzhiyun ((__index) * (__psize)))
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun for (i = 0; i < queue->limit; i++) {
1119*4882a593Smuzhiyun entries[i].flags = 0;
1120*4882a593Smuzhiyun entries[i].queue = queue;
1121*4882a593Smuzhiyun entries[i].skb = NULL;
1122*4882a593Smuzhiyun entries[i].entry_idx = i;
1123*4882a593Smuzhiyun entries[i].priv_data =
1124*4882a593Smuzhiyun QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
1125*4882a593Smuzhiyun sizeof(*entries), queue->priv_size);
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun #undef QUEUE_ENTRY_PRIV_OFFSET
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun queue->entries = entries;
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun return 0;
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun
rt2x00queue_free_skbs(struct data_queue * queue)1135*4882a593Smuzhiyun static void rt2x00queue_free_skbs(struct data_queue *queue)
1136*4882a593Smuzhiyun {
1137*4882a593Smuzhiyun unsigned int i;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun if (!queue->entries)
1140*4882a593Smuzhiyun return;
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun for (i = 0; i < queue->limit; i++) {
1143*4882a593Smuzhiyun rt2x00queue_free_skb(&queue->entries[i]);
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun
rt2x00queue_alloc_rxskbs(struct data_queue * queue)1147*4882a593Smuzhiyun static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
1148*4882a593Smuzhiyun {
1149*4882a593Smuzhiyun unsigned int i;
1150*4882a593Smuzhiyun struct sk_buff *skb;
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun for (i = 0; i < queue->limit; i++) {
1153*4882a593Smuzhiyun skb = rt2x00queue_alloc_rxskb(&queue->entries[i], GFP_KERNEL);
1154*4882a593Smuzhiyun if (!skb)
1155*4882a593Smuzhiyun return -ENOMEM;
1156*4882a593Smuzhiyun queue->entries[i].skb = skb;
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun return 0;
1160*4882a593Smuzhiyun }
1161*4882a593Smuzhiyun
rt2x00queue_initialize(struct rt2x00_dev * rt2x00dev)1162*4882a593Smuzhiyun int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
1163*4882a593Smuzhiyun {
1164*4882a593Smuzhiyun struct data_queue *queue;
1165*4882a593Smuzhiyun int status;
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun status = rt2x00queue_alloc_entries(rt2x00dev->rx);
1168*4882a593Smuzhiyun if (status)
1169*4882a593Smuzhiyun goto exit;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun tx_queue_for_each(rt2x00dev, queue) {
1172*4882a593Smuzhiyun status = rt2x00queue_alloc_entries(queue);
1173*4882a593Smuzhiyun if (status)
1174*4882a593Smuzhiyun goto exit;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun status = rt2x00queue_alloc_entries(rt2x00dev->bcn);
1178*4882a593Smuzhiyun if (status)
1179*4882a593Smuzhiyun goto exit;
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun if (rt2x00_has_cap_flag(rt2x00dev, REQUIRE_ATIM_QUEUE)) {
1182*4882a593Smuzhiyun status = rt2x00queue_alloc_entries(rt2x00dev->atim);
1183*4882a593Smuzhiyun if (status)
1184*4882a593Smuzhiyun goto exit;
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
1188*4882a593Smuzhiyun if (status)
1189*4882a593Smuzhiyun goto exit;
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun return 0;
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun exit:
1194*4882a593Smuzhiyun rt2x00_err(rt2x00dev, "Queue entries allocation failed\n");
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun rt2x00queue_uninitialize(rt2x00dev);
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun return status;
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
rt2x00queue_uninitialize(struct rt2x00_dev * rt2x00dev)1201*4882a593Smuzhiyun void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun struct data_queue *queue;
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun rt2x00queue_free_skbs(rt2x00dev->rx);
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun queue_for_each(rt2x00dev, queue) {
1208*4882a593Smuzhiyun kfree(queue->entries);
1209*4882a593Smuzhiyun queue->entries = NULL;
1210*4882a593Smuzhiyun }
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun
rt2x00queue_init(struct rt2x00_dev * rt2x00dev,struct data_queue * queue,enum data_queue_qid qid)1213*4882a593Smuzhiyun static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
1214*4882a593Smuzhiyun struct data_queue *queue, enum data_queue_qid qid)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun mutex_init(&queue->status_lock);
1217*4882a593Smuzhiyun spin_lock_init(&queue->tx_lock);
1218*4882a593Smuzhiyun spin_lock_init(&queue->index_lock);
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun queue->rt2x00dev = rt2x00dev;
1221*4882a593Smuzhiyun queue->qid = qid;
1222*4882a593Smuzhiyun queue->txop = 0;
1223*4882a593Smuzhiyun queue->aifs = 2;
1224*4882a593Smuzhiyun queue->cw_min = 5;
1225*4882a593Smuzhiyun queue->cw_max = 10;
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun rt2x00dev->ops->queue_init(queue);
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun queue->threshold = DIV_ROUND_UP(queue->limit, 10);
1230*4882a593Smuzhiyun }
1231*4882a593Smuzhiyun
rt2x00queue_allocate(struct rt2x00_dev * rt2x00dev)1232*4882a593Smuzhiyun int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
1233*4882a593Smuzhiyun {
1234*4882a593Smuzhiyun struct data_queue *queue;
1235*4882a593Smuzhiyun enum data_queue_qid qid;
1236*4882a593Smuzhiyun unsigned int req_atim =
1237*4882a593Smuzhiyun rt2x00_has_cap_flag(rt2x00dev, REQUIRE_ATIM_QUEUE);
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun /*
1240*4882a593Smuzhiyun * We need the following queues:
1241*4882a593Smuzhiyun * RX: 1
1242*4882a593Smuzhiyun * TX: ops->tx_queues
1243*4882a593Smuzhiyun * Beacon: 1
1244*4882a593Smuzhiyun * Atim: 1 (if required)
1245*4882a593Smuzhiyun */
1246*4882a593Smuzhiyun rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL);
1249*4882a593Smuzhiyun if (!queue)
1250*4882a593Smuzhiyun return -ENOMEM;
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun /*
1253*4882a593Smuzhiyun * Initialize pointers
1254*4882a593Smuzhiyun */
1255*4882a593Smuzhiyun rt2x00dev->rx = queue;
1256*4882a593Smuzhiyun rt2x00dev->tx = &queue[1];
1257*4882a593Smuzhiyun rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
1258*4882a593Smuzhiyun rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun /*
1261*4882a593Smuzhiyun * Initialize queue parameters.
1262*4882a593Smuzhiyun * RX: qid = QID_RX
1263*4882a593Smuzhiyun * TX: qid = QID_AC_VO + index
1264*4882a593Smuzhiyun * TX: cw_min: 2^5 = 32.
1265*4882a593Smuzhiyun * TX: cw_max: 2^10 = 1024.
1266*4882a593Smuzhiyun * BCN: qid = QID_BEACON
1267*4882a593Smuzhiyun * ATIM: qid = QID_ATIM
1268*4882a593Smuzhiyun */
1269*4882a593Smuzhiyun rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun qid = QID_AC_VO;
1272*4882a593Smuzhiyun tx_queue_for_each(rt2x00dev, queue)
1273*4882a593Smuzhiyun rt2x00queue_init(rt2x00dev, queue, qid++);
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
1276*4882a593Smuzhiyun if (req_atim)
1277*4882a593Smuzhiyun rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun return 0;
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
rt2x00queue_free(struct rt2x00_dev * rt2x00dev)1282*4882a593Smuzhiyun void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
1283*4882a593Smuzhiyun {
1284*4882a593Smuzhiyun kfree(rt2x00dev->rx);
1285*4882a593Smuzhiyun rt2x00dev->rx = NULL;
1286*4882a593Smuzhiyun rt2x00dev->tx = NULL;
1287*4882a593Smuzhiyun rt2x00dev->bcn = NULL;
1288*4882a593Smuzhiyun }
1289