xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4*4882a593Smuzhiyun 	<http://rt2x00.serialmonkey.com>
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun 	Module: rt2x00mmio
10*4882a593Smuzhiyun 	Abstract: rt2x00 generic mmio device routines.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/dma-mapping.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "rt2x00.h"
19*4882a593Smuzhiyun #include "rt2x00mmio.h"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun  * Register access.
23*4882a593Smuzhiyun  */
rt2x00mmio_regbusy_read(struct rt2x00_dev * rt2x00dev,const unsigned int offset,const struct rt2x00_field32 field,u32 * reg)24*4882a593Smuzhiyun int rt2x00mmio_regbusy_read(struct rt2x00_dev *rt2x00dev,
25*4882a593Smuzhiyun 			    const unsigned int offset,
26*4882a593Smuzhiyun 			    const struct rt2x00_field32 field,
27*4882a593Smuzhiyun 			    u32 *reg)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	unsigned int i;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
32*4882a593Smuzhiyun 		return 0;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
35*4882a593Smuzhiyun 		*reg = rt2x00mmio_register_read(rt2x00dev, offset);
36*4882a593Smuzhiyun 		if (!rt2x00_get_field32(*reg, field))
37*4882a593Smuzhiyun 			return 1;
38*4882a593Smuzhiyun 		udelay(REGISTER_BUSY_DELAY);
39*4882a593Smuzhiyun 	}
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	printk_once(KERN_ERR "%s() Indirect register access failed: "
42*4882a593Smuzhiyun 	      "offset=0x%.08x, value=0x%.08x\n", __func__, offset, *reg);
43*4882a593Smuzhiyun 	*reg = ~0;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00mmio_regbusy_read);
48*4882a593Smuzhiyun 
rt2x00mmio_rxdone(struct rt2x00_dev * rt2x00dev)49*4882a593Smuzhiyun bool rt2x00mmio_rxdone(struct rt2x00_dev *rt2x00dev)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct data_queue *queue = rt2x00dev->rx;
52*4882a593Smuzhiyun 	struct queue_entry *entry;
53*4882a593Smuzhiyun 	struct queue_entry_priv_mmio *entry_priv;
54*4882a593Smuzhiyun 	struct skb_frame_desc *skbdesc;
55*4882a593Smuzhiyun 	int max_rx = 16;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	while (--max_rx) {
58*4882a593Smuzhiyun 		entry = rt2x00queue_get_entry(queue, Q_INDEX);
59*4882a593Smuzhiyun 		entry_priv = entry->priv_data;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 		if (rt2x00dev->ops->lib->get_entry_state(entry))
62*4882a593Smuzhiyun 			break;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 		/*
65*4882a593Smuzhiyun 		 * Fill in desc fields of the skb descriptor
66*4882a593Smuzhiyun 		 */
67*4882a593Smuzhiyun 		skbdesc = get_skb_frame_desc(entry->skb);
68*4882a593Smuzhiyun 		skbdesc->desc = entry_priv->desc;
69*4882a593Smuzhiyun 		skbdesc->desc_len = entry->queue->desc_size;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 		/*
72*4882a593Smuzhiyun 		 * DMA is already done, notify rt2x00lib that
73*4882a593Smuzhiyun 		 * it finished successfully.
74*4882a593Smuzhiyun 		 */
75*4882a593Smuzhiyun 		rt2x00lib_dmastart(entry);
76*4882a593Smuzhiyun 		rt2x00lib_dmadone(entry);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 		/*
79*4882a593Smuzhiyun 		 * Send the frame to rt2x00lib for further processing.
80*4882a593Smuzhiyun 		 */
81*4882a593Smuzhiyun 		rt2x00lib_rxdone(entry, GFP_ATOMIC);
82*4882a593Smuzhiyun 	}
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	return !max_rx;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00mmio_rxdone);
87*4882a593Smuzhiyun 
rt2x00mmio_flush_queue(struct data_queue * queue,bool drop)88*4882a593Smuzhiyun void rt2x00mmio_flush_queue(struct data_queue *queue, bool drop)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	unsigned int i;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)
93*4882a593Smuzhiyun 		msleep(50);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00mmio_flush_queue);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun  * Device initialization handlers.
99*4882a593Smuzhiyun  */
rt2x00mmio_alloc_queue_dma(struct rt2x00_dev * rt2x00dev,struct data_queue * queue)100*4882a593Smuzhiyun static int rt2x00mmio_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
101*4882a593Smuzhiyun 				      struct data_queue *queue)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct queue_entry_priv_mmio *entry_priv;
104*4882a593Smuzhiyun 	void *addr;
105*4882a593Smuzhiyun 	dma_addr_t dma;
106*4882a593Smuzhiyun 	unsigned int i;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/*
109*4882a593Smuzhiyun 	 * Allocate DMA memory for descriptor and buffer.
110*4882a593Smuzhiyun 	 */
111*4882a593Smuzhiyun 	addr = dma_alloc_coherent(rt2x00dev->dev,
112*4882a593Smuzhiyun 				  queue->limit * queue->desc_size, &dma,
113*4882a593Smuzhiyun 				  GFP_KERNEL);
114*4882a593Smuzhiyun 	if (!addr)
115*4882a593Smuzhiyun 		return -ENOMEM;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/*
118*4882a593Smuzhiyun 	 * Initialize all queue entries to contain valid addresses.
119*4882a593Smuzhiyun 	 */
120*4882a593Smuzhiyun 	for (i = 0; i < queue->limit; i++) {
121*4882a593Smuzhiyun 		entry_priv = queue->entries[i].priv_data;
122*4882a593Smuzhiyun 		entry_priv->desc = addr + i * queue->desc_size;
123*4882a593Smuzhiyun 		entry_priv->desc_dma = dma + i * queue->desc_size;
124*4882a593Smuzhiyun 	}
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
rt2x00mmio_free_queue_dma(struct rt2x00_dev * rt2x00dev,struct data_queue * queue)129*4882a593Smuzhiyun static void rt2x00mmio_free_queue_dma(struct rt2x00_dev *rt2x00dev,
130*4882a593Smuzhiyun 				      struct data_queue *queue)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	struct queue_entry_priv_mmio *entry_priv =
133*4882a593Smuzhiyun 	    queue->entries[0].priv_data;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (entry_priv->desc)
136*4882a593Smuzhiyun 		dma_free_coherent(rt2x00dev->dev,
137*4882a593Smuzhiyun 				  queue->limit * queue->desc_size,
138*4882a593Smuzhiyun 				  entry_priv->desc, entry_priv->desc_dma);
139*4882a593Smuzhiyun 	entry_priv->desc = NULL;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
rt2x00mmio_initialize(struct rt2x00_dev * rt2x00dev)142*4882a593Smuzhiyun int rt2x00mmio_initialize(struct rt2x00_dev *rt2x00dev)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	struct data_queue *queue;
145*4882a593Smuzhiyun 	int status;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/*
148*4882a593Smuzhiyun 	 * Allocate DMA
149*4882a593Smuzhiyun 	 */
150*4882a593Smuzhiyun 	queue_for_each(rt2x00dev, queue) {
151*4882a593Smuzhiyun 		status = rt2x00mmio_alloc_queue_dma(rt2x00dev, queue);
152*4882a593Smuzhiyun 		if (status)
153*4882a593Smuzhiyun 			goto exit;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/*
157*4882a593Smuzhiyun 	 * Register interrupt handler.
158*4882a593Smuzhiyun 	 */
159*4882a593Smuzhiyun 	status = request_irq(rt2x00dev->irq,
160*4882a593Smuzhiyun 			     rt2x00dev->ops->lib->irq_handler,
161*4882a593Smuzhiyun 			     IRQF_SHARED, rt2x00dev->name, rt2x00dev);
162*4882a593Smuzhiyun 	if (status) {
163*4882a593Smuzhiyun 		rt2x00_err(rt2x00dev, "IRQ %d allocation failed (error %d)\n",
164*4882a593Smuzhiyun 			   rt2x00dev->irq, status);
165*4882a593Smuzhiyun 		goto exit;
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	return 0;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun exit:
171*4882a593Smuzhiyun 	queue_for_each(rt2x00dev, queue)
172*4882a593Smuzhiyun 		rt2x00mmio_free_queue_dma(rt2x00dev, queue);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	return status;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00mmio_initialize);
177*4882a593Smuzhiyun 
rt2x00mmio_uninitialize(struct rt2x00_dev * rt2x00dev)178*4882a593Smuzhiyun void rt2x00mmio_uninitialize(struct rt2x00_dev *rt2x00dev)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	struct data_queue *queue;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	/*
183*4882a593Smuzhiyun 	 * Free irq line.
184*4882a593Smuzhiyun 	 */
185*4882a593Smuzhiyun 	free_irq(rt2x00dev->irq, rt2x00dev);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	/*
188*4882a593Smuzhiyun 	 * Free DMA
189*4882a593Smuzhiyun 	 */
190*4882a593Smuzhiyun 	queue_for_each(rt2x00dev, queue)
191*4882a593Smuzhiyun 		rt2x00mmio_free_queue_dma(rt2x00dev, queue);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rt2x00mmio_uninitialize);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun  * rt2x00mmio module information.
197*4882a593Smuzhiyun  */
198*4882a593Smuzhiyun MODULE_AUTHOR(DRV_PROJECT);
199*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
200*4882a593Smuzhiyun MODULE_DESCRIPTION("rt2x00 mmio library");
201*4882a593Smuzhiyun MODULE_LICENSE("GPL");
202