1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4*4882a593Smuzhiyun Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
5*4882a593Smuzhiyun Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6*4882a593Smuzhiyun <http://rt2x00.serialmonkey.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun Module: rt2x00
12*4882a593Smuzhiyun Abstract: rt2x00 global information.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #ifndef RT2X00_H
16*4882a593Smuzhiyun #define RT2X00_H
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/bitops.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/skbuff.h>
21*4882a593Smuzhiyun #include <linux/workqueue.h>
22*4882a593Smuzhiyun #include <linux/firmware.h>
23*4882a593Smuzhiyun #include <linux/leds.h>
24*4882a593Smuzhiyun #include <linux/mutex.h>
25*4882a593Smuzhiyun #include <linux/etherdevice.h>
26*4882a593Smuzhiyun #include <linux/kfifo.h>
27*4882a593Smuzhiyun #include <linux/hrtimer.h>
28*4882a593Smuzhiyun #include <linux/average.h>
29*4882a593Smuzhiyun #include <linux/usb.h>
30*4882a593Smuzhiyun #include <linux/clk.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <net/mac80211.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include "rt2x00debug.h"
35*4882a593Smuzhiyun #include "rt2x00dump.h"
36*4882a593Smuzhiyun #include "rt2x00leds.h"
37*4882a593Smuzhiyun #include "rt2x00reg.h"
38*4882a593Smuzhiyun #include "rt2x00queue.h"
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * Module information.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun #define DRV_VERSION "2.3.0"
44*4882a593Smuzhiyun #define DRV_PROJECT "http://rt2x00.serialmonkey.com"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Debug definitions.
47*4882a593Smuzhiyun * Debug output has to be enabled during compile time.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_DEBUG
50*4882a593Smuzhiyun #define DEBUG
51*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_DEBUG */
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Utility printing macros
54*4882a593Smuzhiyun * rt2x00_probe_err is for messages when rt2x00_dev is uninitialized
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun #define rt2x00_probe_err(fmt, ...) \
57*4882a593Smuzhiyun printk(KERN_ERR KBUILD_MODNAME ": %s: Error - " fmt, \
58*4882a593Smuzhiyun __func__, ##__VA_ARGS__)
59*4882a593Smuzhiyun #define rt2x00_err(dev, fmt, ...) \
60*4882a593Smuzhiyun wiphy_err_ratelimited((dev)->hw->wiphy, "%s: Error - " fmt, \
61*4882a593Smuzhiyun __func__, ##__VA_ARGS__)
62*4882a593Smuzhiyun #define rt2x00_warn(dev, fmt, ...) \
63*4882a593Smuzhiyun wiphy_warn_ratelimited((dev)->hw->wiphy, "%s: Warning - " fmt, \
64*4882a593Smuzhiyun __func__, ##__VA_ARGS__)
65*4882a593Smuzhiyun #define rt2x00_info(dev, fmt, ...) \
66*4882a593Smuzhiyun wiphy_info((dev)->hw->wiphy, "%s: Info - " fmt, \
67*4882a593Smuzhiyun __func__, ##__VA_ARGS__)
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Various debug levels */
70*4882a593Smuzhiyun #define rt2x00_dbg(dev, fmt, ...) \
71*4882a593Smuzhiyun wiphy_dbg((dev)->hw->wiphy, "%s: Debug - " fmt, \
72*4882a593Smuzhiyun __func__, ##__VA_ARGS__)
73*4882a593Smuzhiyun #define rt2x00_eeprom_dbg(dev, fmt, ...) \
74*4882a593Smuzhiyun wiphy_dbg((dev)->hw->wiphy, "%s: EEPROM recovery - " fmt, \
75*4882a593Smuzhiyun __func__, ##__VA_ARGS__)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * Duration calculations
79*4882a593Smuzhiyun * The rate variable passed is: 100kbs.
80*4882a593Smuzhiyun * To convert from bytes to bits we multiply size with 8,
81*4882a593Smuzhiyun * then the size is multiplied with 10 to make the
82*4882a593Smuzhiyun * real rate -> rate argument correction.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun #define GET_DURATION(__size, __rate) (((__size) * 8 * 10) / (__rate))
85*4882a593Smuzhiyun #define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate))
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * Determine the number of L2 padding bytes required between the header and
89*4882a593Smuzhiyun * the payload.
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun #define L2PAD_SIZE(__hdrlen) (-(__hdrlen) & 3)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun * Determine the alignment requirement,
95*4882a593Smuzhiyun * to make sure the 802.11 payload is padded to a 4-byte boundrary
96*4882a593Smuzhiyun * we must determine the address of the payload and calculate the
97*4882a593Smuzhiyun * amount of bytes needed to move the data.
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun #define ALIGN_SIZE(__skb, __header) \
100*4882a593Smuzhiyun (((unsigned long)((__skb)->data + (__header))) & 3)
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * Constants for extra TX headroom for alignment purposes.
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun #define RT2X00_ALIGN_SIZE 4 /* Only whole frame needs alignment */
106*4882a593Smuzhiyun #define RT2X00_L2PAD_SIZE 8 /* Both header & payload need alignment */
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * Standard timing and size defines.
110*4882a593Smuzhiyun * These values should follow the ieee80211 specifications.
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun #define ACK_SIZE 14
113*4882a593Smuzhiyun #define IEEE80211_HEADER 24
114*4882a593Smuzhiyun #define PLCP 48
115*4882a593Smuzhiyun #define BEACON 100
116*4882a593Smuzhiyun #define PREAMBLE 144
117*4882a593Smuzhiyun #define SHORT_PREAMBLE 72
118*4882a593Smuzhiyun #define SLOT_TIME 20
119*4882a593Smuzhiyun #define SHORT_SLOT_TIME 9
120*4882a593Smuzhiyun #define SIFS 10
121*4882a593Smuzhiyun #define PIFS (SIFS + SLOT_TIME)
122*4882a593Smuzhiyun #define SHORT_PIFS (SIFS + SHORT_SLOT_TIME)
123*4882a593Smuzhiyun #define DIFS (PIFS + SLOT_TIME)
124*4882a593Smuzhiyun #define SHORT_DIFS (SHORT_PIFS + SHORT_SLOT_TIME)
125*4882a593Smuzhiyun #define EIFS (SIFS + DIFS + \
126*4882a593Smuzhiyun GET_DURATION(IEEE80211_HEADER + ACK_SIZE, 10))
127*4882a593Smuzhiyun #define SHORT_EIFS (SIFS + SHORT_DIFS + \
128*4882a593Smuzhiyun GET_DURATION(IEEE80211_HEADER + ACK_SIZE, 10))
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun enum rt2x00_chip_intf {
131*4882a593Smuzhiyun RT2X00_CHIP_INTF_PCI,
132*4882a593Smuzhiyun RT2X00_CHIP_INTF_PCIE,
133*4882a593Smuzhiyun RT2X00_CHIP_INTF_USB,
134*4882a593Smuzhiyun RT2X00_CHIP_INTF_SOC,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun * Chipset identification
139*4882a593Smuzhiyun * The chipset on the device is composed of a RT and RF chip.
140*4882a593Smuzhiyun * The chipset combination is important for determining device capabilities.
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun struct rt2x00_chip {
143*4882a593Smuzhiyun u16 rt;
144*4882a593Smuzhiyun #define RT2460 0x2460
145*4882a593Smuzhiyun #define RT2560 0x2560
146*4882a593Smuzhiyun #define RT2570 0x2570
147*4882a593Smuzhiyun #define RT2661 0x2661
148*4882a593Smuzhiyun #define RT2573 0x2573
149*4882a593Smuzhiyun #define RT2860 0x2860 /* 2.4GHz */
150*4882a593Smuzhiyun #define RT2872 0x2872 /* WSOC */
151*4882a593Smuzhiyun #define RT2883 0x2883 /* WSOC */
152*4882a593Smuzhiyun #define RT3070 0x3070
153*4882a593Smuzhiyun #define RT3071 0x3071
154*4882a593Smuzhiyun #define RT3090 0x3090 /* 2.4GHz PCIe */
155*4882a593Smuzhiyun #define RT3290 0x3290
156*4882a593Smuzhiyun #define RT3352 0x3352 /* WSOC */
157*4882a593Smuzhiyun #define RT3390 0x3390
158*4882a593Smuzhiyun #define RT3572 0x3572
159*4882a593Smuzhiyun #define RT3593 0x3593
160*4882a593Smuzhiyun #define RT3883 0x3883 /* WSOC */
161*4882a593Smuzhiyun #define RT5350 0x5350 /* WSOC 2.4GHz */
162*4882a593Smuzhiyun #define RT5390 0x5390 /* 2.4GHz */
163*4882a593Smuzhiyun #define RT5392 0x5392 /* 2.4GHz */
164*4882a593Smuzhiyun #define RT5592 0x5592
165*4882a593Smuzhiyun #define RT6352 0x6352 /* WSOC 2.4GHz */
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun u16 rf;
168*4882a593Smuzhiyun u16 rev;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun enum rt2x00_chip_intf intf;
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun * RF register values that belong to a particular channel.
175*4882a593Smuzhiyun */
176*4882a593Smuzhiyun struct rf_channel {
177*4882a593Smuzhiyun int channel;
178*4882a593Smuzhiyun u32 rf1;
179*4882a593Smuzhiyun u32 rf2;
180*4882a593Smuzhiyun u32 rf3;
181*4882a593Smuzhiyun u32 rf4;
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun * Channel information structure
186*4882a593Smuzhiyun */
187*4882a593Smuzhiyun struct channel_info {
188*4882a593Smuzhiyun unsigned int flags;
189*4882a593Smuzhiyun #define GEOGRAPHY_ALLOWED 0x00000001
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun short max_power;
192*4882a593Smuzhiyun short default_power1;
193*4882a593Smuzhiyun short default_power2;
194*4882a593Smuzhiyun short default_power3;
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun /*
198*4882a593Smuzhiyun * Antenna setup values.
199*4882a593Smuzhiyun */
200*4882a593Smuzhiyun struct antenna_setup {
201*4882a593Smuzhiyun enum antenna rx;
202*4882a593Smuzhiyun enum antenna tx;
203*4882a593Smuzhiyun u8 rx_chain_num;
204*4882a593Smuzhiyun u8 tx_chain_num;
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /*
208*4882a593Smuzhiyun * Quality statistics about the currently active link.
209*4882a593Smuzhiyun */
210*4882a593Smuzhiyun struct link_qual {
211*4882a593Smuzhiyun /*
212*4882a593Smuzhiyun * Statistics required for Link tuning by driver
213*4882a593Smuzhiyun * The rssi value is provided by rt2x00lib during the
214*4882a593Smuzhiyun * link_tuner() callback function.
215*4882a593Smuzhiyun * The false_cca field is filled during the link_stats()
216*4882a593Smuzhiyun * callback function and could be used during the
217*4882a593Smuzhiyun * link_tuner() callback function.
218*4882a593Smuzhiyun */
219*4882a593Smuzhiyun int rssi;
220*4882a593Smuzhiyun int false_cca;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /*
223*4882a593Smuzhiyun * VGC levels
224*4882a593Smuzhiyun * Hardware driver will tune the VGC level during each call
225*4882a593Smuzhiyun * to the link_tuner() callback function. This vgc_level is
226*4882a593Smuzhiyun * is determined based on the link quality statistics like
227*4882a593Smuzhiyun * average RSSI and the false CCA count.
228*4882a593Smuzhiyun *
229*4882a593Smuzhiyun * In some cases the drivers need to differentiate between
230*4882a593Smuzhiyun * the currently "desired" VGC level and the level configured
231*4882a593Smuzhiyun * in the hardware. The latter is important to reduce the
232*4882a593Smuzhiyun * number of BBP register reads to reduce register access
233*4882a593Smuzhiyun * overhead. For this reason we store both values here.
234*4882a593Smuzhiyun */
235*4882a593Smuzhiyun u8 vgc_level;
236*4882a593Smuzhiyun u8 vgc_level_reg;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /*
239*4882a593Smuzhiyun * Statistics required for Signal quality calculation.
240*4882a593Smuzhiyun * These fields might be changed during the link_stats()
241*4882a593Smuzhiyun * callback function.
242*4882a593Smuzhiyun */
243*4882a593Smuzhiyun int rx_success;
244*4882a593Smuzhiyun int rx_failed;
245*4882a593Smuzhiyun int tx_success;
246*4882a593Smuzhiyun int tx_failed;
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun DECLARE_EWMA(rssi, 10, 8)
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /*
252*4882a593Smuzhiyun * Antenna settings about the currently active link.
253*4882a593Smuzhiyun */
254*4882a593Smuzhiyun struct link_ant {
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun * Antenna flags
257*4882a593Smuzhiyun */
258*4882a593Smuzhiyun unsigned int flags;
259*4882a593Smuzhiyun #define ANTENNA_RX_DIVERSITY 0x00000001
260*4882a593Smuzhiyun #define ANTENNA_TX_DIVERSITY 0x00000002
261*4882a593Smuzhiyun #define ANTENNA_MODE_SAMPLE 0x00000004
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * Currently active TX/RX antenna setup.
265*4882a593Smuzhiyun * When software diversity is used, this will indicate
266*4882a593Smuzhiyun * which antenna is actually used at this time.
267*4882a593Smuzhiyun */
268*4882a593Smuzhiyun struct antenna_setup active;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun * RSSI history information for the antenna.
272*4882a593Smuzhiyun * Used to determine when to switch antenna
273*4882a593Smuzhiyun * when using software diversity.
274*4882a593Smuzhiyun */
275*4882a593Smuzhiyun int rssi_history;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun /*
278*4882a593Smuzhiyun * Current RSSI average of the currently active antenna.
279*4882a593Smuzhiyun * Similar to the avg_rssi in the link_qual structure
280*4882a593Smuzhiyun * this value is updated by using the walking average.
281*4882a593Smuzhiyun */
282*4882a593Smuzhiyun struct ewma_rssi rssi_ant;
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun * To optimize the quality of the link we need to store
287*4882a593Smuzhiyun * the quality of received frames and periodically
288*4882a593Smuzhiyun * optimize the link.
289*4882a593Smuzhiyun */
290*4882a593Smuzhiyun struct link {
291*4882a593Smuzhiyun /*
292*4882a593Smuzhiyun * Link tuner counter
293*4882a593Smuzhiyun * The number of times the link has been tuned
294*4882a593Smuzhiyun * since the radio has been switched on.
295*4882a593Smuzhiyun */
296*4882a593Smuzhiyun u32 count;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /*
299*4882a593Smuzhiyun * Quality measurement values.
300*4882a593Smuzhiyun */
301*4882a593Smuzhiyun struct link_qual qual;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /*
304*4882a593Smuzhiyun * TX/RX antenna setup.
305*4882a593Smuzhiyun */
306*4882a593Smuzhiyun struct link_ant ant;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /*
309*4882a593Smuzhiyun * Currently active average RSSI value
310*4882a593Smuzhiyun */
311*4882a593Smuzhiyun struct ewma_rssi avg_rssi;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /*
314*4882a593Smuzhiyun * Work structure for scheduling periodic link tuning.
315*4882a593Smuzhiyun */
316*4882a593Smuzhiyun struct delayed_work work;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /*
319*4882a593Smuzhiyun * Work structure for scheduling periodic watchdog monitoring.
320*4882a593Smuzhiyun * This work must be scheduled on the kernel workqueue, while
321*4882a593Smuzhiyun * all other work structures must be queued on the mac80211
322*4882a593Smuzhiyun * workqueue. This guarantees that the watchdog can schedule
323*4882a593Smuzhiyun * other work structures and wait for their completion in order
324*4882a593Smuzhiyun * to bring the device/driver back into the desired state.
325*4882a593Smuzhiyun */
326*4882a593Smuzhiyun struct delayed_work watchdog_work;
327*4882a593Smuzhiyun unsigned int watchdog_interval;
328*4882a593Smuzhiyun bool watchdog_disabled;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /*
331*4882a593Smuzhiyun * Work structure for scheduling periodic AGC adjustments.
332*4882a593Smuzhiyun */
333*4882a593Smuzhiyun struct delayed_work agc_work;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /*
336*4882a593Smuzhiyun * Work structure for scheduling periodic VCO calibration.
337*4882a593Smuzhiyun */
338*4882a593Smuzhiyun struct delayed_work vco_work;
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun enum rt2x00_delayed_flags {
342*4882a593Smuzhiyun DELAYED_UPDATE_BEACON,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /*
346*4882a593Smuzhiyun * Interface structure
347*4882a593Smuzhiyun * Per interface configuration details, this structure
348*4882a593Smuzhiyun * is allocated as the private data for ieee80211_vif.
349*4882a593Smuzhiyun */
350*4882a593Smuzhiyun struct rt2x00_intf {
351*4882a593Smuzhiyun /*
352*4882a593Smuzhiyun * beacon->skb must be protected with the mutex.
353*4882a593Smuzhiyun */
354*4882a593Smuzhiyun struct mutex beacon_skb_mutex;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /*
357*4882a593Smuzhiyun * Entry in the beacon queue which belongs to
358*4882a593Smuzhiyun * this interface. Each interface has its own
359*4882a593Smuzhiyun * dedicated beacon entry.
360*4882a593Smuzhiyun */
361*4882a593Smuzhiyun struct queue_entry *beacon;
362*4882a593Smuzhiyun bool enable_beacon;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun /*
365*4882a593Smuzhiyun * Actions that needed rescheduling.
366*4882a593Smuzhiyun */
367*4882a593Smuzhiyun unsigned long delayed_flags;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun /*
370*4882a593Smuzhiyun * Software sequence counter, this is only required
371*4882a593Smuzhiyun * for hardware which doesn't support hardware
372*4882a593Smuzhiyun * sequence counting.
373*4882a593Smuzhiyun */
374*4882a593Smuzhiyun atomic_t seqno;
375*4882a593Smuzhiyun };
376*4882a593Smuzhiyun
vif_to_intf(struct ieee80211_vif * vif)377*4882a593Smuzhiyun static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif)
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun return (struct rt2x00_intf *)vif->drv_priv;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun /**
383*4882a593Smuzhiyun * struct hw_mode_spec: Hardware specifications structure
384*4882a593Smuzhiyun *
385*4882a593Smuzhiyun * Details about the supported modes, rates and channels
386*4882a593Smuzhiyun * of a particular chipset. This is used by rt2x00lib
387*4882a593Smuzhiyun * to build the ieee80211_hw_mode array for mac80211.
388*4882a593Smuzhiyun *
389*4882a593Smuzhiyun * @supported_bands: Bitmask contained the supported bands (2.4GHz, 5.2GHz).
390*4882a593Smuzhiyun * @supported_rates: Rate types which are supported (CCK, OFDM).
391*4882a593Smuzhiyun * @num_channels: Number of supported channels. This is used as array size
392*4882a593Smuzhiyun * for @tx_power_a, @tx_power_bg and @channels.
393*4882a593Smuzhiyun * @channels: Device/chipset specific channel values (See &struct rf_channel).
394*4882a593Smuzhiyun * @channels_info: Additional information for channels (See &struct channel_info).
395*4882a593Smuzhiyun * @ht: Driver HT Capabilities (See &ieee80211_sta_ht_cap).
396*4882a593Smuzhiyun */
397*4882a593Smuzhiyun struct hw_mode_spec {
398*4882a593Smuzhiyun unsigned int supported_bands;
399*4882a593Smuzhiyun #define SUPPORT_BAND_2GHZ 0x00000001
400*4882a593Smuzhiyun #define SUPPORT_BAND_5GHZ 0x00000002
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun unsigned int supported_rates;
403*4882a593Smuzhiyun #define SUPPORT_RATE_CCK 0x00000001
404*4882a593Smuzhiyun #define SUPPORT_RATE_OFDM 0x00000002
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun unsigned int num_channels;
407*4882a593Smuzhiyun const struct rf_channel *channels;
408*4882a593Smuzhiyun const struct channel_info *channels_info;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun struct ieee80211_sta_ht_cap ht;
411*4882a593Smuzhiyun };
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /*
414*4882a593Smuzhiyun * Configuration structure wrapper around the
415*4882a593Smuzhiyun * mac80211 configuration structure.
416*4882a593Smuzhiyun * When mac80211 configures the driver, rt2x00lib
417*4882a593Smuzhiyun * can precalculate values which are equal for all
418*4882a593Smuzhiyun * rt2x00 drivers. Those values can be stored in here.
419*4882a593Smuzhiyun */
420*4882a593Smuzhiyun struct rt2x00lib_conf {
421*4882a593Smuzhiyun struct ieee80211_conf *conf;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun struct rf_channel rf;
424*4882a593Smuzhiyun struct channel_info channel;
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /*
428*4882a593Smuzhiyun * Configuration structure for erp settings.
429*4882a593Smuzhiyun */
430*4882a593Smuzhiyun struct rt2x00lib_erp {
431*4882a593Smuzhiyun int short_preamble;
432*4882a593Smuzhiyun int cts_protection;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun u32 basic_rates;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun int slot_time;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun short sifs;
439*4882a593Smuzhiyun short pifs;
440*4882a593Smuzhiyun short difs;
441*4882a593Smuzhiyun short eifs;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun u16 beacon_int;
444*4882a593Smuzhiyun u16 ht_opmode;
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun /*
448*4882a593Smuzhiyun * Configuration structure for hardware encryption.
449*4882a593Smuzhiyun */
450*4882a593Smuzhiyun struct rt2x00lib_crypto {
451*4882a593Smuzhiyun enum cipher cipher;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun enum set_key_cmd cmd;
454*4882a593Smuzhiyun const u8 *address;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun u32 bssidx;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun u8 key[16];
459*4882a593Smuzhiyun u8 tx_mic[8];
460*4882a593Smuzhiyun u8 rx_mic[8];
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun int wcid;
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun /*
466*4882a593Smuzhiyun * Configuration structure wrapper around the
467*4882a593Smuzhiyun * rt2x00 interface configuration handler.
468*4882a593Smuzhiyun */
469*4882a593Smuzhiyun struct rt2x00intf_conf {
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun * Interface type
472*4882a593Smuzhiyun */
473*4882a593Smuzhiyun enum nl80211_iftype type;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /*
476*4882a593Smuzhiyun * TSF sync value, this is dependent on the operation type.
477*4882a593Smuzhiyun */
478*4882a593Smuzhiyun enum tsf_sync sync;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun /*
481*4882a593Smuzhiyun * The MAC and BSSID addresses are simple array of bytes,
482*4882a593Smuzhiyun * these arrays are little endian, so when sending the addresses
483*4882a593Smuzhiyun * to the drivers, copy the it into a endian-signed variable.
484*4882a593Smuzhiyun *
485*4882a593Smuzhiyun * Note that all devices (except rt2500usb) have 32 bits
486*4882a593Smuzhiyun * register word sizes. This means that whatever variable we
487*4882a593Smuzhiyun * pass _must_ be a multiple of 32 bits. Otherwise the device
488*4882a593Smuzhiyun * might not accept what we are sending to it.
489*4882a593Smuzhiyun * This will also make it easier for the driver to write
490*4882a593Smuzhiyun * the data to the device.
491*4882a593Smuzhiyun */
492*4882a593Smuzhiyun __le32 mac[2];
493*4882a593Smuzhiyun __le32 bssid[2];
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun /*
497*4882a593Smuzhiyun * Private structure for storing STA details
498*4882a593Smuzhiyun * wcid: Wireless Client ID
499*4882a593Smuzhiyun */
500*4882a593Smuzhiyun struct rt2x00_sta {
501*4882a593Smuzhiyun int wcid;
502*4882a593Smuzhiyun };
503*4882a593Smuzhiyun
sta_to_rt2x00_sta(struct ieee80211_sta * sta)504*4882a593Smuzhiyun static inline struct rt2x00_sta* sta_to_rt2x00_sta(struct ieee80211_sta *sta)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun return (struct rt2x00_sta *)sta->drv_priv;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun /*
510*4882a593Smuzhiyun * rt2x00lib callback functions.
511*4882a593Smuzhiyun */
512*4882a593Smuzhiyun struct rt2x00lib_ops {
513*4882a593Smuzhiyun /*
514*4882a593Smuzhiyun * Interrupt handlers.
515*4882a593Smuzhiyun */
516*4882a593Smuzhiyun irq_handler_t irq_handler;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun /*
519*4882a593Smuzhiyun * TX status tasklet handler.
520*4882a593Smuzhiyun */
521*4882a593Smuzhiyun void (*txstatus_tasklet) (struct tasklet_struct *t);
522*4882a593Smuzhiyun void (*pretbtt_tasklet) (struct tasklet_struct *t);
523*4882a593Smuzhiyun void (*tbtt_tasklet) (struct tasklet_struct *t);
524*4882a593Smuzhiyun void (*rxdone_tasklet) (struct tasklet_struct *t);
525*4882a593Smuzhiyun void (*autowake_tasklet) (struct tasklet_struct *t);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /*
528*4882a593Smuzhiyun * Device init handlers.
529*4882a593Smuzhiyun */
530*4882a593Smuzhiyun int (*probe_hw) (struct rt2x00_dev *rt2x00dev);
531*4882a593Smuzhiyun char *(*get_firmware_name) (struct rt2x00_dev *rt2x00dev);
532*4882a593Smuzhiyun int (*check_firmware) (struct rt2x00_dev *rt2x00dev,
533*4882a593Smuzhiyun const u8 *data, const size_t len);
534*4882a593Smuzhiyun int (*load_firmware) (struct rt2x00_dev *rt2x00dev,
535*4882a593Smuzhiyun const u8 *data, const size_t len);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun /*
538*4882a593Smuzhiyun * Device initialization/deinitialization handlers.
539*4882a593Smuzhiyun */
540*4882a593Smuzhiyun int (*initialize) (struct rt2x00_dev *rt2x00dev);
541*4882a593Smuzhiyun void (*uninitialize) (struct rt2x00_dev *rt2x00dev);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /*
544*4882a593Smuzhiyun * queue initialization handlers
545*4882a593Smuzhiyun */
546*4882a593Smuzhiyun bool (*get_entry_state) (struct queue_entry *entry);
547*4882a593Smuzhiyun void (*clear_entry) (struct queue_entry *entry);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun /*
550*4882a593Smuzhiyun * Radio control handlers.
551*4882a593Smuzhiyun */
552*4882a593Smuzhiyun int (*set_device_state) (struct rt2x00_dev *rt2x00dev,
553*4882a593Smuzhiyun enum dev_state state);
554*4882a593Smuzhiyun int (*rfkill_poll) (struct rt2x00_dev *rt2x00dev);
555*4882a593Smuzhiyun void (*link_stats) (struct rt2x00_dev *rt2x00dev,
556*4882a593Smuzhiyun struct link_qual *qual);
557*4882a593Smuzhiyun void (*reset_tuner) (struct rt2x00_dev *rt2x00dev,
558*4882a593Smuzhiyun struct link_qual *qual);
559*4882a593Smuzhiyun void (*link_tuner) (struct rt2x00_dev *rt2x00dev,
560*4882a593Smuzhiyun struct link_qual *qual, const u32 count);
561*4882a593Smuzhiyun void (*gain_calibration) (struct rt2x00_dev *rt2x00dev);
562*4882a593Smuzhiyun void (*vco_calibration) (struct rt2x00_dev *rt2x00dev);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /*
565*4882a593Smuzhiyun * Data queue handlers.
566*4882a593Smuzhiyun */
567*4882a593Smuzhiyun void (*watchdog) (struct rt2x00_dev *rt2x00dev);
568*4882a593Smuzhiyun void (*start_queue) (struct data_queue *queue);
569*4882a593Smuzhiyun void (*kick_queue) (struct data_queue *queue);
570*4882a593Smuzhiyun void (*stop_queue) (struct data_queue *queue);
571*4882a593Smuzhiyun void (*flush_queue) (struct data_queue *queue, bool drop);
572*4882a593Smuzhiyun void (*tx_dma_done) (struct queue_entry *entry);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun /*
575*4882a593Smuzhiyun * TX control handlers
576*4882a593Smuzhiyun */
577*4882a593Smuzhiyun void (*write_tx_desc) (struct queue_entry *entry,
578*4882a593Smuzhiyun struct txentry_desc *txdesc);
579*4882a593Smuzhiyun void (*write_tx_data) (struct queue_entry *entry,
580*4882a593Smuzhiyun struct txentry_desc *txdesc);
581*4882a593Smuzhiyun void (*write_beacon) (struct queue_entry *entry,
582*4882a593Smuzhiyun struct txentry_desc *txdesc);
583*4882a593Smuzhiyun void (*clear_beacon) (struct queue_entry *entry);
584*4882a593Smuzhiyun int (*get_tx_data_len) (struct queue_entry *entry);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun /*
587*4882a593Smuzhiyun * RX control handlers
588*4882a593Smuzhiyun */
589*4882a593Smuzhiyun void (*fill_rxdone) (struct queue_entry *entry,
590*4882a593Smuzhiyun struct rxdone_entry_desc *rxdesc);
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun /*
593*4882a593Smuzhiyun * Configuration handlers.
594*4882a593Smuzhiyun */
595*4882a593Smuzhiyun int (*config_shared_key) (struct rt2x00_dev *rt2x00dev,
596*4882a593Smuzhiyun struct rt2x00lib_crypto *crypto,
597*4882a593Smuzhiyun struct ieee80211_key_conf *key);
598*4882a593Smuzhiyun int (*config_pairwise_key) (struct rt2x00_dev *rt2x00dev,
599*4882a593Smuzhiyun struct rt2x00lib_crypto *crypto,
600*4882a593Smuzhiyun struct ieee80211_key_conf *key);
601*4882a593Smuzhiyun void (*config_filter) (struct rt2x00_dev *rt2x00dev,
602*4882a593Smuzhiyun const unsigned int filter_flags);
603*4882a593Smuzhiyun void (*config_intf) (struct rt2x00_dev *rt2x00dev,
604*4882a593Smuzhiyun struct rt2x00_intf *intf,
605*4882a593Smuzhiyun struct rt2x00intf_conf *conf,
606*4882a593Smuzhiyun const unsigned int flags);
607*4882a593Smuzhiyun #define CONFIG_UPDATE_TYPE ( 1 << 1 )
608*4882a593Smuzhiyun #define CONFIG_UPDATE_MAC ( 1 << 2 )
609*4882a593Smuzhiyun #define CONFIG_UPDATE_BSSID ( 1 << 3 )
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun void (*config_erp) (struct rt2x00_dev *rt2x00dev,
612*4882a593Smuzhiyun struct rt2x00lib_erp *erp,
613*4882a593Smuzhiyun u32 changed);
614*4882a593Smuzhiyun void (*config_ant) (struct rt2x00_dev *rt2x00dev,
615*4882a593Smuzhiyun struct antenna_setup *ant);
616*4882a593Smuzhiyun void (*config) (struct rt2x00_dev *rt2x00dev,
617*4882a593Smuzhiyun struct rt2x00lib_conf *libconf,
618*4882a593Smuzhiyun const unsigned int changed_flags);
619*4882a593Smuzhiyun void (*pre_reset_hw) (struct rt2x00_dev *rt2x00dev);
620*4882a593Smuzhiyun int (*sta_add) (struct rt2x00_dev *rt2x00dev,
621*4882a593Smuzhiyun struct ieee80211_vif *vif,
622*4882a593Smuzhiyun struct ieee80211_sta *sta);
623*4882a593Smuzhiyun int (*sta_remove) (struct rt2x00_dev *rt2x00dev,
624*4882a593Smuzhiyun struct ieee80211_sta *sta);
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun /*
628*4882a593Smuzhiyun * rt2x00 driver callback operation structure.
629*4882a593Smuzhiyun */
630*4882a593Smuzhiyun struct rt2x00_ops {
631*4882a593Smuzhiyun const char *name;
632*4882a593Smuzhiyun const unsigned int drv_data_size;
633*4882a593Smuzhiyun const unsigned int max_ap_intf;
634*4882a593Smuzhiyun const unsigned int eeprom_size;
635*4882a593Smuzhiyun const unsigned int rf_size;
636*4882a593Smuzhiyun const unsigned int tx_queues;
637*4882a593Smuzhiyun void (*queue_init)(struct data_queue *queue);
638*4882a593Smuzhiyun const struct rt2x00lib_ops *lib;
639*4882a593Smuzhiyun const void *drv;
640*4882a593Smuzhiyun const struct ieee80211_ops *hw;
641*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_LIB_DEBUGFS
642*4882a593Smuzhiyun const struct rt2x00debug *debugfs;
643*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun /*
647*4882a593Smuzhiyun * rt2x00 state flags
648*4882a593Smuzhiyun */
649*4882a593Smuzhiyun enum rt2x00_state_flags {
650*4882a593Smuzhiyun /*
651*4882a593Smuzhiyun * Device flags
652*4882a593Smuzhiyun */
653*4882a593Smuzhiyun DEVICE_STATE_PRESENT,
654*4882a593Smuzhiyun DEVICE_STATE_REGISTERED_HW,
655*4882a593Smuzhiyun DEVICE_STATE_INITIALIZED,
656*4882a593Smuzhiyun DEVICE_STATE_STARTED,
657*4882a593Smuzhiyun DEVICE_STATE_ENABLED_RADIO,
658*4882a593Smuzhiyun DEVICE_STATE_SCANNING,
659*4882a593Smuzhiyun DEVICE_STATE_FLUSHING,
660*4882a593Smuzhiyun DEVICE_STATE_RESET,
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun /*
663*4882a593Smuzhiyun * Driver configuration
664*4882a593Smuzhiyun */
665*4882a593Smuzhiyun CONFIG_CHANNEL_HT40,
666*4882a593Smuzhiyun CONFIG_POWERSAVING,
667*4882a593Smuzhiyun CONFIG_HT_DISABLED,
668*4882a593Smuzhiyun CONFIG_MONITORING,
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun /*
671*4882a593Smuzhiyun * Mark we currently are sequentially reading TX_STA_FIFO register
672*4882a593Smuzhiyun * FIXME: this is for only rt2800usb, should go to private data
673*4882a593Smuzhiyun */
674*4882a593Smuzhiyun TX_STATUS_READING,
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun /*
678*4882a593Smuzhiyun * rt2x00 capability flags
679*4882a593Smuzhiyun */
680*4882a593Smuzhiyun enum rt2x00_capability_flags {
681*4882a593Smuzhiyun /*
682*4882a593Smuzhiyun * Requirements
683*4882a593Smuzhiyun */
684*4882a593Smuzhiyun REQUIRE_FIRMWARE,
685*4882a593Smuzhiyun REQUIRE_BEACON_GUARD,
686*4882a593Smuzhiyun REQUIRE_ATIM_QUEUE,
687*4882a593Smuzhiyun REQUIRE_DMA,
688*4882a593Smuzhiyun REQUIRE_COPY_IV,
689*4882a593Smuzhiyun REQUIRE_L2PAD,
690*4882a593Smuzhiyun REQUIRE_TXSTATUS_FIFO,
691*4882a593Smuzhiyun REQUIRE_TASKLET_CONTEXT,
692*4882a593Smuzhiyun REQUIRE_SW_SEQNO,
693*4882a593Smuzhiyun REQUIRE_HT_TX_DESC,
694*4882a593Smuzhiyun REQUIRE_PS_AUTOWAKE,
695*4882a593Smuzhiyun REQUIRE_DELAYED_RFKILL,
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun /*
698*4882a593Smuzhiyun * Capabilities
699*4882a593Smuzhiyun */
700*4882a593Smuzhiyun CAPABILITY_HW_BUTTON,
701*4882a593Smuzhiyun CAPABILITY_HW_CRYPTO,
702*4882a593Smuzhiyun CAPABILITY_POWER_LIMIT,
703*4882a593Smuzhiyun CAPABILITY_CONTROL_FILTERS,
704*4882a593Smuzhiyun CAPABILITY_CONTROL_FILTER_PSPOLL,
705*4882a593Smuzhiyun CAPABILITY_PRE_TBTT_INTERRUPT,
706*4882a593Smuzhiyun CAPABILITY_LINK_TUNING,
707*4882a593Smuzhiyun CAPABILITY_FRAME_TYPE,
708*4882a593Smuzhiyun CAPABILITY_RF_SEQUENCE,
709*4882a593Smuzhiyun CAPABILITY_EXTERNAL_LNA_A,
710*4882a593Smuzhiyun CAPABILITY_EXTERNAL_LNA_BG,
711*4882a593Smuzhiyun CAPABILITY_DOUBLE_ANTENNA,
712*4882a593Smuzhiyun CAPABILITY_BT_COEXIST,
713*4882a593Smuzhiyun CAPABILITY_VCO_RECALIBRATION,
714*4882a593Smuzhiyun CAPABILITY_EXTERNAL_PA_TX0,
715*4882a593Smuzhiyun CAPABILITY_EXTERNAL_PA_TX1,
716*4882a593Smuzhiyun CAPABILITY_RESTART_HW,
717*4882a593Smuzhiyun };
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun /*
720*4882a593Smuzhiyun * Interface combinations
721*4882a593Smuzhiyun */
722*4882a593Smuzhiyun enum {
723*4882a593Smuzhiyun IF_COMB_AP = 0,
724*4882a593Smuzhiyun NUM_IF_COMB,
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun /*
728*4882a593Smuzhiyun * rt2x00 device structure.
729*4882a593Smuzhiyun */
730*4882a593Smuzhiyun struct rt2x00_dev {
731*4882a593Smuzhiyun /*
732*4882a593Smuzhiyun * Device structure.
733*4882a593Smuzhiyun * The structure stored in here depends on the
734*4882a593Smuzhiyun * system bus (PCI or USB).
735*4882a593Smuzhiyun * When accessing this variable, the rt2x00dev_{pci,usb}
736*4882a593Smuzhiyun * macros should be used for correct typecasting.
737*4882a593Smuzhiyun */
738*4882a593Smuzhiyun struct device *dev;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun /*
741*4882a593Smuzhiyun * Callback functions.
742*4882a593Smuzhiyun */
743*4882a593Smuzhiyun const struct rt2x00_ops *ops;
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun /*
746*4882a593Smuzhiyun * Driver data.
747*4882a593Smuzhiyun */
748*4882a593Smuzhiyun void *drv_data;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun /*
751*4882a593Smuzhiyun * IEEE80211 control structure.
752*4882a593Smuzhiyun */
753*4882a593Smuzhiyun struct ieee80211_hw *hw;
754*4882a593Smuzhiyun struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
755*4882a593Smuzhiyun enum nl80211_band curr_band;
756*4882a593Smuzhiyun int curr_freq;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun /*
759*4882a593Smuzhiyun * If enabled, the debugfs interface structures
760*4882a593Smuzhiyun * required for deregistration of debugfs.
761*4882a593Smuzhiyun */
762*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_LIB_DEBUGFS
763*4882a593Smuzhiyun struct rt2x00debug_intf *debugfs_intf;
764*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun /*
767*4882a593Smuzhiyun * LED structure for changing the LED status
768*4882a593Smuzhiyun * by mac8011 or the kernel.
769*4882a593Smuzhiyun */
770*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_LIB_LEDS
771*4882a593Smuzhiyun struct rt2x00_led led_radio;
772*4882a593Smuzhiyun struct rt2x00_led led_assoc;
773*4882a593Smuzhiyun struct rt2x00_led led_qual;
774*4882a593Smuzhiyun u16 led_mcu_reg;
775*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_LIB_LEDS */
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun /*
778*4882a593Smuzhiyun * Device state flags.
779*4882a593Smuzhiyun * In these flags the current status is stored.
780*4882a593Smuzhiyun * Access to these flags should occur atomically.
781*4882a593Smuzhiyun */
782*4882a593Smuzhiyun unsigned long flags;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun /*
785*4882a593Smuzhiyun * Device capabiltiy flags.
786*4882a593Smuzhiyun * In these flags the device/driver capabilities are stored.
787*4882a593Smuzhiyun * Access to these flags should occur non-atomically.
788*4882a593Smuzhiyun */
789*4882a593Smuzhiyun unsigned long cap_flags;
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun /*
792*4882a593Smuzhiyun * Device information, Bus IRQ and name (PCI, SoC)
793*4882a593Smuzhiyun */
794*4882a593Smuzhiyun int irq;
795*4882a593Smuzhiyun const char *name;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun /*
798*4882a593Smuzhiyun * Chipset identification.
799*4882a593Smuzhiyun */
800*4882a593Smuzhiyun struct rt2x00_chip chip;
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun /*
803*4882a593Smuzhiyun * hw capability specifications.
804*4882a593Smuzhiyun */
805*4882a593Smuzhiyun struct hw_mode_spec spec;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun /*
808*4882a593Smuzhiyun * This is the default TX/RX antenna setup as indicated
809*4882a593Smuzhiyun * by the device's EEPROM.
810*4882a593Smuzhiyun */
811*4882a593Smuzhiyun struct antenna_setup default_ant;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun /*
814*4882a593Smuzhiyun * Register pointers
815*4882a593Smuzhiyun * csr.base: CSR base register address. (PCI)
816*4882a593Smuzhiyun * csr.cache: CSR cache for usb_control_msg. (USB)
817*4882a593Smuzhiyun */
818*4882a593Smuzhiyun union csr {
819*4882a593Smuzhiyun void __iomem *base;
820*4882a593Smuzhiyun void *cache;
821*4882a593Smuzhiyun } csr;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun /*
824*4882a593Smuzhiyun * Mutex to protect register accesses.
825*4882a593Smuzhiyun * For PCI and USB devices it protects against concurrent indirect
826*4882a593Smuzhiyun * register access (BBP, RF, MCU) since accessing those
827*4882a593Smuzhiyun * registers require multiple calls to the CSR registers.
828*4882a593Smuzhiyun * For USB devices it also protects the csr_cache since that
829*4882a593Smuzhiyun * field is used for normal CSR access and it cannot support
830*4882a593Smuzhiyun * multiple callers simultaneously.
831*4882a593Smuzhiyun */
832*4882a593Smuzhiyun struct mutex csr_mutex;
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun /*
835*4882a593Smuzhiyun * Mutex to synchronize config and link tuner.
836*4882a593Smuzhiyun */
837*4882a593Smuzhiyun struct mutex conf_mutex;
838*4882a593Smuzhiyun /*
839*4882a593Smuzhiyun * Current packet filter configuration for the device.
840*4882a593Smuzhiyun * This contains all currently active FIF_* flags send
841*4882a593Smuzhiyun * to us by mac80211 during configure_filter().
842*4882a593Smuzhiyun */
843*4882a593Smuzhiyun unsigned int packet_filter;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun /*
846*4882a593Smuzhiyun * Interface details:
847*4882a593Smuzhiyun * - Open ap interface count.
848*4882a593Smuzhiyun * - Open sta interface count.
849*4882a593Smuzhiyun * - Association count.
850*4882a593Smuzhiyun * - Beaconing enabled count.
851*4882a593Smuzhiyun */
852*4882a593Smuzhiyun unsigned int intf_ap_count;
853*4882a593Smuzhiyun unsigned int intf_sta_count;
854*4882a593Smuzhiyun unsigned int intf_associated;
855*4882a593Smuzhiyun unsigned int intf_beaconing;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun /*
858*4882a593Smuzhiyun * Interface combinations
859*4882a593Smuzhiyun */
860*4882a593Smuzhiyun struct ieee80211_iface_limit if_limits_ap;
861*4882a593Smuzhiyun struct ieee80211_iface_combination if_combinations[NUM_IF_COMB];
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /*
864*4882a593Smuzhiyun * Link quality
865*4882a593Smuzhiyun */
866*4882a593Smuzhiyun struct link link;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun /*
869*4882a593Smuzhiyun * EEPROM data.
870*4882a593Smuzhiyun */
871*4882a593Smuzhiyun __le16 *eeprom;
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun /*
874*4882a593Smuzhiyun * Active RF register values.
875*4882a593Smuzhiyun * These are stored here so we don't need
876*4882a593Smuzhiyun * to read the rf registers and can directly
877*4882a593Smuzhiyun * use this value instead.
878*4882a593Smuzhiyun * This field should be accessed by using
879*4882a593Smuzhiyun * rt2x00_rf_read() and rt2x00_rf_write().
880*4882a593Smuzhiyun */
881*4882a593Smuzhiyun u32 *rf;
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun /*
884*4882a593Smuzhiyun * LNA gain
885*4882a593Smuzhiyun */
886*4882a593Smuzhiyun short lna_gain;
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun /*
889*4882a593Smuzhiyun * Current TX power value.
890*4882a593Smuzhiyun */
891*4882a593Smuzhiyun u16 tx_power;
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun /*
894*4882a593Smuzhiyun * Current retry values.
895*4882a593Smuzhiyun */
896*4882a593Smuzhiyun u8 short_retry;
897*4882a593Smuzhiyun u8 long_retry;
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun /*
900*4882a593Smuzhiyun * Rssi <-> Dbm offset
901*4882a593Smuzhiyun */
902*4882a593Smuzhiyun u8 rssi_offset;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun /*
905*4882a593Smuzhiyun * Frequency offset.
906*4882a593Smuzhiyun */
907*4882a593Smuzhiyun u8 freq_offset;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun /*
910*4882a593Smuzhiyun * Association id.
911*4882a593Smuzhiyun */
912*4882a593Smuzhiyun u16 aid;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun /*
915*4882a593Smuzhiyun * Beacon interval.
916*4882a593Smuzhiyun */
917*4882a593Smuzhiyun u16 beacon_int;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun /**
920*4882a593Smuzhiyun * Timestamp of last received beacon
921*4882a593Smuzhiyun */
922*4882a593Smuzhiyun unsigned long last_beacon;
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun /*
925*4882a593Smuzhiyun * Low level statistics which will have
926*4882a593Smuzhiyun * to be kept up to date while device is running.
927*4882a593Smuzhiyun */
928*4882a593Smuzhiyun struct ieee80211_low_level_stats low_level_stats;
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun /**
931*4882a593Smuzhiyun * Work queue for all work which should not be placed
932*4882a593Smuzhiyun * on the mac80211 workqueue (because of dependencies
933*4882a593Smuzhiyun * between various work structures).
934*4882a593Smuzhiyun */
935*4882a593Smuzhiyun struct workqueue_struct *workqueue;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun /*
938*4882a593Smuzhiyun * Scheduled work.
939*4882a593Smuzhiyun * NOTE: intf_work will use ieee80211_iterate_active_interfaces()
940*4882a593Smuzhiyun * which means it cannot be placed on the hw->workqueue
941*4882a593Smuzhiyun * due to RTNL locking requirements.
942*4882a593Smuzhiyun */
943*4882a593Smuzhiyun struct work_struct intf_work;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun /**
946*4882a593Smuzhiyun * Scheduled work for TX/RX done handling (USB devices)
947*4882a593Smuzhiyun */
948*4882a593Smuzhiyun struct work_struct rxdone_work;
949*4882a593Smuzhiyun struct work_struct txdone_work;
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun /*
952*4882a593Smuzhiyun * Powersaving work
953*4882a593Smuzhiyun */
954*4882a593Smuzhiyun struct delayed_work autowakeup_work;
955*4882a593Smuzhiyun struct work_struct sleep_work;
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun /*
958*4882a593Smuzhiyun * Data queue arrays for RX, TX, Beacon and ATIM.
959*4882a593Smuzhiyun */
960*4882a593Smuzhiyun unsigned int data_queues;
961*4882a593Smuzhiyun struct data_queue *rx;
962*4882a593Smuzhiyun struct data_queue *tx;
963*4882a593Smuzhiyun struct data_queue *bcn;
964*4882a593Smuzhiyun struct data_queue *atim;
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun /*
967*4882a593Smuzhiyun * Firmware image.
968*4882a593Smuzhiyun */
969*4882a593Smuzhiyun const struct firmware *fw;
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun /*
972*4882a593Smuzhiyun * FIFO for storing tx status reports between isr and tasklet.
973*4882a593Smuzhiyun */
974*4882a593Smuzhiyun DECLARE_KFIFO_PTR(txstatus_fifo, u32);
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun /*
977*4882a593Smuzhiyun * Timer to ensure tx status reports are read (rt2800usb).
978*4882a593Smuzhiyun */
979*4882a593Smuzhiyun struct hrtimer txstatus_timer;
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun /*
982*4882a593Smuzhiyun * Tasklet for processing tx status reports (rt2800pci).
983*4882a593Smuzhiyun */
984*4882a593Smuzhiyun struct tasklet_struct txstatus_tasklet;
985*4882a593Smuzhiyun struct tasklet_struct pretbtt_tasklet;
986*4882a593Smuzhiyun struct tasklet_struct tbtt_tasklet;
987*4882a593Smuzhiyun struct tasklet_struct rxdone_tasklet;
988*4882a593Smuzhiyun struct tasklet_struct autowake_tasklet;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun /*
991*4882a593Smuzhiyun * Used for VCO periodic calibration.
992*4882a593Smuzhiyun */
993*4882a593Smuzhiyun int rf_channel;
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun /*
996*4882a593Smuzhiyun * Protect the interrupt mask register.
997*4882a593Smuzhiyun */
998*4882a593Smuzhiyun spinlock_t irqmask_lock;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun /*
1001*4882a593Smuzhiyun * List of BlockAckReq TX entries that need driver BlockAck processing.
1002*4882a593Smuzhiyun */
1003*4882a593Smuzhiyun struct list_head bar_list;
1004*4882a593Smuzhiyun spinlock_t bar_list_lock;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun /* Extra TX headroom required for alignment purposes. */
1007*4882a593Smuzhiyun unsigned int extra_tx_headroom;
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun struct usb_anchor *anchor;
1010*4882a593Smuzhiyun unsigned int num_proto_errs;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun /* Clock for System On Chip devices. */
1013*4882a593Smuzhiyun struct clk *clk;
1014*4882a593Smuzhiyun };
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun struct rt2x00_bar_list_entry {
1017*4882a593Smuzhiyun struct list_head list;
1018*4882a593Smuzhiyun struct rcu_head head;
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun struct queue_entry *entry;
1021*4882a593Smuzhiyun int block_acked;
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun /* Relevant parts of the IEEE80211 BAR header */
1024*4882a593Smuzhiyun __u8 ra[6];
1025*4882a593Smuzhiyun __u8 ta[6];
1026*4882a593Smuzhiyun __le16 control;
1027*4882a593Smuzhiyun __le16 start_seq_num;
1028*4882a593Smuzhiyun };
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun /*
1031*4882a593Smuzhiyun * Register defines.
1032*4882a593Smuzhiyun * Some registers require multiple attempts before success,
1033*4882a593Smuzhiyun * in those cases REGISTER_BUSY_COUNT attempts should be
1034*4882a593Smuzhiyun * taken with a REGISTER_BUSY_DELAY interval. Due to USB
1035*4882a593Smuzhiyun * bus delays, we do not have to loop so many times to wait
1036*4882a593Smuzhiyun * for valid register value on that bus.
1037*4882a593Smuzhiyun */
1038*4882a593Smuzhiyun #define REGISTER_BUSY_COUNT 100
1039*4882a593Smuzhiyun #define REGISTER_USB_BUSY_COUNT 20
1040*4882a593Smuzhiyun #define REGISTER_BUSY_DELAY 100
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun /*
1043*4882a593Smuzhiyun * Generic RF access.
1044*4882a593Smuzhiyun * The RF is being accessed by word index.
1045*4882a593Smuzhiyun */
rt2x00_rf_read(struct rt2x00_dev * rt2x00dev,const unsigned int word)1046*4882a593Smuzhiyun static inline u32 rt2x00_rf_read(struct rt2x00_dev *rt2x00dev,
1047*4882a593Smuzhiyun const unsigned int word)
1048*4882a593Smuzhiyun {
1049*4882a593Smuzhiyun BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32));
1050*4882a593Smuzhiyun return rt2x00dev->rf[word - 1];
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
rt2x00_rf_write(struct rt2x00_dev * rt2x00dev,const unsigned int word,u32 data)1053*4882a593Smuzhiyun static inline void rt2x00_rf_write(struct rt2x00_dev *rt2x00dev,
1054*4882a593Smuzhiyun const unsigned int word, u32 data)
1055*4882a593Smuzhiyun {
1056*4882a593Smuzhiyun BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32));
1057*4882a593Smuzhiyun rt2x00dev->rf[word - 1] = data;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun /*
1061*4882a593Smuzhiyun * Generic EEPROM access. The EEPROM is being accessed by word or byte index.
1062*4882a593Smuzhiyun */
rt2x00_eeprom_addr(struct rt2x00_dev * rt2x00dev,const unsigned int word)1063*4882a593Smuzhiyun static inline void *rt2x00_eeprom_addr(struct rt2x00_dev *rt2x00dev,
1064*4882a593Smuzhiyun const unsigned int word)
1065*4882a593Smuzhiyun {
1066*4882a593Smuzhiyun return (void *)&rt2x00dev->eeprom[word];
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun
rt2x00_eeprom_read(struct rt2x00_dev * rt2x00dev,const unsigned int word)1069*4882a593Smuzhiyun static inline u16 rt2x00_eeprom_read(struct rt2x00_dev *rt2x00dev,
1070*4882a593Smuzhiyun const unsigned int word)
1071*4882a593Smuzhiyun {
1072*4882a593Smuzhiyun return le16_to_cpu(rt2x00dev->eeprom[word]);
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun
rt2x00_eeprom_write(struct rt2x00_dev * rt2x00dev,const unsigned int word,u16 data)1075*4882a593Smuzhiyun static inline void rt2x00_eeprom_write(struct rt2x00_dev *rt2x00dev,
1076*4882a593Smuzhiyun const unsigned int word, u16 data)
1077*4882a593Smuzhiyun {
1078*4882a593Smuzhiyun rt2x00dev->eeprom[word] = cpu_to_le16(data);
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun
rt2x00_eeprom_byte(struct rt2x00_dev * rt2x00dev,const unsigned int byte)1081*4882a593Smuzhiyun static inline u8 rt2x00_eeprom_byte(struct rt2x00_dev *rt2x00dev,
1082*4882a593Smuzhiyun const unsigned int byte)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun return *(((u8 *)rt2x00dev->eeprom) + byte);
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun /*
1088*4882a593Smuzhiyun * Chipset handlers
1089*4882a593Smuzhiyun */
rt2x00_set_chip(struct rt2x00_dev * rt2x00dev,const u16 rt,const u16 rf,const u16 rev)1090*4882a593Smuzhiyun static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
1091*4882a593Smuzhiyun const u16 rt, const u16 rf, const u16 rev)
1092*4882a593Smuzhiyun {
1093*4882a593Smuzhiyun rt2x00dev->chip.rt = rt;
1094*4882a593Smuzhiyun rt2x00dev->chip.rf = rf;
1095*4882a593Smuzhiyun rt2x00dev->chip.rev = rev;
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun rt2x00_info(rt2x00dev, "Chipset detected - rt: %04x, rf: %04x, rev: %04x\n",
1098*4882a593Smuzhiyun rt2x00dev->chip.rt, rt2x00dev->chip.rf,
1099*4882a593Smuzhiyun rt2x00dev->chip.rev);
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun
rt2x00_set_rt(struct rt2x00_dev * rt2x00dev,const u16 rt,const u16 rev)1102*4882a593Smuzhiyun static inline void rt2x00_set_rt(struct rt2x00_dev *rt2x00dev,
1103*4882a593Smuzhiyun const u16 rt, const u16 rev)
1104*4882a593Smuzhiyun {
1105*4882a593Smuzhiyun rt2x00dev->chip.rt = rt;
1106*4882a593Smuzhiyun rt2x00dev->chip.rev = rev;
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun rt2x00_info(rt2x00dev, "RT chipset %04x, rev %04x detected\n",
1109*4882a593Smuzhiyun rt2x00dev->chip.rt, rt2x00dev->chip.rev);
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun
rt2x00_set_rf(struct rt2x00_dev * rt2x00dev,const u16 rf)1112*4882a593Smuzhiyun static inline void rt2x00_set_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
1113*4882a593Smuzhiyun {
1114*4882a593Smuzhiyun rt2x00dev->chip.rf = rf;
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun rt2x00_info(rt2x00dev, "RF chipset %04x detected\n",
1117*4882a593Smuzhiyun rt2x00dev->chip.rf);
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun
rt2x00_rt(struct rt2x00_dev * rt2x00dev,const u16 rt)1120*4882a593Smuzhiyun static inline bool rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun return (rt2x00dev->chip.rt == rt);
1123*4882a593Smuzhiyun }
1124*4882a593Smuzhiyun
rt2x00_rf(struct rt2x00_dev * rt2x00dev,const u16 rf)1125*4882a593Smuzhiyun static inline bool rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
1126*4882a593Smuzhiyun {
1127*4882a593Smuzhiyun return (rt2x00dev->chip.rf == rf);
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun
rt2x00_rev(struct rt2x00_dev * rt2x00dev)1130*4882a593Smuzhiyun static inline u16 rt2x00_rev(struct rt2x00_dev *rt2x00dev)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun return rt2x00dev->chip.rev;
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun
rt2x00_rt_rev(struct rt2x00_dev * rt2x00dev,const u16 rt,const u16 rev)1135*4882a593Smuzhiyun static inline bool rt2x00_rt_rev(struct rt2x00_dev *rt2x00dev,
1136*4882a593Smuzhiyun const u16 rt, const u16 rev)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) == rev);
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun
rt2x00_rt_rev_lt(struct rt2x00_dev * rt2x00dev,const u16 rt,const u16 rev)1141*4882a593Smuzhiyun static inline bool rt2x00_rt_rev_lt(struct rt2x00_dev *rt2x00dev,
1142*4882a593Smuzhiyun const u16 rt, const u16 rev)
1143*4882a593Smuzhiyun {
1144*4882a593Smuzhiyun return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) < rev);
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun
rt2x00_rt_rev_gte(struct rt2x00_dev * rt2x00dev,const u16 rt,const u16 rev)1147*4882a593Smuzhiyun static inline bool rt2x00_rt_rev_gte(struct rt2x00_dev *rt2x00dev,
1148*4882a593Smuzhiyun const u16 rt, const u16 rev)
1149*4882a593Smuzhiyun {
1150*4882a593Smuzhiyun return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) >= rev);
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun
rt2x00_set_chip_intf(struct rt2x00_dev * rt2x00dev,enum rt2x00_chip_intf intf)1153*4882a593Smuzhiyun static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
1154*4882a593Smuzhiyun enum rt2x00_chip_intf intf)
1155*4882a593Smuzhiyun {
1156*4882a593Smuzhiyun rt2x00dev->chip.intf = intf;
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun
rt2x00_intf(struct rt2x00_dev * rt2x00dev,enum rt2x00_chip_intf intf)1159*4882a593Smuzhiyun static inline bool rt2x00_intf(struct rt2x00_dev *rt2x00dev,
1160*4882a593Smuzhiyun enum rt2x00_chip_intf intf)
1161*4882a593Smuzhiyun {
1162*4882a593Smuzhiyun return (rt2x00dev->chip.intf == intf);
1163*4882a593Smuzhiyun }
1164*4882a593Smuzhiyun
rt2x00_is_pci(struct rt2x00_dev * rt2x00dev)1165*4882a593Smuzhiyun static inline bool rt2x00_is_pci(struct rt2x00_dev *rt2x00dev)
1166*4882a593Smuzhiyun {
1167*4882a593Smuzhiyun return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI) ||
1168*4882a593Smuzhiyun rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
1169*4882a593Smuzhiyun }
1170*4882a593Smuzhiyun
rt2x00_is_pcie(struct rt2x00_dev * rt2x00dev)1171*4882a593Smuzhiyun static inline bool rt2x00_is_pcie(struct rt2x00_dev *rt2x00dev)
1172*4882a593Smuzhiyun {
1173*4882a593Smuzhiyun return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
1174*4882a593Smuzhiyun }
1175*4882a593Smuzhiyun
rt2x00_is_usb(struct rt2x00_dev * rt2x00dev)1176*4882a593Smuzhiyun static inline bool rt2x00_is_usb(struct rt2x00_dev *rt2x00dev)
1177*4882a593Smuzhiyun {
1178*4882a593Smuzhiyun return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
1179*4882a593Smuzhiyun }
1180*4882a593Smuzhiyun
rt2x00_is_soc(struct rt2x00_dev * rt2x00dev)1181*4882a593Smuzhiyun static inline bool rt2x00_is_soc(struct rt2x00_dev *rt2x00dev)
1182*4882a593Smuzhiyun {
1183*4882a593Smuzhiyun return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC);
1184*4882a593Smuzhiyun }
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun /* Helpers for capability flags */
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_flag(struct rt2x00_dev * rt2x00dev,enum rt2x00_capability_flags cap_flag)1189*4882a593Smuzhiyun rt2x00_has_cap_flag(struct rt2x00_dev *rt2x00dev,
1190*4882a593Smuzhiyun enum rt2x00_capability_flags cap_flag)
1191*4882a593Smuzhiyun {
1192*4882a593Smuzhiyun return test_bit(cap_flag, &rt2x00dev->cap_flags);
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_hw_crypto(struct rt2x00_dev * rt2x00dev)1196*4882a593Smuzhiyun rt2x00_has_cap_hw_crypto(struct rt2x00_dev *rt2x00dev)
1197*4882a593Smuzhiyun {
1198*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_HW_CRYPTO);
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_power_limit(struct rt2x00_dev * rt2x00dev)1202*4882a593Smuzhiyun rt2x00_has_cap_power_limit(struct rt2x00_dev *rt2x00dev)
1203*4882a593Smuzhiyun {
1204*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_POWER_LIMIT);
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_control_filters(struct rt2x00_dev * rt2x00dev)1208*4882a593Smuzhiyun rt2x00_has_cap_control_filters(struct rt2x00_dev *rt2x00dev)
1209*4882a593Smuzhiyun {
1210*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_CONTROL_FILTERS);
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_control_filter_pspoll(struct rt2x00_dev * rt2x00dev)1214*4882a593Smuzhiyun rt2x00_has_cap_control_filter_pspoll(struct rt2x00_dev *rt2x00dev)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_CONTROL_FILTER_PSPOLL);
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_pre_tbtt_interrupt(struct rt2x00_dev * rt2x00dev)1220*4882a593Smuzhiyun rt2x00_has_cap_pre_tbtt_interrupt(struct rt2x00_dev *rt2x00dev)
1221*4882a593Smuzhiyun {
1222*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_PRE_TBTT_INTERRUPT);
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_link_tuning(struct rt2x00_dev * rt2x00dev)1226*4882a593Smuzhiyun rt2x00_has_cap_link_tuning(struct rt2x00_dev *rt2x00dev)
1227*4882a593Smuzhiyun {
1228*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_LINK_TUNING);
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_frame_type(struct rt2x00_dev * rt2x00dev)1232*4882a593Smuzhiyun rt2x00_has_cap_frame_type(struct rt2x00_dev *rt2x00dev)
1233*4882a593Smuzhiyun {
1234*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_FRAME_TYPE);
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_rf_sequence(struct rt2x00_dev * rt2x00dev)1238*4882a593Smuzhiyun rt2x00_has_cap_rf_sequence(struct rt2x00_dev *rt2x00dev)
1239*4882a593Smuzhiyun {
1240*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_RF_SEQUENCE);
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_external_lna_a(struct rt2x00_dev * rt2x00dev)1244*4882a593Smuzhiyun rt2x00_has_cap_external_lna_a(struct rt2x00_dev *rt2x00dev)
1245*4882a593Smuzhiyun {
1246*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_A);
1247*4882a593Smuzhiyun }
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_external_lna_bg(struct rt2x00_dev * rt2x00dev)1250*4882a593Smuzhiyun rt2x00_has_cap_external_lna_bg(struct rt2x00_dev *rt2x00dev)
1251*4882a593Smuzhiyun {
1252*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_BG);
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_double_antenna(struct rt2x00_dev * rt2x00dev)1256*4882a593Smuzhiyun rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA);
1259*4882a593Smuzhiyun }
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_bt_coexist(struct rt2x00_dev * rt2x00dev)1262*4882a593Smuzhiyun rt2x00_has_cap_bt_coexist(struct rt2x00_dev *rt2x00dev)
1263*4882a593Smuzhiyun {
1264*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_BT_COEXIST);
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_vco_recalibration(struct rt2x00_dev * rt2x00dev)1268*4882a593Smuzhiyun rt2x00_has_cap_vco_recalibration(struct rt2x00_dev *rt2x00dev)
1269*4882a593Smuzhiyun {
1270*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_VCO_RECALIBRATION);
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun static inline bool
rt2x00_has_cap_restart_hw(struct rt2x00_dev * rt2x00dev)1274*4882a593Smuzhiyun rt2x00_has_cap_restart_hw(struct rt2x00_dev *rt2x00dev)
1275*4882a593Smuzhiyun {
1276*4882a593Smuzhiyun return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_RESTART_HW);
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun /**
1280*4882a593Smuzhiyun * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes.
1281*4882a593Smuzhiyun * @entry: Pointer to &struct queue_entry
1282*4882a593Smuzhiyun *
1283*4882a593Smuzhiyun * Returns -ENOMEM if mapping fail, 0 otherwise.
1284*4882a593Smuzhiyun */
1285*4882a593Smuzhiyun int rt2x00queue_map_txskb(struct queue_entry *entry);
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun /**
1288*4882a593Smuzhiyun * rt2x00queue_unmap_skb - Unmap a skb from DMA.
1289*4882a593Smuzhiyun * @entry: Pointer to &struct queue_entry
1290*4882a593Smuzhiyun */
1291*4882a593Smuzhiyun void rt2x00queue_unmap_skb(struct queue_entry *entry);
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun /**
1294*4882a593Smuzhiyun * rt2x00queue_get_tx_queue - Convert tx queue index to queue pointer
1295*4882a593Smuzhiyun * @rt2x00dev: Pointer to &struct rt2x00_dev.
1296*4882a593Smuzhiyun * @queue: rt2x00 queue index (see &enum data_queue_qid).
1297*4882a593Smuzhiyun *
1298*4882a593Smuzhiyun * Returns NULL for non tx queues.
1299*4882a593Smuzhiyun */
1300*4882a593Smuzhiyun static inline struct data_queue *
rt2x00queue_get_tx_queue(struct rt2x00_dev * rt2x00dev,const enum data_queue_qid queue)1301*4882a593Smuzhiyun rt2x00queue_get_tx_queue(struct rt2x00_dev *rt2x00dev,
1302*4882a593Smuzhiyun const enum data_queue_qid queue)
1303*4882a593Smuzhiyun {
1304*4882a593Smuzhiyun if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
1305*4882a593Smuzhiyun return &rt2x00dev->tx[queue];
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun if (queue == QID_ATIM)
1308*4882a593Smuzhiyun return rt2x00dev->atim;
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun return NULL;
1311*4882a593Smuzhiyun }
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun /**
1314*4882a593Smuzhiyun * rt2x00queue_get_entry - Get queue entry where the given index points to.
1315*4882a593Smuzhiyun * @queue: Pointer to &struct data_queue from where we obtain the entry.
1316*4882a593Smuzhiyun * @index: Index identifier for obtaining the correct index.
1317*4882a593Smuzhiyun */
1318*4882a593Smuzhiyun struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
1319*4882a593Smuzhiyun enum queue_index index);
1320*4882a593Smuzhiyun
1321*4882a593Smuzhiyun /**
1322*4882a593Smuzhiyun * rt2x00queue_pause_queue - Pause a data queue
1323*4882a593Smuzhiyun * @queue: Pointer to &struct data_queue.
1324*4882a593Smuzhiyun *
1325*4882a593Smuzhiyun * This function will pause the data queue locally, preventing
1326*4882a593Smuzhiyun * new frames to be added to the queue (while the hardware is
1327*4882a593Smuzhiyun * still allowed to run).
1328*4882a593Smuzhiyun */
1329*4882a593Smuzhiyun void rt2x00queue_pause_queue(struct data_queue *queue);
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun /**
1332*4882a593Smuzhiyun * rt2x00queue_unpause_queue - unpause a data queue
1333*4882a593Smuzhiyun * @queue: Pointer to &struct data_queue.
1334*4882a593Smuzhiyun *
1335*4882a593Smuzhiyun * This function will unpause the data queue locally, allowing
1336*4882a593Smuzhiyun * new frames to be added to the queue again.
1337*4882a593Smuzhiyun */
1338*4882a593Smuzhiyun void rt2x00queue_unpause_queue(struct data_queue *queue);
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun /**
1341*4882a593Smuzhiyun * rt2x00queue_start_queue - Start a data queue
1342*4882a593Smuzhiyun * @queue: Pointer to &struct data_queue.
1343*4882a593Smuzhiyun *
1344*4882a593Smuzhiyun * This function will start handling all pending frames in the queue.
1345*4882a593Smuzhiyun */
1346*4882a593Smuzhiyun void rt2x00queue_start_queue(struct data_queue *queue);
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun /**
1349*4882a593Smuzhiyun * rt2x00queue_stop_queue - Halt a data queue
1350*4882a593Smuzhiyun * @queue: Pointer to &struct data_queue.
1351*4882a593Smuzhiyun *
1352*4882a593Smuzhiyun * This function will stop all pending frames in the queue.
1353*4882a593Smuzhiyun */
1354*4882a593Smuzhiyun void rt2x00queue_stop_queue(struct data_queue *queue);
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun /**
1357*4882a593Smuzhiyun * rt2x00queue_flush_queue - Flush a data queue
1358*4882a593Smuzhiyun * @queue: Pointer to &struct data_queue.
1359*4882a593Smuzhiyun * @drop: True to drop all pending frames.
1360*4882a593Smuzhiyun *
1361*4882a593Smuzhiyun * This function will flush the queue. After this call
1362*4882a593Smuzhiyun * the queue is guaranteed to be empty.
1363*4882a593Smuzhiyun */
1364*4882a593Smuzhiyun void rt2x00queue_flush_queue(struct data_queue *queue, bool drop);
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun /**
1367*4882a593Smuzhiyun * rt2x00queue_start_queues - Start all data queues
1368*4882a593Smuzhiyun * @rt2x00dev: Pointer to &struct rt2x00_dev.
1369*4882a593Smuzhiyun *
1370*4882a593Smuzhiyun * This function will loop through all available queues to start them
1371*4882a593Smuzhiyun */
1372*4882a593Smuzhiyun void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev);
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun /**
1375*4882a593Smuzhiyun * rt2x00queue_stop_queues - Halt all data queues
1376*4882a593Smuzhiyun * @rt2x00dev: Pointer to &struct rt2x00_dev.
1377*4882a593Smuzhiyun *
1378*4882a593Smuzhiyun * This function will loop through all available queues to stop
1379*4882a593Smuzhiyun * any pending frames.
1380*4882a593Smuzhiyun */
1381*4882a593Smuzhiyun void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev);
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun /**
1384*4882a593Smuzhiyun * rt2x00queue_flush_queues - Flush all data queues
1385*4882a593Smuzhiyun * @rt2x00dev: Pointer to &struct rt2x00_dev.
1386*4882a593Smuzhiyun * @drop: True to drop all pending frames.
1387*4882a593Smuzhiyun *
1388*4882a593Smuzhiyun * This function will loop through all available queues to flush
1389*4882a593Smuzhiyun * any pending frames.
1390*4882a593Smuzhiyun */
1391*4882a593Smuzhiyun void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop);
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun /*
1394*4882a593Smuzhiyun * Debugfs handlers.
1395*4882a593Smuzhiyun */
1396*4882a593Smuzhiyun /**
1397*4882a593Smuzhiyun * rt2x00debug_dump_frame - Dump a frame to userspace through debugfs.
1398*4882a593Smuzhiyun * @rt2x00dev: Pointer to &struct rt2x00_dev.
1399*4882a593Smuzhiyun * @type: The type of frame that is being dumped.
1400*4882a593Smuzhiyun * @entry: The queue entry containing the frame to be dumped.
1401*4882a593Smuzhiyun */
1402*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1403*4882a593Smuzhiyun void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
1404*4882a593Smuzhiyun enum rt2x00_dump_type type, struct queue_entry *entry);
1405*4882a593Smuzhiyun #else
rt2x00debug_dump_frame(struct rt2x00_dev * rt2x00dev,enum rt2x00_dump_type type,struct queue_entry * entry)1406*4882a593Smuzhiyun static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
1407*4882a593Smuzhiyun enum rt2x00_dump_type type,
1408*4882a593Smuzhiyun struct queue_entry *entry)
1409*4882a593Smuzhiyun {
1410*4882a593Smuzhiyun }
1411*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1412*4882a593Smuzhiyun
1413*4882a593Smuzhiyun /*
1414*4882a593Smuzhiyun * Utility functions.
1415*4882a593Smuzhiyun */
1416*4882a593Smuzhiyun u32 rt2x00lib_get_bssidx(struct rt2x00_dev *rt2x00dev,
1417*4882a593Smuzhiyun struct ieee80211_vif *vif);
1418*4882a593Smuzhiyun void rt2x00lib_set_mac_address(struct rt2x00_dev *rt2x00dev, u8 *eeprom_mac_addr);
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun /*
1421*4882a593Smuzhiyun * Interrupt context handlers.
1422*4882a593Smuzhiyun */
1423*4882a593Smuzhiyun void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev);
1424*4882a593Smuzhiyun void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev);
1425*4882a593Smuzhiyun void rt2x00lib_dmastart(struct queue_entry *entry);
1426*4882a593Smuzhiyun void rt2x00lib_dmadone(struct queue_entry *entry);
1427*4882a593Smuzhiyun void rt2x00lib_txdone(struct queue_entry *entry,
1428*4882a593Smuzhiyun struct txdone_entry_desc *txdesc);
1429*4882a593Smuzhiyun void rt2x00lib_txdone_nomatch(struct queue_entry *entry,
1430*4882a593Smuzhiyun struct txdone_entry_desc *txdesc);
1431*4882a593Smuzhiyun void rt2x00lib_txdone_noinfo(struct queue_entry *entry, u32 status);
1432*4882a593Smuzhiyun void rt2x00lib_rxdone(struct queue_entry *entry, gfp_t gfp);
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun /*
1435*4882a593Smuzhiyun * mac80211 handlers.
1436*4882a593Smuzhiyun */
1437*4882a593Smuzhiyun void rt2x00mac_tx(struct ieee80211_hw *hw,
1438*4882a593Smuzhiyun struct ieee80211_tx_control *control,
1439*4882a593Smuzhiyun struct sk_buff *skb);
1440*4882a593Smuzhiyun int rt2x00mac_start(struct ieee80211_hw *hw);
1441*4882a593Smuzhiyun void rt2x00mac_stop(struct ieee80211_hw *hw);
1442*4882a593Smuzhiyun void rt2x00mac_reconfig_complete(struct ieee80211_hw *hw,
1443*4882a593Smuzhiyun enum ieee80211_reconfig_type reconfig_type);
1444*4882a593Smuzhiyun int rt2x00mac_add_interface(struct ieee80211_hw *hw,
1445*4882a593Smuzhiyun struct ieee80211_vif *vif);
1446*4882a593Smuzhiyun void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
1447*4882a593Smuzhiyun struct ieee80211_vif *vif);
1448*4882a593Smuzhiyun int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed);
1449*4882a593Smuzhiyun void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
1450*4882a593Smuzhiyun unsigned int changed_flags,
1451*4882a593Smuzhiyun unsigned int *total_flags,
1452*4882a593Smuzhiyun u64 multicast);
1453*4882a593Smuzhiyun int rt2x00mac_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
1454*4882a593Smuzhiyun bool set);
1455*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_LIB_CRYPTO
1456*4882a593Smuzhiyun int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
1457*4882a593Smuzhiyun struct ieee80211_vif *vif, struct ieee80211_sta *sta,
1458*4882a593Smuzhiyun struct ieee80211_key_conf *key);
1459*4882a593Smuzhiyun #else
1460*4882a593Smuzhiyun #define rt2x00mac_set_key NULL
1461*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_LIB_CRYPTO */
1462*4882a593Smuzhiyun void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw,
1463*4882a593Smuzhiyun struct ieee80211_vif *vif,
1464*4882a593Smuzhiyun const u8 *mac_addr);
1465*4882a593Smuzhiyun void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw,
1466*4882a593Smuzhiyun struct ieee80211_vif *vif);
1467*4882a593Smuzhiyun int rt2x00mac_get_stats(struct ieee80211_hw *hw,
1468*4882a593Smuzhiyun struct ieee80211_low_level_stats *stats);
1469*4882a593Smuzhiyun void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
1470*4882a593Smuzhiyun struct ieee80211_vif *vif,
1471*4882a593Smuzhiyun struct ieee80211_bss_conf *bss_conf,
1472*4882a593Smuzhiyun u32 changes);
1473*4882a593Smuzhiyun int rt2x00mac_conf_tx(struct ieee80211_hw *hw,
1474*4882a593Smuzhiyun struct ieee80211_vif *vif, u16 queue,
1475*4882a593Smuzhiyun const struct ieee80211_tx_queue_params *params);
1476*4882a593Smuzhiyun void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw);
1477*4882a593Smuzhiyun void rt2x00mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1478*4882a593Smuzhiyun u32 queues, bool drop);
1479*4882a593Smuzhiyun int rt2x00mac_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant);
1480*4882a593Smuzhiyun int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
1481*4882a593Smuzhiyun void rt2x00mac_get_ringparam(struct ieee80211_hw *hw,
1482*4882a593Smuzhiyun u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max);
1483*4882a593Smuzhiyun bool rt2x00mac_tx_frames_pending(struct ieee80211_hw *hw);
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun /*
1486*4882a593Smuzhiyun * Driver allocation handlers.
1487*4882a593Smuzhiyun */
1488*4882a593Smuzhiyun int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev);
1489*4882a593Smuzhiyun void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev);
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev);
1492*4882a593Smuzhiyun int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev);
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun #endif /* RT2X00_H */
1495