1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
4*4882a593Smuzhiyun Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5*4882a593Smuzhiyun Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6*4882a593Smuzhiyun Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7*4882a593Smuzhiyun Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8*4882a593Smuzhiyun Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9*4882a593Smuzhiyun Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10*4882a593Smuzhiyun Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11*4882a593Smuzhiyun <http://rt2x00.serialmonkey.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun Module: rt2800pci
17*4882a593Smuzhiyun Abstract: rt2800pci device specific routines.
18*4882a593Smuzhiyun Supported chipsets: RT2800E & RT2800ED.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/etherdevice.h>
23*4882a593Smuzhiyun #include <linux/init.h>
24*4882a593Smuzhiyun #include <linux/kernel.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <linux/pci.h>
27*4882a593Smuzhiyun #include <linux/eeprom_93cx6.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include "rt2x00.h"
30*4882a593Smuzhiyun #include "rt2x00mmio.h"
31*4882a593Smuzhiyun #include "rt2x00pci.h"
32*4882a593Smuzhiyun #include "rt2800lib.h"
33*4882a593Smuzhiyun #include "rt2800mmio.h"
34*4882a593Smuzhiyun #include "rt2800.h"
35*4882a593Smuzhiyun #include "rt2800pci.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Allow hardware encryption to be disabled.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun static bool modparam_nohwcrypt = false;
41*4882a593Smuzhiyun module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
42*4882a593Smuzhiyun MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
43*4882a593Smuzhiyun
rt2800pci_hwcrypt_disabled(struct rt2x00_dev * rt2x00dev)44*4882a593Smuzhiyun static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun return modparam_nohwcrypt;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
rt2800pci_mcu_status(struct rt2x00_dev * rt2x00dev,const u8 token)49*4882a593Smuzhiyun static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun unsigned int i;
52*4882a593Smuzhiyun u32 reg;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * SOC devices don't support MCU requests.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun if (rt2x00_is_soc(rt2x00dev))
58*4882a593Smuzhiyun return;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (i = 0; i < 200; i++) {
61*4882a593Smuzhiyun reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
64*4882a593Smuzhiyun (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
65*4882a593Smuzhiyun (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
66*4882a593Smuzhiyun (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
67*4882a593Smuzhiyun break;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun udelay(REGISTER_BUSY_DELAY);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (i == 200)
73*4882a593Smuzhiyun rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
76*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
rt2800pci_eepromregister_read(struct eeprom_93cx6 * eeprom)79*4882a593Smuzhiyun static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct rt2x00_dev *rt2x00dev = eeprom->data;
82*4882a593Smuzhiyun u32 reg;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
87*4882a593Smuzhiyun eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
88*4882a593Smuzhiyun eeprom->reg_data_clock =
89*4882a593Smuzhiyun !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
90*4882a593Smuzhiyun eeprom->reg_chip_select =
91*4882a593Smuzhiyun !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
rt2800pci_eepromregister_write(struct eeprom_93cx6 * eeprom)94*4882a593Smuzhiyun static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct rt2x00_dev *rt2x00dev = eeprom->data;
97*4882a593Smuzhiyun u32 reg = 0;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
100*4882a593Smuzhiyun rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
101*4882a593Smuzhiyun rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
102*4882a593Smuzhiyun !!eeprom->reg_data_clock);
103*4882a593Smuzhiyun rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
104*4882a593Smuzhiyun !!eeprom->reg_chip_select);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
rt2800pci_read_eeprom_pci(struct rt2x00_dev * rt2x00dev)109*4882a593Smuzhiyun static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct eeprom_93cx6 eeprom;
112*4882a593Smuzhiyun u32 reg;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun eeprom.data = rt2x00dev;
117*4882a593Smuzhiyun eeprom.register_read = rt2800pci_eepromregister_read;
118*4882a593Smuzhiyun eeprom.register_write = rt2800pci_eepromregister_write;
119*4882a593Smuzhiyun switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun case 0:
122*4882a593Smuzhiyun eeprom.width = PCI_EEPROM_WIDTH_93C46;
123*4882a593Smuzhiyun break;
124*4882a593Smuzhiyun case 1:
125*4882a593Smuzhiyun eeprom.width = PCI_EEPROM_WIDTH_93C66;
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun default:
128*4882a593Smuzhiyun eeprom.width = PCI_EEPROM_WIDTH_93C86;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun eeprom.reg_data_in = 0;
132*4882a593Smuzhiyun eeprom.reg_data_out = 0;
133*4882a593Smuzhiyun eeprom.reg_data_clock = 0;
134*4882a593Smuzhiyun eeprom.reg_chip_select = 0;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
137*4882a593Smuzhiyun EEPROM_SIZE / sizeof(u16));
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
rt2800pci_efuse_detect(struct rt2x00_dev * rt2x00dev)142*4882a593Smuzhiyun static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun return rt2800_efuse_detect(rt2x00dev);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
rt2800pci_read_eeprom_efuse(struct rt2x00_dev * rt2x00dev)147*4882a593Smuzhiyun static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun return rt2800_read_eeprom_efuse(rt2x00dev);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun * Firmware functions
154*4882a593Smuzhiyun */
rt2800pci_get_firmware_name(struct rt2x00_dev * rt2x00dev)155*4882a593Smuzhiyun static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * Chip rt3290 use specific 4KB firmware named rt3290.bin.
159*4882a593Smuzhiyun */
160*4882a593Smuzhiyun if (rt2x00_rt(rt2x00dev, RT3290))
161*4882a593Smuzhiyun return FIRMWARE_RT3290;
162*4882a593Smuzhiyun else
163*4882a593Smuzhiyun return FIRMWARE_RT2860;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
rt2800pci_write_firmware(struct rt2x00_dev * rt2x00dev,const u8 * data,const size_t len)166*4882a593Smuzhiyun static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
167*4882a593Smuzhiyun const u8 *data, const size_t len)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun u32 reg;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /*
172*4882a593Smuzhiyun * enable Host program ram write selection
173*4882a593Smuzhiyun */
174*4882a593Smuzhiyun reg = 0;
175*4882a593Smuzhiyun rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
176*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /*
179*4882a593Smuzhiyun * Write firmware to device.
180*4882a593Smuzhiyun */
181*4882a593Smuzhiyun rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
182*4882a593Smuzhiyun data, len);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
185*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
188*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /*
194*4882a593Smuzhiyun * Device state switch handlers.
195*4882a593Smuzhiyun */
rt2800pci_enable_radio(struct rt2x00_dev * rt2x00dev)196*4882a593Smuzhiyun static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun int retval;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun retval = rt2800mmio_enable_radio(rt2x00dev);
201*4882a593Smuzhiyun if (retval)
202*4882a593Smuzhiyun return retval;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* After resume MCU_BOOT_SIGNAL will trash these. */
205*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
206*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
209*4882a593Smuzhiyun rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
212*4882a593Smuzhiyun rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun return retval;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
rt2800pci_set_state(struct rt2x00_dev * rt2x00dev,enum dev_state state)217*4882a593Smuzhiyun static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
218*4882a593Smuzhiyun enum dev_state state)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun if (state == STATE_AWAKE) {
221*4882a593Smuzhiyun rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
222*4882a593Smuzhiyun 0, 0x02);
223*4882a593Smuzhiyun rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
224*4882a593Smuzhiyun } else if (state == STATE_SLEEP) {
225*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
226*4882a593Smuzhiyun 0xffffffff);
227*4882a593Smuzhiyun rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
228*4882a593Smuzhiyun 0xffffffff);
229*4882a593Smuzhiyun rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
230*4882a593Smuzhiyun 0xff, 0x01);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
rt2800pci_set_device_state(struct rt2x00_dev * rt2x00dev,enum dev_state state)236*4882a593Smuzhiyun static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
237*4882a593Smuzhiyun enum dev_state state)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun int retval = 0;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun switch (state) {
242*4882a593Smuzhiyun case STATE_RADIO_ON:
243*4882a593Smuzhiyun retval = rt2800pci_enable_radio(rt2x00dev);
244*4882a593Smuzhiyun break;
245*4882a593Smuzhiyun case STATE_RADIO_OFF:
246*4882a593Smuzhiyun /*
247*4882a593Smuzhiyun * After the radio has been disabled, the device should
248*4882a593Smuzhiyun * be put to sleep for powersaving.
249*4882a593Smuzhiyun */
250*4882a593Smuzhiyun rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
251*4882a593Smuzhiyun break;
252*4882a593Smuzhiyun case STATE_RADIO_IRQ_ON:
253*4882a593Smuzhiyun case STATE_RADIO_IRQ_OFF:
254*4882a593Smuzhiyun rt2800mmio_toggle_irq(rt2x00dev, state);
255*4882a593Smuzhiyun break;
256*4882a593Smuzhiyun case STATE_DEEP_SLEEP:
257*4882a593Smuzhiyun case STATE_SLEEP:
258*4882a593Smuzhiyun case STATE_STANDBY:
259*4882a593Smuzhiyun case STATE_AWAKE:
260*4882a593Smuzhiyun retval = rt2800pci_set_state(rt2x00dev, state);
261*4882a593Smuzhiyun break;
262*4882a593Smuzhiyun default:
263*4882a593Smuzhiyun retval = -ENOTSUPP;
264*4882a593Smuzhiyun break;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (unlikely(retval))
268*4882a593Smuzhiyun rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
269*4882a593Smuzhiyun state, retval);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return retval;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /*
275*4882a593Smuzhiyun * Device probe functions.
276*4882a593Smuzhiyun */
rt2800pci_read_eeprom(struct rt2x00_dev * rt2x00dev)277*4882a593Smuzhiyun static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun int retval;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun if (rt2800pci_efuse_detect(rt2x00dev))
282*4882a593Smuzhiyun retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
283*4882a593Smuzhiyun else
284*4882a593Smuzhiyun retval = rt2800pci_read_eeprom_pci(rt2x00dev);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun return retval;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun static const struct ieee80211_ops rt2800pci_mac80211_ops = {
290*4882a593Smuzhiyun .tx = rt2x00mac_tx,
291*4882a593Smuzhiyun .start = rt2x00mac_start,
292*4882a593Smuzhiyun .stop = rt2x00mac_stop,
293*4882a593Smuzhiyun .add_interface = rt2x00mac_add_interface,
294*4882a593Smuzhiyun .remove_interface = rt2x00mac_remove_interface,
295*4882a593Smuzhiyun .config = rt2x00mac_config,
296*4882a593Smuzhiyun .configure_filter = rt2x00mac_configure_filter,
297*4882a593Smuzhiyun .set_key = rt2x00mac_set_key,
298*4882a593Smuzhiyun .sw_scan_start = rt2x00mac_sw_scan_start,
299*4882a593Smuzhiyun .sw_scan_complete = rt2x00mac_sw_scan_complete,
300*4882a593Smuzhiyun .get_stats = rt2x00mac_get_stats,
301*4882a593Smuzhiyun .get_key_seq = rt2800_get_key_seq,
302*4882a593Smuzhiyun .set_rts_threshold = rt2800_set_rts_threshold,
303*4882a593Smuzhiyun .sta_add = rt2800_sta_add,
304*4882a593Smuzhiyun .sta_remove = rt2800_sta_remove,
305*4882a593Smuzhiyun .bss_info_changed = rt2x00mac_bss_info_changed,
306*4882a593Smuzhiyun .conf_tx = rt2800_conf_tx,
307*4882a593Smuzhiyun .get_tsf = rt2800_get_tsf,
308*4882a593Smuzhiyun .rfkill_poll = rt2x00mac_rfkill_poll,
309*4882a593Smuzhiyun .ampdu_action = rt2800_ampdu_action,
310*4882a593Smuzhiyun .flush = rt2x00mac_flush,
311*4882a593Smuzhiyun .get_survey = rt2800_get_survey,
312*4882a593Smuzhiyun .get_ringparam = rt2x00mac_get_ringparam,
313*4882a593Smuzhiyun .tx_frames_pending = rt2x00mac_tx_frames_pending,
314*4882a593Smuzhiyun .reconfig_complete = rt2x00mac_reconfig_complete,
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun static const struct rt2800_ops rt2800pci_rt2800_ops = {
318*4882a593Smuzhiyun .register_read = rt2x00mmio_register_read,
319*4882a593Smuzhiyun .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
320*4882a593Smuzhiyun .register_write = rt2x00mmio_register_write,
321*4882a593Smuzhiyun .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
322*4882a593Smuzhiyun .register_multiread = rt2x00mmio_register_multiread,
323*4882a593Smuzhiyun .register_multiwrite = rt2x00mmio_register_multiwrite,
324*4882a593Smuzhiyun .regbusy_read = rt2x00mmio_regbusy_read,
325*4882a593Smuzhiyun .read_eeprom = rt2800pci_read_eeprom,
326*4882a593Smuzhiyun .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
327*4882a593Smuzhiyun .drv_write_firmware = rt2800pci_write_firmware,
328*4882a593Smuzhiyun .drv_init_registers = rt2800mmio_init_registers,
329*4882a593Smuzhiyun .drv_get_txwi = rt2800mmio_get_txwi,
330*4882a593Smuzhiyun .drv_get_dma_done = rt2800mmio_get_dma_done,
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
334*4882a593Smuzhiyun .irq_handler = rt2800mmio_interrupt,
335*4882a593Smuzhiyun .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
336*4882a593Smuzhiyun .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
337*4882a593Smuzhiyun .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
338*4882a593Smuzhiyun .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
339*4882a593Smuzhiyun .autowake_tasklet = rt2800mmio_autowake_tasklet,
340*4882a593Smuzhiyun .probe_hw = rt2800mmio_probe_hw,
341*4882a593Smuzhiyun .get_firmware_name = rt2800pci_get_firmware_name,
342*4882a593Smuzhiyun .check_firmware = rt2800_check_firmware,
343*4882a593Smuzhiyun .load_firmware = rt2800_load_firmware,
344*4882a593Smuzhiyun .initialize = rt2x00mmio_initialize,
345*4882a593Smuzhiyun .uninitialize = rt2x00mmio_uninitialize,
346*4882a593Smuzhiyun .get_entry_state = rt2800mmio_get_entry_state,
347*4882a593Smuzhiyun .clear_entry = rt2800mmio_clear_entry,
348*4882a593Smuzhiyun .set_device_state = rt2800pci_set_device_state,
349*4882a593Smuzhiyun .rfkill_poll = rt2800_rfkill_poll,
350*4882a593Smuzhiyun .link_stats = rt2800_link_stats,
351*4882a593Smuzhiyun .reset_tuner = rt2800_reset_tuner,
352*4882a593Smuzhiyun .link_tuner = rt2800_link_tuner,
353*4882a593Smuzhiyun .gain_calibration = rt2800_gain_calibration,
354*4882a593Smuzhiyun .vco_calibration = rt2800_vco_calibration,
355*4882a593Smuzhiyun .watchdog = rt2800_watchdog,
356*4882a593Smuzhiyun .start_queue = rt2800mmio_start_queue,
357*4882a593Smuzhiyun .kick_queue = rt2800mmio_kick_queue,
358*4882a593Smuzhiyun .stop_queue = rt2800mmio_stop_queue,
359*4882a593Smuzhiyun .flush_queue = rt2800mmio_flush_queue,
360*4882a593Smuzhiyun .write_tx_desc = rt2800mmio_write_tx_desc,
361*4882a593Smuzhiyun .write_tx_data = rt2800_write_tx_data,
362*4882a593Smuzhiyun .write_beacon = rt2800_write_beacon,
363*4882a593Smuzhiyun .clear_beacon = rt2800_clear_beacon,
364*4882a593Smuzhiyun .fill_rxdone = rt2800mmio_fill_rxdone,
365*4882a593Smuzhiyun .config_shared_key = rt2800_config_shared_key,
366*4882a593Smuzhiyun .config_pairwise_key = rt2800_config_pairwise_key,
367*4882a593Smuzhiyun .config_filter = rt2800_config_filter,
368*4882a593Smuzhiyun .config_intf = rt2800_config_intf,
369*4882a593Smuzhiyun .config_erp = rt2800_config_erp,
370*4882a593Smuzhiyun .config_ant = rt2800_config_ant,
371*4882a593Smuzhiyun .config = rt2800_config,
372*4882a593Smuzhiyun .pre_reset_hw = rt2800_pre_reset_hw,
373*4882a593Smuzhiyun };
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun static const struct rt2x00_ops rt2800pci_ops = {
376*4882a593Smuzhiyun .name = KBUILD_MODNAME,
377*4882a593Smuzhiyun .drv_data_size = sizeof(struct rt2800_drv_data),
378*4882a593Smuzhiyun .max_ap_intf = 8,
379*4882a593Smuzhiyun .eeprom_size = EEPROM_SIZE,
380*4882a593Smuzhiyun .rf_size = RF_SIZE,
381*4882a593Smuzhiyun .tx_queues = NUM_TX_QUEUES,
382*4882a593Smuzhiyun .queue_init = rt2800mmio_queue_init,
383*4882a593Smuzhiyun .lib = &rt2800pci_rt2x00_ops,
384*4882a593Smuzhiyun .drv = &rt2800pci_rt2800_ops,
385*4882a593Smuzhiyun .hw = &rt2800pci_mac80211_ops,
386*4882a593Smuzhiyun #ifdef CONFIG_RT2X00_LIB_DEBUGFS
387*4882a593Smuzhiyun .debugfs = &rt2800_rt2x00debug,
388*4882a593Smuzhiyun #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /*
392*4882a593Smuzhiyun * RT2800pci module information.
393*4882a593Smuzhiyun */
394*4882a593Smuzhiyun static const struct pci_device_id rt2800pci_device_table[] = {
395*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x0601) },
396*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x0681) },
397*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x0701) },
398*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x0781) },
399*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3090) },
400*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3091) },
401*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3092) },
402*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7708) },
403*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7727) },
404*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7728) },
405*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7738) },
406*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7748) },
407*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7758) },
408*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7768) },
409*4882a593Smuzhiyun { PCI_DEVICE(0x1462, 0x891a) },
410*4882a593Smuzhiyun { PCI_DEVICE(0x1a3b, 0x1059) },
411*4882a593Smuzhiyun #ifdef CONFIG_RT2800PCI_RT3290
412*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3290) },
413*4882a593Smuzhiyun #endif
414*4882a593Smuzhiyun #ifdef CONFIG_RT2800PCI_RT33XX
415*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3390) },
416*4882a593Smuzhiyun #endif
417*4882a593Smuzhiyun #ifdef CONFIG_RT2800PCI_RT35XX
418*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7711) },
419*4882a593Smuzhiyun { PCI_DEVICE(0x1432, 0x7722) },
420*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3060) },
421*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3062) },
422*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3562) },
423*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3592) },
424*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x3593) },
425*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x359f) },
426*4882a593Smuzhiyun #endif
427*4882a593Smuzhiyun #ifdef CONFIG_RT2800PCI_RT53XX
428*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x5360) },
429*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x5362) },
430*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x5390) },
431*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x5392) },
432*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x539a) },
433*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x539b) },
434*4882a593Smuzhiyun { PCI_DEVICE(0x1814, 0x539f) },
435*4882a593Smuzhiyun #endif
436*4882a593Smuzhiyun { 0, }
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun MODULE_AUTHOR(DRV_PROJECT);
440*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
441*4882a593Smuzhiyun MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
442*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
443*4882a593Smuzhiyun MODULE_FIRMWARE(FIRMWARE_RT2860);
444*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
445*4882a593Smuzhiyun MODULE_LICENSE("GPL");
446*4882a593Smuzhiyun
rt2800pci_probe(struct pci_dev * pci_dev,const struct pci_device_id * id)447*4882a593Smuzhiyun static int rt2800pci_probe(struct pci_dev *pci_dev,
448*4882a593Smuzhiyun const struct pci_device_id *id)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun static struct pci_driver rt2800pci_driver = {
454*4882a593Smuzhiyun .name = KBUILD_MODNAME,
455*4882a593Smuzhiyun .id_table = rt2800pci_device_table,
456*4882a593Smuzhiyun .probe = rt2800pci_probe,
457*4882a593Smuzhiyun .remove = rt2x00pci_remove,
458*4882a593Smuzhiyun .driver.pm = &rt2x00pci_pm_ops,
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun module_pci_driver(rt2800pci_driver);
462