1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 3*4882a593Smuzhiyun * Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 4*4882a593Smuzhiyun * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 5*4882a593Smuzhiyun * Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 6*4882a593Smuzhiyun * Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 7*4882a593Smuzhiyun * Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 8*4882a593Smuzhiyun * Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 9*4882a593Smuzhiyun * Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 10*4882a593Smuzhiyun * <http://rt2x00.serialmonkey.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Module: rt2800mmio 14*4882a593Smuzhiyun * Abstract: forward declarations for the rt2800mmio module. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef RT2800MMIO_H 18*4882a593Smuzhiyun #define RT2800MMIO_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Queue register offset macros 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define TX_QUEUE_REG_OFFSET 0x10 24*4882a593Smuzhiyun #define TX_BASE_PTR(__x) (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)) 25*4882a593Smuzhiyun #define TX_MAX_CNT(__x) (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)) 26*4882a593Smuzhiyun #define TX_CTX_IDX(__x) (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)) 27*4882a593Smuzhiyun #define TX_DTX_IDX(__x) (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * DMA descriptor defines. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define TXD_DESC_SIZE (4 * sizeof(__le32)) 33*4882a593Smuzhiyun #define RXD_DESC_SIZE (4 * sizeof(__le32)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * TX descriptor format for TX, PRIO and Beacon Ring. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Word0 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * Word1 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) 48*4882a593Smuzhiyun #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) 49*4882a593Smuzhiyun #define TXD_W1_BURST FIELD32(0x00008000) 50*4882a593Smuzhiyun #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) 51*4882a593Smuzhiyun #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) 52*4882a593Smuzhiyun #define TXD_W1_DMA_DONE FIELD32(0x80000000) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Word2 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * Word3 61*4882a593Smuzhiyun * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI 62*4882a593Smuzhiyun * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler. 63*4882a593Smuzhiyun * 0:MGMT, 1:HCCA 2:EDCA 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define TXD_W3_WIV FIELD32(0x01000000) 66*4882a593Smuzhiyun #define TXD_W3_QSEL FIELD32(0x06000000) 67*4882a593Smuzhiyun #define TXD_W3_TCO FIELD32(0x20000000) 68*4882a593Smuzhiyun #define TXD_W3_UCO FIELD32(0x40000000) 69*4882a593Smuzhiyun #define TXD_W3_ICO FIELD32(0x80000000) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * RX descriptor format for RX Ring. 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * Word0 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define RXD_W0_SDP0 FIELD32(0xffffffff) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * Word1 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define RXD_W1_SDL1 FIELD32(0x00003fff) 84*4882a593Smuzhiyun #define RXD_W1_SDL0 FIELD32(0x3fff0000) 85*4882a593Smuzhiyun #define RXD_W1_LS0 FIELD32(0x40000000) 86*4882a593Smuzhiyun #define RXD_W1_DMA_DONE FIELD32(0x80000000) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Word2 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun #define RXD_W2_SDP1 FIELD32(0xffffffff) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * Word3 95*4882a593Smuzhiyun * AMSDU: RX with 802.3 header, not 802.11 header. 96*4882a593Smuzhiyun * DECRYPTED: This frame is being decrypted. 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun #define RXD_W3_BA FIELD32(0x00000001) 99*4882a593Smuzhiyun #define RXD_W3_DATA FIELD32(0x00000002) 100*4882a593Smuzhiyun #define RXD_W3_NULLDATA FIELD32(0x00000004) 101*4882a593Smuzhiyun #define RXD_W3_FRAG FIELD32(0x00000008) 102*4882a593Smuzhiyun #define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010) 103*4882a593Smuzhiyun #define RXD_W3_MULTICAST FIELD32(0x00000020) 104*4882a593Smuzhiyun #define RXD_W3_BROADCAST FIELD32(0x00000040) 105*4882a593Smuzhiyun #define RXD_W3_MY_BSS FIELD32(0x00000080) 106*4882a593Smuzhiyun #define RXD_W3_CRC_ERROR FIELD32(0x00000100) 107*4882a593Smuzhiyun #define RXD_W3_CIPHER_ERROR FIELD32(0x00000600) 108*4882a593Smuzhiyun #define RXD_W3_AMSDU FIELD32(0x00000800) 109*4882a593Smuzhiyun #define RXD_W3_HTC FIELD32(0x00001000) 110*4882a593Smuzhiyun #define RXD_W3_RSSI FIELD32(0x00002000) 111*4882a593Smuzhiyun #define RXD_W3_L2PAD FIELD32(0x00004000) 112*4882a593Smuzhiyun #define RXD_W3_AMPDU FIELD32(0x00008000) 113*4882a593Smuzhiyun #define RXD_W3_DECRYPTED FIELD32(0x00010000) 114*4882a593Smuzhiyun #define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000) 115*4882a593Smuzhiyun #define RXD_W3_PLCP_RSSI FIELD32(0x00040000) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun unsigned int rt2800mmio_get_dma_done(struct data_queue *queue); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* TX descriptor initialization */ 120*4882a593Smuzhiyun __le32 *rt2800mmio_get_txwi(struct queue_entry *entry); 121*4882a593Smuzhiyun void rt2800mmio_write_tx_desc(struct queue_entry *entry, 122*4882a593Smuzhiyun struct txentry_desc *txdesc); 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* RX control handlers */ 125*4882a593Smuzhiyun void rt2800mmio_fill_rxdone(struct queue_entry *entry, 126*4882a593Smuzhiyun struct rxdone_entry_desc *rxdesc); 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Interrupt functions */ 129*4882a593Smuzhiyun void rt2800mmio_txstatus_tasklet(struct tasklet_struct *t); 130*4882a593Smuzhiyun void rt2800mmio_pretbtt_tasklet(struct tasklet_struct *t); 131*4882a593Smuzhiyun void rt2800mmio_tbtt_tasklet(struct tasklet_struct *t); 132*4882a593Smuzhiyun void rt2800mmio_rxdone_tasklet(struct tasklet_struct *t); 133*4882a593Smuzhiyun void rt2800mmio_autowake_tasklet(struct tasklet_struct *t); 134*4882a593Smuzhiyun irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance); 135*4882a593Smuzhiyun void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev, 136*4882a593Smuzhiyun enum dev_state state); 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* Queue handlers */ 139*4882a593Smuzhiyun void rt2800mmio_start_queue(struct data_queue *queue); 140*4882a593Smuzhiyun void rt2800mmio_kick_queue(struct data_queue *queue); 141*4882a593Smuzhiyun void rt2800mmio_flush_queue(struct data_queue *queue, bool drop); 142*4882a593Smuzhiyun void rt2800mmio_stop_queue(struct data_queue *queue); 143*4882a593Smuzhiyun void rt2800mmio_queue_init(struct data_queue *queue); 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Initialization functions */ 146*4882a593Smuzhiyun int rt2800mmio_probe_hw(struct rt2x00_dev *rt2x00dev); 147*4882a593Smuzhiyun bool rt2800mmio_get_entry_state(struct queue_entry *entry); 148*4882a593Smuzhiyun void rt2800mmio_clear_entry(struct queue_entry *entry); 149*4882a593Smuzhiyun int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev); 150*4882a593Smuzhiyun int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev); 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* Device state switch handlers. */ 153*4882a593Smuzhiyun int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev); 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #endif /* RT2800MMIO_H */ 156