xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/quantenna/qtnfmac/shm_ipc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /* Copyright (c) 2015-2016 Quantenna Communications. All rights reserved. */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <linux/types.h>
5*4882a593Smuzhiyun #include <linux/io.h>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include "shm_ipc.h"
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #undef pr_fmt
10*4882a593Smuzhiyun #define pr_fmt(fmt)	"qtnfmac shm_ipc: %s: " fmt, __func__
11*4882a593Smuzhiyun 
qtnf_shm_ipc_has_new_data(struct qtnf_shm_ipc * ipc)12*4882a593Smuzhiyun static bool qtnf_shm_ipc_has_new_data(struct qtnf_shm_ipc *ipc)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun 	const u32 flags = readl(&ipc->shm_region->headroom.hdr.flags);
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun 	return (flags & QTNF_SHM_IPC_NEW_DATA);
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun 
qtnf_shm_handle_new_data(struct qtnf_shm_ipc * ipc)19*4882a593Smuzhiyun static void qtnf_shm_handle_new_data(struct qtnf_shm_ipc *ipc)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun 	size_t size;
22*4882a593Smuzhiyun 	bool rx_buff_ok = true;
23*4882a593Smuzhiyun 	struct qtnf_shm_ipc_region_header __iomem *shm_reg_hdr;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	shm_reg_hdr = &ipc->shm_region->headroom.hdr;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	size = readw(&shm_reg_hdr->data_len);
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	if (unlikely(size == 0 || size > QTN_IPC_MAX_DATA_SZ)) {
30*4882a593Smuzhiyun 		pr_err("wrong rx packet size: %zu\n", size);
31*4882a593Smuzhiyun 		rx_buff_ok = false;
32*4882a593Smuzhiyun 	}
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	if (likely(rx_buff_ok)) {
35*4882a593Smuzhiyun 		ipc->rx_packet_count++;
36*4882a593Smuzhiyun 		ipc->rx_callback.fn(ipc->rx_callback.arg,
37*4882a593Smuzhiyun 				    ipc->shm_region->data, size);
38*4882a593Smuzhiyun 	}
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	writel(QTNF_SHM_IPC_ACK, &shm_reg_hdr->flags);
41*4882a593Smuzhiyun 	readl(&shm_reg_hdr->flags); /* flush PCIe write */
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	ipc->interrupt.fn(ipc->interrupt.arg);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun 
qtnf_shm_ipc_irq_work(struct work_struct * work)46*4882a593Smuzhiyun static void qtnf_shm_ipc_irq_work(struct work_struct *work)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	struct qtnf_shm_ipc *ipc = container_of(work, struct qtnf_shm_ipc,
49*4882a593Smuzhiyun 						irq_work);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	while (qtnf_shm_ipc_has_new_data(ipc))
52*4882a593Smuzhiyun 		qtnf_shm_handle_new_data(ipc);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
qtnf_shm_ipc_irq_inbound_handler(struct qtnf_shm_ipc * ipc)55*4882a593Smuzhiyun static void qtnf_shm_ipc_irq_inbound_handler(struct qtnf_shm_ipc *ipc)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	u32 flags;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	flags = readl(&ipc->shm_region->headroom.hdr.flags);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (flags & QTNF_SHM_IPC_NEW_DATA)
62*4882a593Smuzhiyun 		queue_work(ipc->workqueue, &ipc->irq_work);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
qtnf_shm_ipc_irq_outbound_handler(struct qtnf_shm_ipc * ipc)65*4882a593Smuzhiyun static void qtnf_shm_ipc_irq_outbound_handler(struct qtnf_shm_ipc *ipc)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	u32 flags;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	if (!READ_ONCE(ipc->waiting_for_ack))
70*4882a593Smuzhiyun 		return;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	flags = readl(&ipc->shm_region->headroom.hdr.flags);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	if (flags & QTNF_SHM_IPC_ACK) {
75*4882a593Smuzhiyun 		WRITE_ONCE(ipc->waiting_for_ack, 0);
76*4882a593Smuzhiyun 		complete(&ipc->tx_completion);
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
qtnf_shm_ipc_init(struct qtnf_shm_ipc * ipc,enum qtnf_shm_ipc_direction direction,struct qtnf_shm_ipc_region __iomem * shm_region,struct workqueue_struct * workqueue,const struct qtnf_shm_ipc_int * interrupt,const struct qtnf_shm_ipc_rx_callback * rx_callback)80*4882a593Smuzhiyun int qtnf_shm_ipc_init(struct qtnf_shm_ipc *ipc,
81*4882a593Smuzhiyun 		      enum qtnf_shm_ipc_direction direction,
82*4882a593Smuzhiyun 		      struct qtnf_shm_ipc_region __iomem *shm_region,
83*4882a593Smuzhiyun 		      struct workqueue_struct *workqueue,
84*4882a593Smuzhiyun 		      const struct qtnf_shm_ipc_int *interrupt,
85*4882a593Smuzhiyun 		      const struct qtnf_shm_ipc_rx_callback *rx_callback)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	BUILD_BUG_ON(offsetof(struct qtnf_shm_ipc_region, data) !=
88*4882a593Smuzhiyun 		     QTN_IPC_REG_HDR_SZ);
89*4882a593Smuzhiyun 	BUILD_BUG_ON(sizeof(struct qtnf_shm_ipc_region) > QTN_IPC_REG_SZ);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	ipc->shm_region = shm_region;
92*4882a593Smuzhiyun 	ipc->direction = direction;
93*4882a593Smuzhiyun 	ipc->interrupt = *interrupt;
94*4882a593Smuzhiyun 	ipc->rx_callback = *rx_callback;
95*4882a593Smuzhiyun 	ipc->tx_packet_count = 0;
96*4882a593Smuzhiyun 	ipc->rx_packet_count = 0;
97*4882a593Smuzhiyun 	ipc->workqueue = workqueue;
98*4882a593Smuzhiyun 	ipc->waiting_for_ack = 0;
99*4882a593Smuzhiyun 	ipc->tx_timeout_count = 0;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	switch (direction) {
102*4882a593Smuzhiyun 	case QTNF_SHM_IPC_OUTBOUND:
103*4882a593Smuzhiyun 		ipc->irq_handler = qtnf_shm_ipc_irq_outbound_handler;
104*4882a593Smuzhiyun 		break;
105*4882a593Smuzhiyun 	case QTNF_SHM_IPC_INBOUND:
106*4882a593Smuzhiyun 		ipc->irq_handler = qtnf_shm_ipc_irq_inbound_handler;
107*4882a593Smuzhiyun 		break;
108*4882a593Smuzhiyun 	default:
109*4882a593Smuzhiyun 		return -EINVAL;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	INIT_WORK(&ipc->irq_work, qtnf_shm_ipc_irq_work);
113*4882a593Smuzhiyun 	init_completion(&ipc->tx_completion);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
qtnf_shm_ipc_free(struct qtnf_shm_ipc * ipc)118*4882a593Smuzhiyun void qtnf_shm_ipc_free(struct qtnf_shm_ipc *ipc)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	complete_all(&ipc->tx_completion);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
qtnf_shm_ipc_send(struct qtnf_shm_ipc * ipc,const u8 * buf,size_t size)123*4882a593Smuzhiyun int qtnf_shm_ipc_send(struct qtnf_shm_ipc *ipc, const u8 *buf, size_t size)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	int ret = 0;
126*4882a593Smuzhiyun 	struct qtnf_shm_ipc_region_header __iomem *shm_reg_hdr;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	shm_reg_hdr = &ipc->shm_region->headroom.hdr;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	if (unlikely(size > QTN_IPC_MAX_DATA_SZ))
131*4882a593Smuzhiyun 		return -E2BIG;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	ipc->tx_packet_count++;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	writew(size, &shm_reg_hdr->data_len);
136*4882a593Smuzhiyun 	memcpy_toio(ipc->shm_region->data, buf, size);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/* sync previous writes before proceeding */
139*4882a593Smuzhiyun 	dma_wmb();
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	WRITE_ONCE(ipc->waiting_for_ack, 1);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* sync previous memory write before announcing new data ready */
144*4882a593Smuzhiyun 	wmb();
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	writel(QTNF_SHM_IPC_NEW_DATA, &shm_reg_hdr->flags);
147*4882a593Smuzhiyun 	readl(&shm_reg_hdr->flags); /* flush PCIe write */
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	ipc->interrupt.fn(ipc->interrupt.arg);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	if (!wait_for_completion_timeout(&ipc->tx_completion,
152*4882a593Smuzhiyun 					 QTN_SHM_IPC_ACK_TIMEOUT)) {
153*4882a593Smuzhiyun 		ret = -ETIMEDOUT;
154*4882a593Smuzhiyun 		ipc->tx_timeout_count++;
155*4882a593Smuzhiyun 		pr_err("TX ACK timeout\n");
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* now we're not waiting for ACK even in case of timeout */
159*4882a593Smuzhiyun 	WRITE_ONCE(ipc->waiting_for_ack, 0);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	return ret;
162*4882a593Smuzhiyun }
163