1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4*4882a593Smuzhiyun * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "mt7601u.h"
8*4882a593Smuzhiyun #include "trace.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun enum mt76_txq_id {
11*4882a593Smuzhiyun MT_TXQ_VO = IEEE80211_AC_VO,
12*4882a593Smuzhiyun MT_TXQ_VI = IEEE80211_AC_VI,
13*4882a593Smuzhiyun MT_TXQ_BE = IEEE80211_AC_BE,
14*4882a593Smuzhiyun MT_TXQ_BK = IEEE80211_AC_BK,
15*4882a593Smuzhiyun MT_TXQ_PSD,
16*4882a593Smuzhiyun MT_TXQ_MCU,
17*4882a593Smuzhiyun __MT_TXQ_MAX
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Hardware uses mirrored order of queues with Q0 having the highest priority */
q2hwq(u8 q)21*4882a593Smuzhiyun static u8 q2hwq(u8 q)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun return q ^ 0x3;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Take mac80211 Q id from the skb and translate it to hardware Q id */
skb2q(struct sk_buff * skb)27*4882a593Smuzhiyun static u8 skb2q(struct sk_buff *skb)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun int qid = skb_get_queue_mapping(skb);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (WARN_ON(qid >= MT_TXQ_PSD)) {
32*4882a593Smuzhiyun qid = MT_TXQ_BE;
33*4882a593Smuzhiyun skb_set_queue_mapping(skb, qid);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return q2hwq(qid);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Note: TX retry reporting is a bit broken.
40*4882a593Smuzhiyun * Retries are reported only once per AMPDU and often come a frame early
41*4882a593Smuzhiyun * i.e. they are reported in the last status preceding the AMPDU. Apart
42*4882a593Smuzhiyun * from the fact that it's hard to know the length of the AMPDU (which is
43*4882a593Smuzhiyun * required to know to how many consecutive frames retries should be
44*4882a593Smuzhiyun * applied), if status comes early on full FIFO it gets lost and retries
45*4882a593Smuzhiyun * of the whole AMPDU become invisible.
46*4882a593Smuzhiyun * As a work-around encode the desired rate in PKT_ID of TX descriptor
47*4882a593Smuzhiyun * and based on that guess the retries (every rate is tried once).
48*4882a593Smuzhiyun * Only downside here is that for MCS0 we have to rely solely on
49*4882a593Smuzhiyun * transmission failures as no retries can ever be reported.
50*4882a593Smuzhiyun * Not having to read EXT_FIFO has a nice effect of doubling the number
51*4882a593Smuzhiyun * of reports which can be fetched.
52*4882a593Smuzhiyun * Also the vendor driver never uses the EXT_FIFO register so it may be
53*4882a593Smuzhiyun * undertested.
54*4882a593Smuzhiyun */
mt7601u_tx_pktid_enc(struct mt7601u_dev * dev,u8 rate,bool is_probe)55*4882a593Smuzhiyun static u8 mt7601u_tx_pktid_enc(struct mt7601u_dev *dev, u8 rate, bool is_probe)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun u8 encoded = (rate + 1) + is_probe * 8;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Because PKT_ID 0 disables status reporting only 15 values are
60*4882a593Smuzhiyun * available but 16 are needed (8 MCS * 2 for encoding is_probe)
61*4882a593Smuzhiyun * - we need to cram together two rates. MCS0 and MCS7 with is_probe
62*4882a593Smuzhiyun * share PKT_ID 9.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun if (is_probe && rate == 7)
65*4882a593Smuzhiyun return encoded - 7;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return encoded;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static void
mt7601u_tx_pktid_dec(struct mt7601u_dev * dev,struct mt76_tx_status * stat)71*4882a593Smuzhiyun mt7601u_tx_pktid_dec(struct mt7601u_dev *dev, struct mt76_tx_status *stat)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun u8 req_rate = stat->pktid;
74*4882a593Smuzhiyun u8 eff_rate = stat->rate & 0x7;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun req_rate -= 1;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (req_rate > 7) {
79*4882a593Smuzhiyun stat->is_probe = true;
80*4882a593Smuzhiyun req_rate -= 8;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Decide between MCS0 and MCS7 which share pktid 9 */
83*4882a593Smuzhiyun if (!req_rate && eff_rate)
84*4882a593Smuzhiyun req_rate = 7;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun stat->retry = req_rate - eff_rate;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
mt7601u_tx_skb_remove_dma_overhead(struct sk_buff * skb,struct ieee80211_tx_info * info)90*4882a593Smuzhiyun static void mt7601u_tx_skb_remove_dma_overhead(struct sk_buff *skb,
91*4882a593Smuzhiyun struct ieee80211_tx_info *info)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int pkt_len = (unsigned long)info->status.status_driver_data[0];
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun skb_pull(skb, sizeof(struct mt76_txwi) + 4);
96*4882a593Smuzhiyun if (ieee80211_get_hdrlen_from_skb(skb) % 4)
97*4882a593Smuzhiyun mt76_remove_hdr_pad(skb);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun skb_trim(skb, pkt_len);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
mt7601u_tx_status(struct mt7601u_dev * dev,struct sk_buff * skb)102*4882a593Smuzhiyun void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun mt7601u_tx_skb_remove_dma_overhead(skb, info);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun ieee80211_tx_info_clear_status(info);
109*4882a593Smuzhiyun info->status.rates[0].idx = -1;
110*4882a593Smuzhiyun info->flags |= IEEE80211_TX_STAT_ACK;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun spin_lock_bh(&dev->mac_lock);
113*4882a593Smuzhiyun ieee80211_tx_status(dev->hw, skb);
114*4882a593Smuzhiyun spin_unlock_bh(&dev->mac_lock);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
mt7601u_skb_rooms(struct mt7601u_dev * dev,struct sk_buff * skb)117*4882a593Smuzhiyun static int mt7601u_skb_rooms(struct mt7601u_dev *dev, struct sk_buff *skb)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
120*4882a593Smuzhiyun u32 need_head;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun need_head = sizeof(struct mt76_txwi) + 4;
123*4882a593Smuzhiyun if (hdr_len % 4)
124*4882a593Smuzhiyun need_head += 2;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return skb_cow(skb, need_head);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static struct mt76_txwi *
mt7601u_push_txwi(struct mt7601u_dev * dev,struct sk_buff * skb,struct ieee80211_sta * sta,struct mt76_wcid * wcid,int pkt_len)130*4882a593Smuzhiyun mt7601u_push_txwi(struct mt7601u_dev *dev, struct sk_buff *skb,
131*4882a593Smuzhiyun struct ieee80211_sta *sta, struct mt76_wcid *wcid,
132*4882a593Smuzhiyun int pkt_len)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
135*4882a593Smuzhiyun struct ieee80211_tx_rate *rate = &info->control.rates[0];
136*4882a593Smuzhiyun struct mt76_txwi *txwi;
137*4882a593Smuzhiyun unsigned long flags;
138*4882a593Smuzhiyun bool is_probe;
139*4882a593Smuzhiyun u32 pkt_id;
140*4882a593Smuzhiyun u16 rate_ctl;
141*4882a593Smuzhiyun u8 nss;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun txwi = skb_push(skb, sizeof(struct mt76_txwi));
144*4882a593Smuzhiyun memset(txwi, 0, sizeof(*txwi));
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (!wcid->tx_rate_set)
147*4882a593Smuzhiyun ieee80211_get_tx_rates(info->control.vif, sta, skb,
148*4882a593Smuzhiyun info->control.rates, 1);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
151*4882a593Smuzhiyun if (rate->idx < 0 || !rate->count)
152*4882a593Smuzhiyun rate_ctl = wcid->tx_rate;
153*4882a593Smuzhiyun else
154*4882a593Smuzhiyun rate_ctl = mt76_mac_tx_rate_val(dev, rate, &nss);
155*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
156*4882a593Smuzhiyun txwi->rate_ctl = cpu_to_le16(rate_ctl);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
159*4882a593Smuzhiyun txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
160*4882a593Smuzhiyun if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
161*4882a593Smuzhiyun txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
164*4882a593Smuzhiyun u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun ba_size <<= sta->ht_cap.ampdu_factor;
167*4882a593Smuzhiyun ba_size = min_t(int, 63, ba_size);
168*4882a593Smuzhiyun if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
169*4882a593Smuzhiyun ba_size = 0;
170*4882a593Smuzhiyun txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun txwi->flags =
173*4882a593Smuzhiyun cpu_to_le16(MT_TXWI_FLAGS_AMPDU |
174*4882a593Smuzhiyun FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY,
175*4882a593Smuzhiyun sta->ht_cap.ampdu_density));
176*4882a593Smuzhiyun if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
177*4882a593Smuzhiyun txwi->flags = 0;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun txwi->wcid = wcid->idx;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun is_probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
183*4882a593Smuzhiyun pkt_id = mt7601u_tx_pktid_enc(dev, rate_ctl & 0x7, is_probe);
184*4882a593Smuzhiyun pkt_len |= FIELD_PREP(MT_TXWI_LEN_PKTID, pkt_id);
185*4882a593Smuzhiyun txwi->len_ctl = cpu_to_le16(pkt_len);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return txwi;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
mt7601u_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)190*4882a593Smuzhiyun void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
191*4882a593Smuzhiyun struct sk_buff *skb)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
194*4882a593Smuzhiyun struct mt7601u_dev *dev = hw->priv;
195*4882a593Smuzhiyun struct ieee80211_vif *vif = info->control.vif;
196*4882a593Smuzhiyun struct ieee80211_sta *sta = control->sta;
197*4882a593Smuzhiyun struct mt76_sta *msta = NULL;
198*4882a593Smuzhiyun struct mt76_wcid *wcid = dev->mon_wcid;
199*4882a593Smuzhiyun struct mt76_txwi *txwi;
200*4882a593Smuzhiyun int pkt_len = skb->len;
201*4882a593Smuzhiyun int hw_q = skb2q(skb);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1);
204*4882a593Smuzhiyun info->status.status_driver_data[0] = (void *)(unsigned long)pkt_len;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (mt7601u_skb_rooms(dev, skb) || mt76_insert_hdr_pad(skb)) {
207*4882a593Smuzhiyun ieee80211_free_txskb(dev->hw, skb);
208*4882a593Smuzhiyun return;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (sta) {
212*4882a593Smuzhiyun msta = (struct mt76_sta *) sta->drv_priv;
213*4882a593Smuzhiyun wcid = &msta->wcid;
214*4882a593Smuzhiyun } else if (vif) {
215*4882a593Smuzhiyun struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun wcid = &mvif->group_wcid;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun txwi = mt7601u_push_txwi(dev, skb, sta, wcid, pkt_len);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (mt7601u_dma_enqueue_tx(dev, skb, wcid, hw_q))
223*4882a593Smuzhiyun return;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun trace_mt_tx(dev, skb, msta, txwi);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
mt7601u_tx_stat(struct work_struct * work)228*4882a593Smuzhiyun void mt7601u_tx_stat(struct work_struct *work)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
231*4882a593Smuzhiyun stat_work.work);
232*4882a593Smuzhiyun struct mt76_tx_status stat;
233*4882a593Smuzhiyun unsigned long flags;
234*4882a593Smuzhiyun int cleaned = 0;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun while (!test_bit(MT7601U_STATE_REMOVED, &dev->state)) {
237*4882a593Smuzhiyun stat = mt7601u_mac_fetch_tx_status(dev);
238*4882a593Smuzhiyun if (!stat.valid)
239*4882a593Smuzhiyun break;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun mt7601u_tx_pktid_dec(dev, &stat);
242*4882a593Smuzhiyun mt76_send_tx_status(dev, &stat);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun cleaned++;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun trace_mt_tx_status_cleaned(dev, cleaned);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun spin_lock_irqsave(&dev->tx_lock, flags);
249*4882a593Smuzhiyun if (cleaned)
250*4882a593Smuzhiyun queue_delayed_work(dev->stat_wq, &dev->stat_work,
251*4882a593Smuzhiyun msecs_to_jiffies(10));
252*4882a593Smuzhiyun else if (test_and_clear_bit(MT7601U_STATE_MORE_STATS, &dev->state))
253*4882a593Smuzhiyun queue_delayed_work(dev->stat_wq, &dev->stat_work,
254*4882a593Smuzhiyun msecs_to_jiffies(20));
255*4882a593Smuzhiyun else
256*4882a593Smuzhiyun clear_bit(MT7601U_STATE_READING_STATS, &dev->state);
257*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->tx_lock, flags);
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
mt7601u_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)260*4882a593Smuzhiyun int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
261*4882a593Smuzhiyun u16 queue, const struct ieee80211_tx_queue_params *params)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun struct mt7601u_dev *dev = hw->priv;
264*4882a593Smuzhiyun u8 cw_min = 5, cw_max = 10, hw_q = q2hwq(queue);
265*4882a593Smuzhiyun u32 val;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /* TODO: should we do funny things with the parameters?
268*4882a593Smuzhiyun * See what mt7601u_set_default_edca() used to do in init.c.
269*4882a593Smuzhiyun */
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun if (params->cw_min)
272*4882a593Smuzhiyun cw_min = fls(params->cw_min);
273*4882a593Smuzhiyun if (params->cw_max)
274*4882a593Smuzhiyun cw_max = fls(params->cw_max);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun WARN_ON(params->txop > 0xff);
277*4882a593Smuzhiyun WARN_ON(params->aifs > 0xf);
278*4882a593Smuzhiyun WARN_ON(cw_min > 0xf);
279*4882a593Smuzhiyun WARN_ON(cw_max > 0xf);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun val = FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) |
282*4882a593Smuzhiyun FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) |
283*4882a593Smuzhiyun FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max);
284*4882a593Smuzhiyun /* TODO: based on user-controlled EnableTxBurst var vendor drv sets
285*4882a593Smuzhiyun * a really long txop on AC0 (see connect.c:2009) but only on
286*4882a593Smuzhiyun * connect? When not connected should be 0.
287*4882a593Smuzhiyun */
288*4882a593Smuzhiyun if (!hw_q)
289*4882a593Smuzhiyun val |= 0x60;
290*4882a593Smuzhiyun else
291*4882a593Smuzhiyun val |= FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop);
292*4882a593Smuzhiyun mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_TXOP(hw_q));
295*4882a593Smuzhiyun val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q));
296*4882a593Smuzhiyun val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q);
297*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_TXOP(hw_q), val);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_AIFSN);
300*4882a593Smuzhiyun val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q));
301*4882a593Smuzhiyun val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q);
302*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_AIFSN, val);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_CWMIN);
305*4882a593Smuzhiyun val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q));
306*4882a593Smuzhiyun val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q);
307*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_CWMIN, val);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_CWMAX);
310*4882a593Smuzhiyun val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q));
311*4882a593Smuzhiyun val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q);
312*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_CWMAX, val);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun return 0;
315*4882a593Smuzhiyun }
316