xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt7601u/mcu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * (c) Copyright 2002-2010, Ralink Technology, Inc.
4*4882a593Smuzhiyun  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
5*4882a593Smuzhiyun  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/firmware.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/usb.h>
12*4882a593Smuzhiyun #include <linux/skbuff.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include "mt7601u.h"
15*4882a593Smuzhiyun #include "dma.h"
16*4882a593Smuzhiyun #include "mcu.h"
17*4882a593Smuzhiyun #include "usb.h"
18*4882a593Smuzhiyun #include "trace.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MCU_FW_URB_MAX_PAYLOAD		0x3800
21*4882a593Smuzhiyun #define MCU_FW_URB_SIZE			(MCU_FW_URB_MAX_PAYLOAD + 12)
22*4882a593Smuzhiyun #define MCU_RESP_URB_SIZE		1024
23*4882a593Smuzhiyun 
firmware_running(struct mt7601u_dev * dev)24*4882a593Smuzhiyun static inline int firmware_running(struct mt7601u_dev *dev)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	return mt7601u_rr(dev, MT_MCU_COM_REG0) == 1;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun 
skb_put_le32(struct sk_buff * skb,u32 val)29*4882a593Smuzhiyun static inline void skb_put_le32(struct sk_buff *skb, u32 val)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun 	put_unaligned_le32(val, skb_put(skb, 4));
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun 
mt7601u_dma_skb_wrap_cmd(struct sk_buff * skb,u8 seq,enum mcu_cmd cmd)34*4882a593Smuzhiyun static inline void mt7601u_dma_skb_wrap_cmd(struct sk_buff *skb,
35*4882a593Smuzhiyun 					    u8 seq, enum mcu_cmd cmd)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	WARN_ON(mt7601u_dma_skb_wrap(skb, CPU_TX_PORT, DMA_COMMAND,
38*4882a593Smuzhiyun 				     FIELD_PREP(MT_TXD_CMD_INFO_SEQ, seq) |
39*4882a593Smuzhiyun 				     FIELD_PREP(MT_TXD_CMD_INFO_TYPE, cmd)));
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun 
trace_mt_mcu_msg_send_cs(struct mt7601u_dev * dev,struct sk_buff * skb,bool need_resp)42*4882a593Smuzhiyun static inline void trace_mt_mcu_msg_send_cs(struct mt7601u_dev *dev,
43*4882a593Smuzhiyun 					    struct sk_buff *skb, bool need_resp)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	u32 i, csum = 0;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	for (i = 0; i < skb->len / 4; i++)
48*4882a593Smuzhiyun 		csum ^= get_unaligned_le32(skb->data + i * 4);
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	trace_mt_mcu_msg_send(dev, skb, csum, need_resp);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
mt7601u_mcu_msg_alloc(const void * data,int len)53*4882a593Smuzhiyun static struct sk_buff *mt7601u_mcu_msg_alloc(const void *data, int len)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct sk_buff *skb;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	WARN_ON(len % 4); /* if length is not divisible by 4 we need to pad */
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	skb = alloc_skb(len + MT_DMA_HDR_LEN + 4, GFP_KERNEL);
60*4882a593Smuzhiyun 	if (skb) {
61*4882a593Smuzhiyun 		skb_reserve(skb, MT_DMA_HDR_LEN);
62*4882a593Smuzhiyun 		skb_put_data(skb, data, len);
63*4882a593Smuzhiyun 	}
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	return skb;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
mt7601u_mcu_wait_resp(struct mt7601u_dev * dev,u8 seq)68*4882a593Smuzhiyun static int mt7601u_mcu_wait_resp(struct mt7601u_dev *dev, u8 seq)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	struct urb *urb = dev->mcu.resp.urb;
71*4882a593Smuzhiyun 	u32 rxfce;
72*4882a593Smuzhiyun 	int urb_status, ret, i = 5;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	while (i--) {
75*4882a593Smuzhiyun 		if (!wait_for_completion_timeout(&dev->mcu.resp_cmpl,
76*4882a593Smuzhiyun 						 msecs_to_jiffies(300))) {
77*4882a593Smuzhiyun 			dev_warn(dev->dev, "Warning: %s retrying\n", __func__);
78*4882a593Smuzhiyun 			continue;
79*4882a593Smuzhiyun 		}
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 		/* Make copies of important data before reusing the urb */
82*4882a593Smuzhiyun 		rxfce = get_unaligned_le32(dev->mcu.resp.buf);
83*4882a593Smuzhiyun 		urb_status = urb->status * mt7601u_urb_has_error(urb);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 		ret = mt7601u_usb_submit_buf(dev, USB_DIR_IN, MT_EP_IN_CMD_RESP,
86*4882a593Smuzhiyun 					     &dev->mcu.resp, GFP_KERNEL,
87*4882a593Smuzhiyun 					     mt7601u_complete_urb,
88*4882a593Smuzhiyun 					     &dev->mcu.resp_cmpl);
89*4882a593Smuzhiyun 		if (ret)
90*4882a593Smuzhiyun 			return ret;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 		if (urb_status)
93*4882a593Smuzhiyun 			dev_err(dev->dev, "Error: MCU resp urb failed:%d\n",
94*4882a593Smuzhiyun 				urb_status);
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 		if (FIELD_GET(MT_RXD_CMD_INFO_CMD_SEQ, rxfce) == seq &&
97*4882a593Smuzhiyun 		    FIELD_GET(MT_RXD_CMD_INFO_EVT_TYPE, rxfce) == CMD_DONE)
98*4882a593Smuzhiyun 			return 0;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 		dev_err(dev->dev, "Error: MCU resp evt:%lx seq:%hhx-%lx!\n",
101*4882a593Smuzhiyun 			FIELD_GET(MT_RXD_CMD_INFO_EVT_TYPE, rxfce),
102*4882a593Smuzhiyun 			seq, FIELD_GET(MT_RXD_CMD_INFO_CMD_SEQ, rxfce));
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	dev_err(dev->dev, "Error: %s timed out\n", __func__);
106*4882a593Smuzhiyun 	return -ETIMEDOUT;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun static int
mt7601u_mcu_msg_send(struct mt7601u_dev * dev,struct sk_buff * skb,enum mcu_cmd cmd,bool wait_resp)110*4882a593Smuzhiyun mt7601u_mcu_msg_send(struct mt7601u_dev *dev, struct sk_buff *skb,
111*4882a593Smuzhiyun 		     enum mcu_cmd cmd, bool wait_resp)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	struct usb_device *usb_dev = mt7601u_to_usb_dev(dev);
114*4882a593Smuzhiyun 	unsigned cmd_pipe = usb_sndbulkpipe(usb_dev,
115*4882a593Smuzhiyun 					    dev->out_eps[MT_EP_OUT_INBAND_CMD]);
116*4882a593Smuzhiyun 	int sent, ret;
117*4882a593Smuzhiyun 	u8 seq = 0;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) {
120*4882a593Smuzhiyun 		consume_skb(skb);
121*4882a593Smuzhiyun 		return 0;
122*4882a593Smuzhiyun 	}
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	mutex_lock(&dev->mcu.mutex);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	if (wait_resp)
127*4882a593Smuzhiyun 		while (!seq)
128*4882a593Smuzhiyun 			seq = ++dev->mcu.msg_seq & 0xf;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	mt7601u_dma_skb_wrap_cmd(skb, seq, cmd);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	if (dev->mcu.resp_cmpl.done)
133*4882a593Smuzhiyun 		dev_err(dev->dev, "Error: MCU response pre-completed!\n");
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	trace_mt_mcu_msg_send_cs(dev, skb, wait_resp);
136*4882a593Smuzhiyun 	trace_mt_submit_urb_sync(dev, cmd_pipe, skb->len);
137*4882a593Smuzhiyun 	ret = usb_bulk_msg(usb_dev, cmd_pipe, skb->data, skb->len, &sent, 500);
138*4882a593Smuzhiyun 	if (ret) {
139*4882a593Smuzhiyun 		dev_err(dev->dev, "Error: send MCU cmd failed:%d\n", ret);
140*4882a593Smuzhiyun 		goto out;
141*4882a593Smuzhiyun 	}
142*4882a593Smuzhiyun 	if (sent != skb->len)
143*4882a593Smuzhiyun 		dev_err(dev->dev, "Error: %s sent != skb->len\n", __func__);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	if (wait_resp)
146*4882a593Smuzhiyun 		ret = mt7601u_mcu_wait_resp(dev, seq);
147*4882a593Smuzhiyun out:
148*4882a593Smuzhiyun 	mutex_unlock(&dev->mcu.mutex);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	consume_skb(skb);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	return ret;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
mt7601u_mcu_function_select(struct mt7601u_dev * dev,enum mcu_function func,u32 val)155*4882a593Smuzhiyun static int mt7601u_mcu_function_select(struct mt7601u_dev *dev,
156*4882a593Smuzhiyun 				       enum mcu_function func, u32 val)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	struct sk_buff *skb;
159*4882a593Smuzhiyun 	struct {
160*4882a593Smuzhiyun 		__le32 id;
161*4882a593Smuzhiyun 		__le32 value;
162*4882a593Smuzhiyun 	} __packed __aligned(4) msg = {
163*4882a593Smuzhiyun 		.id = cpu_to_le32(func),
164*4882a593Smuzhiyun 		.value = cpu_to_le32(val),
165*4882a593Smuzhiyun 	};
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	skb = mt7601u_mcu_msg_alloc(&msg, sizeof(msg));
168*4882a593Smuzhiyun 	if (!skb)
169*4882a593Smuzhiyun 		return -ENOMEM;
170*4882a593Smuzhiyun 	return mt7601u_mcu_msg_send(dev, skb, CMD_FUN_SET_OP, func == 5);
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
mt7601u_mcu_tssi_read_kick(struct mt7601u_dev * dev,int use_hvga)173*4882a593Smuzhiyun int mt7601u_mcu_tssi_read_kick(struct mt7601u_dev *dev, int use_hvga)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	int ret;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (!test_bit(MT7601U_STATE_MCU_RUNNING, &dev->state))
178*4882a593Smuzhiyun 		return 0;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ret = mt7601u_mcu_function_select(dev, ATOMIC_TSSI_SETTING,
181*4882a593Smuzhiyun 					  use_hvga);
182*4882a593Smuzhiyun 	if (ret) {
183*4882a593Smuzhiyun 		dev_warn(dev->dev, "Warning: MCU TSSI read kick failed\n");
184*4882a593Smuzhiyun 		return ret;
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	dev->tssi_read_trig = true;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun int
mt7601u_mcu_calibrate(struct mt7601u_dev * dev,enum mcu_calibrate cal,u32 val)193*4882a593Smuzhiyun mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct sk_buff *skb;
196*4882a593Smuzhiyun 	struct {
197*4882a593Smuzhiyun 		__le32 id;
198*4882a593Smuzhiyun 		__le32 value;
199*4882a593Smuzhiyun 	} __packed __aligned(4) msg = {
200*4882a593Smuzhiyun 		.id = cpu_to_le32(cal),
201*4882a593Smuzhiyun 		.value = cpu_to_le32(val),
202*4882a593Smuzhiyun 	};
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	skb = mt7601u_mcu_msg_alloc(&msg, sizeof(msg));
205*4882a593Smuzhiyun 	if (!skb)
206*4882a593Smuzhiyun 		return -ENOMEM;
207*4882a593Smuzhiyun 	return mt7601u_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP, true);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
mt7601u_write_reg_pairs(struct mt7601u_dev * dev,u32 base,const struct mt76_reg_pair * data,int n)210*4882a593Smuzhiyun int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base,
211*4882a593Smuzhiyun 			    const struct mt76_reg_pair *data, int n)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	const int max_vals_per_cmd = INBAND_PACKET_MAX_LEN / 8;
214*4882a593Smuzhiyun 	struct sk_buff *skb;
215*4882a593Smuzhiyun 	int cnt, i, ret;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	if (!n)
218*4882a593Smuzhiyun 		return 0;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	cnt = min(max_vals_per_cmd, n);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	skb = alloc_skb(cnt * 8 + MT_DMA_HDR_LEN + 4, GFP_KERNEL);
223*4882a593Smuzhiyun 	if (!skb)
224*4882a593Smuzhiyun 		return -ENOMEM;
225*4882a593Smuzhiyun 	skb_reserve(skb, MT_DMA_HDR_LEN);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	for (i = 0; i < cnt; i++) {
228*4882a593Smuzhiyun 		skb_put_le32(skb, base + data[i].reg);
229*4882a593Smuzhiyun 		skb_put_le32(skb, data[i].value);
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	ret = mt7601u_mcu_msg_send(dev, skb, CMD_RANDOM_WRITE, cnt == n);
233*4882a593Smuzhiyun 	if (ret)
234*4882a593Smuzhiyun 		return ret;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	return mt7601u_write_reg_pairs(dev, base, data + cnt, n - cnt);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
mt7601u_burst_write_regs(struct mt7601u_dev * dev,u32 offset,const u32 * data,int n)239*4882a593Smuzhiyun int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset,
240*4882a593Smuzhiyun 			     const u32 *data, int n)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	const int max_regs_per_cmd = INBAND_PACKET_MAX_LEN / 4 - 1;
243*4882a593Smuzhiyun 	struct sk_buff *skb;
244*4882a593Smuzhiyun 	int cnt, i, ret;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	if (!n)
247*4882a593Smuzhiyun 		return 0;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	cnt = min(max_regs_per_cmd, n);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	skb = alloc_skb(cnt * 4 + MT_DMA_HDR_LEN + 4, GFP_KERNEL);
252*4882a593Smuzhiyun 	if (!skb)
253*4882a593Smuzhiyun 		return -ENOMEM;
254*4882a593Smuzhiyun 	skb_reserve(skb, MT_DMA_HDR_LEN);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	skb_put_le32(skb, MT_MCU_MEMMAP_WLAN + offset);
257*4882a593Smuzhiyun 	for (i = 0; i < cnt; i++)
258*4882a593Smuzhiyun 		skb_put_le32(skb, data[i]);
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	ret = mt7601u_mcu_msg_send(dev, skb, CMD_BURST_WRITE, cnt == n);
261*4882a593Smuzhiyun 	if (ret)
262*4882a593Smuzhiyun 		return ret;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	return mt7601u_burst_write_regs(dev, offset + cnt * 4,
265*4882a593Smuzhiyun 					data + cnt, n - cnt);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun struct mt76_fw_header {
269*4882a593Smuzhiyun 	__le32 ilm_len;
270*4882a593Smuzhiyun 	__le32 dlm_len;
271*4882a593Smuzhiyun 	__le16 build_ver;
272*4882a593Smuzhiyun 	__le16 fw_ver;
273*4882a593Smuzhiyun 	u8 pad[4];
274*4882a593Smuzhiyun 	char build_time[16];
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun struct mt76_fw {
278*4882a593Smuzhiyun 	struct mt76_fw_header hdr;
279*4882a593Smuzhiyun 	u8 ivb[MT_MCU_IVB_SIZE];
280*4882a593Smuzhiyun 	u8 ilm[];
281*4882a593Smuzhiyun };
282*4882a593Smuzhiyun 
__mt7601u_dma_fw(struct mt7601u_dev * dev,const struct mt7601u_dma_buf * dma_buf,const void * data,u32 len,u32 dst_addr)283*4882a593Smuzhiyun static int __mt7601u_dma_fw(struct mt7601u_dev *dev,
284*4882a593Smuzhiyun 			    const struct mt7601u_dma_buf *dma_buf,
285*4882a593Smuzhiyun 			    const void *data, u32 len, u32 dst_addr)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun 	DECLARE_COMPLETION_ONSTACK(cmpl);
288*4882a593Smuzhiyun 	struct mt7601u_dma_buf buf = *dma_buf; /* we need to fake length */
289*4882a593Smuzhiyun 	__le32 reg;
290*4882a593Smuzhiyun 	u32 val;
291*4882a593Smuzhiyun 	int ret;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	reg = cpu_to_le32(FIELD_PREP(MT_TXD_INFO_TYPE, DMA_PACKET) |
294*4882a593Smuzhiyun 			  FIELD_PREP(MT_TXD_INFO_D_PORT, CPU_TX_PORT) |
295*4882a593Smuzhiyun 			  FIELD_PREP(MT_TXD_INFO_LEN, len));
296*4882a593Smuzhiyun 	memcpy(buf.buf, &reg, sizeof(reg));
297*4882a593Smuzhiyun 	memcpy(buf.buf + sizeof(reg), data, len);
298*4882a593Smuzhiyun 	memset(buf.buf + sizeof(reg) + len, 0, 8);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	ret = mt7601u_vendor_single_wr(dev, MT_VEND_WRITE_FCE,
301*4882a593Smuzhiyun 				       MT_FCE_DMA_ADDR, dst_addr);
302*4882a593Smuzhiyun 	if (ret)
303*4882a593Smuzhiyun 		return ret;
304*4882a593Smuzhiyun 	len = roundup(len, 4);
305*4882a593Smuzhiyun 	ret = mt7601u_vendor_single_wr(dev, MT_VEND_WRITE_FCE,
306*4882a593Smuzhiyun 				       MT_FCE_DMA_LEN, len << 16);
307*4882a593Smuzhiyun 	if (ret)
308*4882a593Smuzhiyun 		return ret;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	buf.len = MT_DMA_HDR_LEN + len + 4;
311*4882a593Smuzhiyun 	ret = mt7601u_usb_submit_buf(dev, USB_DIR_OUT, MT_EP_OUT_INBAND_CMD,
312*4882a593Smuzhiyun 				     &buf, GFP_KERNEL,
313*4882a593Smuzhiyun 				     mt7601u_complete_urb, &cmpl);
314*4882a593Smuzhiyun 	if (ret)
315*4882a593Smuzhiyun 		return ret;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	if (!wait_for_completion_timeout(&cmpl, msecs_to_jiffies(1000))) {
318*4882a593Smuzhiyun 		dev_err(dev->dev, "Error: firmware upload timed out\n");
319*4882a593Smuzhiyun 		usb_kill_urb(buf.urb);
320*4882a593Smuzhiyun 		return -ETIMEDOUT;
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 	if (mt7601u_urb_has_error(buf.urb)) {
323*4882a593Smuzhiyun 		dev_err(dev->dev, "Error: firmware upload urb failed:%d\n",
324*4882a593Smuzhiyun 			buf.urb->status);
325*4882a593Smuzhiyun 		return buf.urb->status;
326*4882a593Smuzhiyun 	}
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX);
329*4882a593Smuzhiyun 	val++;
330*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val);
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	return 0;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun static int
mt7601u_dma_fw(struct mt7601u_dev * dev,struct mt7601u_dma_buf * dma_buf,const void * data,int len,u32 dst_addr)336*4882a593Smuzhiyun mt7601u_dma_fw(struct mt7601u_dev *dev, struct mt7601u_dma_buf *dma_buf,
337*4882a593Smuzhiyun 	       const void *data, int len, u32 dst_addr)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun 	int n, ret;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	if (len == 0)
342*4882a593Smuzhiyun 		return 0;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	n = min(MCU_FW_URB_MAX_PAYLOAD, len);
345*4882a593Smuzhiyun 	ret = __mt7601u_dma_fw(dev, dma_buf, data, n, dst_addr);
346*4882a593Smuzhiyun 	if (ret)
347*4882a593Smuzhiyun 		return ret;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	if (!mt76_poll_msec(dev, MT_MCU_COM_REG1, BIT(31), BIT(31), 500))
350*4882a593Smuzhiyun 		return -ETIMEDOUT;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	return mt7601u_dma_fw(dev, dma_buf, data + n, len - n, dst_addr + n);
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static int
mt7601u_upload_firmware(struct mt7601u_dev * dev,const struct mt76_fw * fw)356*4882a593Smuzhiyun mt7601u_upload_firmware(struct mt7601u_dev *dev, const struct mt76_fw *fw)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct mt7601u_dma_buf dma_buf;
359*4882a593Smuzhiyun 	void *ivb;
360*4882a593Smuzhiyun 	u32 ilm_len, dlm_len;
361*4882a593Smuzhiyun 	int i, ret;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	ivb = kmemdup(fw->ivb, sizeof(fw->ivb), GFP_KERNEL);
364*4882a593Smuzhiyun 	if (!ivb)
365*4882a593Smuzhiyun 		return -ENOMEM;
366*4882a593Smuzhiyun 	if (mt7601u_usb_alloc_buf(dev, MCU_FW_URB_SIZE, &dma_buf)) {
367*4882a593Smuzhiyun 		ret = -ENOMEM;
368*4882a593Smuzhiyun 		goto error;
369*4882a593Smuzhiyun 	}
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	ilm_len = le32_to_cpu(fw->hdr.ilm_len) - sizeof(fw->ivb);
372*4882a593Smuzhiyun 	dev_dbg(dev->dev, "loading FW - ILM %u + IVB %zu\n",
373*4882a593Smuzhiyun 		ilm_len, sizeof(fw->ivb));
374*4882a593Smuzhiyun 	ret = mt7601u_dma_fw(dev, &dma_buf, fw->ilm, ilm_len, sizeof(fw->ivb));
375*4882a593Smuzhiyun 	if (ret)
376*4882a593Smuzhiyun 		goto error;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	dlm_len = le32_to_cpu(fw->hdr.dlm_len);
379*4882a593Smuzhiyun 	dev_dbg(dev->dev, "loading FW - DLM %u\n", dlm_len);
380*4882a593Smuzhiyun 	ret = mt7601u_dma_fw(dev, &dma_buf, fw->ilm + ilm_len,
381*4882a593Smuzhiyun 			     dlm_len, MT_MCU_DLM_OFFSET);
382*4882a593Smuzhiyun 	if (ret)
383*4882a593Smuzhiyun 		goto error;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	ret = mt7601u_vendor_request(dev, MT_VEND_DEV_MODE, USB_DIR_OUT,
386*4882a593Smuzhiyun 				     0x12, 0, ivb, sizeof(fw->ivb));
387*4882a593Smuzhiyun 	if (ret < 0)
388*4882a593Smuzhiyun 		goto error;
389*4882a593Smuzhiyun 	ret = 0;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	for (i = 100; i && !firmware_running(dev); i--)
392*4882a593Smuzhiyun 		msleep(10);
393*4882a593Smuzhiyun 	if (!i) {
394*4882a593Smuzhiyun 		ret = -ETIMEDOUT;
395*4882a593Smuzhiyun 		goto error;
396*4882a593Smuzhiyun 	}
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	dev_dbg(dev->dev, "Firmware running!\n");
399*4882a593Smuzhiyun error:
400*4882a593Smuzhiyun 	kfree(ivb);
401*4882a593Smuzhiyun 	mt7601u_usb_free_buf(dev, &dma_buf);
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	return ret;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun 
mt7601u_load_firmware(struct mt7601u_dev * dev)406*4882a593Smuzhiyun static int mt7601u_load_firmware(struct mt7601u_dev *dev)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	const struct firmware *fw;
409*4882a593Smuzhiyun 	const struct mt76_fw_header *hdr;
410*4882a593Smuzhiyun 	int len, ret;
411*4882a593Smuzhiyun 	u32 val;
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN |
414*4882a593Smuzhiyun 					 MT_USB_DMA_CFG_TX_BULK_EN));
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	if (firmware_running(dev))
417*4882a593Smuzhiyun 		return firmware_request_cache(dev->dev, MT7601U_FIRMWARE);
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret = request_firmware(&fw, MT7601U_FIRMWARE, dev->dev);
420*4882a593Smuzhiyun 	if (ret)
421*4882a593Smuzhiyun 		return ret;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	if (!fw || !fw->data || fw->size < sizeof(*hdr))
424*4882a593Smuzhiyun 		goto err_inv_fw;
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	hdr = (const struct mt76_fw_header *) fw->data;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	if (le32_to_cpu(hdr->ilm_len) <= MT_MCU_IVB_SIZE)
429*4882a593Smuzhiyun 		goto err_inv_fw;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	len = sizeof(*hdr);
432*4882a593Smuzhiyun 	len += le32_to_cpu(hdr->ilm_len);
433*4882a593Smuzhiyun 	len += le32_to_cpu(hdr->dlm_len);
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	if (fw->size != len)
436*4882a593Smuzhiyun 		goto err_inv_fw;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	val = le16_to_cpu(hdr->fw_ver);
439*4882a593Smuzhiyun 	dev_info(dev->dev,
440*4882a593Smuzhiyun 		 "Firmware Version: %d.%d.%02d Build: %x Build time: %.16s\n",
441*4882a593Smuzhiyun 		 (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf,
442*4882a593Smuzhiyun 		 le16_to_cpu(hdr->build_ver), hdr->build_time);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	len = le32_to_cpu(hdr->ilm_len);
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	mt7601u_wr(dev, 0x94c, 0);
447*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_FCE_PSE_CTRL, 0);
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	mt7601u_vendor_reset(dev);
450*4882a593Smuzhiyun 	msleep(5);
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	mt7601u_wr(dev, 0xa44, 0);
453*4882a593Smuzhiyun 	mt7601u_wr(dev, 0x230, 0x84210);
454*4882a593Smuzhiyun 	mt7601u_wr(dev, 0x400, 0x80c00);
455*4882a593Smuzhiyun 	mt7601u_wr(dev, 0x800, 1);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	mt7601u_rmw(dev, MT_PBF_CFG, 0, (MT_PBF_CFG_TX0Q_EN |
458*4882a593Smuzhiyun 					 MT_PBF_CFG_TX1Q_EN |
459*4882a593Smuzhiyun 					 MT_PBF_CFG_TX2Q_EN |
460*4882a593Smuzhiyun 					 MT_PBF_CFG_TX3Q_EN));
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_FCE_PSE_CTRL, 1);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN |
465*4882a593Smuzhiyun 					 MT_USB_DMA_CFG_TX_BULK_EN));
466*4882a593Smuzhiyun 	val = mt76_set(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_CLR);
467*4882a593Smuzhiyun 	val &= ~MT_USB_DMA_CFG_TX_CLR;
468*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_USB_DMA_CFG, val);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	/* FCE tx_fs_base_ptr */
471*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230);
472*4882a593Smuzhiyun 	/* FCE tx_fs_max_cnt */
473*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_MAX_COUNT, 1);
474*4882a593Smuzhiyun 	/* FCE pdma enable */
475*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44);
476*4882a593Smuzhiyun 	/* FCE skip_fs_en */
477*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_FCE_SKIP_FS, 3);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	ret = mt7601u_upload_firmware(dev, (const struct mt76_fw *)fw->data);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	release_firmware(fw);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	return ret;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun err_inv_fw:
486*4882a593Smuzhiyun 	dev_err(dev->dev, "Invalid firmware image\n");
487*4882a593Smuzhiyun 	release_firmware(fw);
488*4882a593Smuzhiyun 	return -ENOENT;
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun 
mt7601u_mcu_init(struct mt7601u_dev * dev)491*4882a593Smuzhiyun int mt7601u_mcu_init(struct mt7601u_dev *dev)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun 	int ret;
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	mutex_init(&dev->mcu.mutex);
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	ret = mt7601u_load_firmware(dev);
498*4882a593Smuzhiyun 	if (ret)
499*4882a593Smuzhiyun 		return ret;
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	set_bit(MT7601U_STATE_MCU_RUNNING, &dev->state);
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	return 0;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun 
mt7601u_mcu_cmd_init(struct mt7601u_dev * dev)506*4882a593Smuzhiyun int mt7601u_mcu_cmd_init(struct mt7601u_dev *dev)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun 	int ret;
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	ret = mt7601u_mcu_function_select(dev, Q_SELECT, 1);
511*4882a593Smuzhiyun 	if (ret)
512*4882a593Smuzhiyun 		return ret;
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	init_completion(&dev->mcu.resp_cmpl);
515*4882a593Smuzhiyun 	if (mt7601u_usb_alloc_buf(dev, MCU_RESP_URB_SIZE, &dev->mcu.resp)) {
516*4882a593Smuzhiyun 		mt7601u_usb_free_buf(dev, &dev->mcu.resp);
517*4882a593Smuzhiyun 		return -ENOMEM;
518*4882a593Smuzhiyun 	}
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	ret = mt7601u_usb_submit_buf(dev, USB_DIR_IN, MT_EP_IN_CMD_RESP,
521*4882a593Smuzhiyun 				     &dev->mcu.resp, GFP_KERNEL,
522*4882a593Smuzhiyun 				     mt7601u_complete_urb, &dev->mcu.resp_cmpl);
523*4882a593Smuzhiyun 	if (ret) {
524*4882a593Smuzhiyun 		mt7601u_usb_free_buf(dev, &dev->mcu.resp);
525*4882a593Smuzhiyun 		return ret;
526*4882a593Smuzhiyun 	}
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	return 0;
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
mt7601u_mcu_cmd_deinit(struct mt7601u_dev * dev)531*4882a593Smuzhiyun void mt7601u_mcu_cmd_deinit(struct mt7601u_dev *dev)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	usb_kill_urb(dev->mcu.resp.urb);
534*4882a593Smuzhiyun 	mt7601u_usb_free_buf(dev, &dev->mcu.resp);
535*4882a593Smuzhiyun }
536