1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4*4882a593Smuzhiyun * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MT76_MAC_H 8*4882a593Smuzhiyun #define __MT76_MAC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct mt76_tx_status { 11*4882a593Smuzhiyun u8 valid:1; 12*4882a593Smuzhiyun u8 success:1; 13*4882a593Smuzhiyun u8 aggr:1; 14*4882a593Smuzhiyun u8 ack_req:1; 15*4882a593Smuzhiyun u8 is_probe:1; 16*4882a593Smuzhiyun u8 wcid; 17*4882a593Smuzhiyun u8 pktid; 18*4882a593Smuzhiyun u8 retry; 19*4882a593Smuzhiyun u16 rate; 20*4882a593Smuzhiyun } __packed __aligned(2); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Note: values in original "RSSI" and "SNR" fields are not actually what they 23*4882a593Smuzhiyun * are called for MT7601U, names used by this driver are educated guesses 24*4882a593Smuzhiyun * (see vendor mac/ral_omac.c). 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun struct mt7601u_rxwi { 27*4882a593Smuzhiyun __le32 rxinfo; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun __le32 ctl; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun __le16 frag_sn; 32*4882a593Smuzhiyun __le16 rate; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun u8 unknown; 35*4882a593Smuzhiyun u8 zero[3]; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun u8 snr; 38*4882a593Smuzhiyun u8 ant; 39*4882a593Smuzhiyun u8 gain; 40*4882a593Smuzhiyun u8 freq_off; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun __le32 resv2; 43*4882a593Smuzhiyun __le32 expert_ant; 44*4882a593Smuzhiyun } __packed __aligned(4); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define MT_RXINFO_BA BIT(0) 47*4882a593Smuzhiyun #define MT_RXINFO_DATA BIT(1) 48*4882a593Smuzhiyun #define MT_RXINFO_NULL BIT(2) 49*4882a593Smuzhiyun #define MT_RXINFO_FRAG BIT(3) 50*4882a593Smuzhiyun #define MT_RXINFO_U2M BIT(4) 51*4882a593Smuzhiyun #define MT_RXINFO_MULTICAST BIT(5) 52*4882a593Smuzhiyun #define MT_RXINFO_BROADCAST BIT(6) 53*4882a593Smuzhiyun #define MT_RXINFO_MYBSS BIT(7) 54*4882a593Smuzhiyun #define MT_RXINFO_CRCERR BIT(8) 55*4882a593Smuzhiyun #define MT_RXINFO_ICVERR BIT(9) 56*4882a593Smuzhiyun #define MT_RXINFO_MICERR BIT(10) 57*4882a593Smuzhiyun #define MT_RXINFO_AMSDU BIT(11) 58*4882a593Smuzhiyun #define MT_RXINFO_HTC BIT(12) 59*4882a593Smuzhiyun #define MT_RXINFO_RSSI BIT(13) 60*4882a593Smuzhiyun #define MT_RXINFO_L2PAD BIT(14) 61*4882a593Smuzhiyun #define MT_RXINFO_AMPDU BIT(15) 62*4882a593Smuzhiyun #define MT_RXINFO_DECRYPT BIT(16) 63*4882a593Smuzhiyun #define MT_RXINFO_BSSIDX3 BIT(17) 64*4882a593Smuzhiyun #define MT_RXINFO_WAPI_KEY BIT(18) 65*4882a593Smuzhiyun #define MT_RXINFO_PN_LEN GENMASK(21, 19) 66*4882a593Smuzhiyun #define MT_RXINFO_SW_PKT_80211 BIT(22) 67*4882a593Smuzhiyun #define MT_RXINFO_TCP_SUM_BYPASS BIT(28) 68*4882a593Smuzhiyun #define MT_RXINFO_IP_SUM_BYPASS BIT(29) 69*4882a593Smuzhiyun #define MT_RXINFO_TCP_SUM_ERR BIT(30) 70*4882a593Smuzhiyun #define MT_RXINFO_IP_SUM_ERR BIT(31) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MT_RXWI_CTL_WCID GENMASK(7, 0) 73*4882a593Smuzhiyun #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) 74*4882a593Smuzhiyun #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) 75*4882a593Smuzhiyun #define MT_RXWI_CTL_UDF GENMASK(15, 13) 76*4882a593Smuzhiyun #define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16) 77*4882a593Smuzhiyun #define MT_RXWI_CTL_TID GENMASK(31, 28) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define MT_RXWI_FRAG GENMASK(3, 0) 80*4882a593Smuzhiyun #define MT_RXWI_SN GENMASK(15, 4) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define MT_RXWI_RATE_MCS GENMASK(6, 0) 83*4882a593Smuzhiyun #define MT_RXWI_RATE_BW BIT(7) 84*4882a593Smuzhiyun #define MT_RXWI_RATE_SGI BIT(8) 85*4882a593Smuzhiyun #define MT_RXWI_RATE_STBC GENMASK(10, 9) 86*4882a593Smuzhiyun #define MT_RXWI_RATE_ETXBF BIT(11) 87*4882a593Smuzhiyun #define MT_RXWI_RATE_SND BIT(12) 88*4882a593Smuzhiyun #define MT_RXWI_RATE_ITXBF BIT(13) 89*4882a593Smuzhiyun #define MT_RXWI_RATE_PHY GENMASK(15, 14) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0) 92*4882a593Smuzhiyun #define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6) 93*4882a593Smuzhiyun #define MT_RXWI_ANT_AUX_LNA BIT(7) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun enum mt76_phy_type { 98*4882a593Smuzhiyun MT_PHY_TYPE_CCK, 99*4882a593Smuzhiyun MT_PHY_TYPE_OFDM, 100*4882a593Smuzhiyun MT_PHY_TYPE_HT, 101*4882a593Smuzhiyun MT_PHY_TYPE_HT_GF, 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun enum mt76_phy_bandwidth { 105*4882a593Smuzhiyun MT_PHY_BW_20, 106*4882a593Smuzhiyun MT_PHY_BW_40, 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun struct mt76_txwi { 110*4882a593Smuzhiyun __le16 flags; 111*4882a593Smuzhiyun __le16 rate_ctl; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun u8 ack_ctl; 114*4882a593Smuzhiyun u8 wcid; 115*4882a593Smuzhiyun __le16 len_ctl; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun __le32 iv; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun __le32 eiv; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun u8 aid; 122*4882a593Smuzhiyun u8 txstream; 123*4882a593Smuzhiyun __le16 ctl; 124*4882a593Smuzhiyun } __packed __aligned(4); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define MT_TXWI_FLAGS_FRAG BIT(0) 127*4882a593Smuzhiyun #define MT_TXWI_FLAGS_MMPS BIT(1) 128*4882a593Smuzhiyun #define MT_TXWI_FLAGS_CFACK BIT(2) 129*4882a593Smuzhiyun #define MT_TXWI_FLAGS_TS BIT(3) 130*4882a593Smuzhiyun #define MT_TXWI_FLAGS_AMPDU BIT(4) 131*4882a593Smuzhiyun #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) 132*4882a593Smuzhiyun #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) 133*4882a593Smuzhiyun #define MT_TXWI_FLAGS_CWMIN GENMASK(12, 10) 134*4882a593Smuzhiyun #define MT_TXWI_FLAGS_NO_RATE_FALLBACK BIT(13) 135*4882a593Smuzhiyun #define MT_TXWI_FLAGS_TX_RPT BIT(14) 136*4882a593Smuzhiyun #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define MT_TXWI_RATE_MCS GENMASK(6, 0) 139*4882a593Smuzhiyun #define MT_TXWI_RATE_BW BIT(7) 140*4882a593Smuzhiyun #define MT_TXWI_RATE_SGI BIT(8) 141*4882a593Smuzhiyun #define MT_TXWI_RATE_STBC GENMASK(10, 9) 142*4882a593Smuzhiyun #define MT_TXWI_RATE_PHY_MODE GENMASK(15, 14) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define MT_TXWI_ACK_CTL_REQ BIT(0) 145*4882a593Smuzhiyun #define MT_TXWI_ACK_CTL_NSEQ BIT(1) 146*4882a593Smuzhiyun #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define MT_TXWI_LEN_BYTE_CNT GENMASK(11, 0) 149*4882a593Smuzhiyun #define MT_TXWI_LEN_PKTID GENMASK(15, 12) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define MT_TXWI_CTL_TX_POWER_ADJ GENMASK(3, 0) 152*4882a593Smuzhiyun #define MT_TXWI_CTL_CHAN_CHECK_PKT BIT(4) 153*4882a593Smuzhiyun #define MT_TXWI_CTL_PIFS_REV BIT(6) 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, 156*4882a593Smuzhiyun u8 *data, void *rxi); 157*4882a593Smuzhiyun int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, 158*4882a593Smuzhiyun struct ieee80211_key_conf *key); 159*4882a593Smuzhiyun void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid, 160*4882a593Smuzhiyun const struct ieee80211_tx_rate *rate); 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx, 163*4882a593Smuzhiyun struct ieee80211_key_conf *key); 164*4882a593Smuzhiyun u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, 165*4882a593Smuzhiyun const struct ieee80211_tx_rate *rate, u8 *nss_val); 166*4882a593Smuzhiyun struct mt76_tx_status 167*4882a593Smuzhiyun mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev); 168*4882a593Smuzhiyun void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat); 169*4882a593Smuzhiyun void mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *addr); 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #endif 172