xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt7601u/mac.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4*4882a593Smuzhiyun  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include "mt7601u.h"
8*4882a593Smuzhiyun #include "trace.h"
9*4882a593Smuzhiyun #include <linux/etherdevice.h>
10*4882a593Smuzhiyun 
mt7601u_set_macaddr(struct mt7601u_dev * dev,const u8 * addr)11*4882a593Smuzhiyun void mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *addr)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun 	ether_addr_copy(dev->macaddr, addr);
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun 	if (!is_valid_ether_addr(dev->macaddr)) {
16*4882a593Smuzhiyun 		eth_random_addr(dev->macaddr);
17*4882a593Smuzhiyun 		dev_info(dev->dev,
18*4882a593Smuzhiyun 			 "Invalid MAC address, using random address %pM\n",
19*4882a593Smuzhiyun 			 dev->macaddr);
20*4882a593Smuzhiyun 	}
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 	mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
23*4882a593Smuzhiyun 	mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4) |
24*4882a593Smuzhiyun 		FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static void
mt76_mac_process_tx_rate(struct ieee80211_tx_rate * txrate,u16 rate)28*4882a593Smuzhiyun mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	u8 idx = FIELD_GET(MT_TXWI_RATE_MCS, rate);
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	txrate->idx = 0;
33*4882a593Smuzhiyun 	txrate->flags = 0;
34*4882a593Smuzhiyun 	txrate->count = 1;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	switch (FIELD_GET(MT_TXWI_RATE_PHY_MODE, rate)) {
37*4882a593Smuzhiyun 	case MT_PHY_TYPE_OFDM:
38*4882a593Smuzhiyun 		txrate->idx = idx + 4;
39*4882a593Smuzhiyun 		return;
40*4882a593Smuzhiyun 	case MT_PHY_TYPE_CCK:
41*4882a593Smuzhiyun 		if (idx >= 8)
42*4882a593Smuzhiyun 			idx -= 8;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 		txrate->idx = idx;
45*4882a593Smuzhiyun 		return;
46*4882a593Smuzhiyun 	case MT_PHY_TYPE_HT_GF:
47*4882a593Smuzhiyun 		txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD;
48*4882a593Smuzhiyun 		fallthrough;
49*4882a593Smuzhiyun 	case MT_PHY_TYPE_HT:
50*4882a593Smuzhiyun 		txrate->flags |= IEEE80211_TX_RC_MCS;
51*4882a593Smuzhiyun 		txrate->idx = idx;
52*4882a593Smuzhiyun 		break;
53*4882a593Smuzhiyun 	default:
54*4882a593Smuzhiyun 		WARN_ON(1);
55*4882a593Smuzhiyun 		return;
56*4882a593Smuzhiyun 	}
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	if (FIELD_GET(MT_TXWI_RATE_BW, rate) == MT_PHY_BW_40)
59*4882a593Smuzhiyun 		txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (rate & MT_TXWI_RATE_SGI)
62*4882a593Smuzhiyun 		txrate->flags |= IEEE80211_TX_RC_SHORT_GI;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static void
mt76_mac_fill_tx_status(struct mt7601u_dev * dev,struct ieee80211_tx_info * info,struct mt76_tx_status * st)66*4882a593Smuzhiyun mt76_mac_fill_tx_status(struct mt7601u_dev *dev, struct ieee80211_tx_info *info,
67*4882a593Smuzhiyun 			struct mt76_tx_status *st)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	struct ieee80211_tx_rate *rate = info->status.rates;
70*4882a593Smuzhiyun 	int cur_idx, last_rate;
71*4882a593Smuzhiyun 	int i;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1);
74*4882a593Smuzhiyun 	mt76_mac_process_tx_rate(&rate[last_rate], st->rate);
75*4882a593Smuzhiyun 	if (last_rate < IEEE80211_TX_MAX_RATES - 1)
76*4882a593Smuzhiyun 		rate[last_rate + 1].idx = -1;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	cur_idx = rate[last_rate].idx + st->retry;
79*4882a593Smuzhiyun 	for (i = 0; i <= last_rate; i++) {
80*4882a593Smuzhiyun 		rate[i].flags = rate[last_rate].flags;
81*4882a593Smuzhiyun 		rate[i].idx = max_t(int, 0, cur_idx - i);
82*4882a593Smuzhiyun 		rate[i].count = 1;
83*4882a593Smuzhiyun 	}
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	if (last_rate > 0)
86*4882a593Smuzhiyun 		rate[last_rate - 1].count = st->retry + 1 - last_rate;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	info->status.ampdu_len = 1;
89*4882a593Smuzhiyun 	info->status.ampdu_ack_len = st->success;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	if (st->is_probe)
92*4882a593Smuzhiyun 		info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (st->aggr)
95*4882a593Smuzhiyun 		info->flags |= IEEE80211_TX_CTL_AMPDU |
96*4882a593Smuzhiyun 			       IEEE80211_TX_STAT_AMPDU;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	if (!st->ack_req)
99*4882a593Smuzhiyun 		info->flags |= IEEE80211_TX_CTL_NO_ACK;
100*4882a593Smuzhiyun 	else if (st->success)
101*4882a593Smuzhiyun 		info->flags |= IEEE80211_TX_STAT_ACK;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
mt76_mac_tx_rate_val(struct mt7601u_dev * dev,const struct ieee80211_tx_rate * rate,u8 * nss_val)104*4882a593Smuzhiyun u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev,
105*4882a593Smuzhiyun 			 const struct ieee80211_tx_rate *rate, u8 *nss_val)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	u16 rateval;
108*4882a593Smuzhiyun 	u8 phy, rate_idx;
109*4882a593Smuzhiyun 	u8 nss = 1;
110*4882a593Smuzhiyun 	u8 bw = 0;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	if (rate->flags & IEEE80211_TX_RC_MCS) {
113*4882a593Smuzhiyun 		rate_idx = rate->idx;
114*4882a593Smuzhiyun 		nss = 1 + (rate->idx >> 3);
115*4882a593Smuzhiyun 		phy = MT_PHY_TYPE_HT;
116*4882a593Smuzhiyun 		if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
117*4882a593Smuzhiyun 			phy = MT_PHY_TYPE_HT_GF;
118*4882a593Smuzhiyun 		if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
119*4882a593Smuzhiyun 			bw = 1;
120*4882a593Smuzhiyun 	} else {
121*4882a593Smuzhiyun 		const struct ieee80211_rate *r;
122*4882a593Smuzhiyun 		int band = dev->chandef.chan->band;
123*4882a593Smuzhiyun 		u16 val;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 		r = &dev->hw->wiphy->bands[band]->bitrates[rate->idx];
126*4882a593Smuzhiyun 		if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
127*4882a593Smuzhiyun 			val = r->hw_value_short;
128*4882a593Smuzhiyun 		else
129*4882a593Smuzhiyun 			val = r->hw_value;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 		phy = val >> 8;
132*4882a593Smuzhiyun 		rate_idx = val & 0xff;
133*4882a593Smuzhiyun 		bw = 0;
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	rateval = FIELD_PREP(MT_RXWI_RATE_MCS, rate_idx);
137*4882a593Smuzhiyun 	rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
138*4882a593Smuzhiyun 	rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
139*4882a593Smuzhiyun 	if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
140*4882a593Smuzhiyun 		rateval |= MT_RXWI_RATE_SGI;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	*nss_val = nss;
143*4882a593Smuzhiyun 	return rateval;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
mt76_mac_wcid_set_rate(struct mt7601u_dev * dev,struct mt76_wcid * wcid,const struct ieee80211_tx_rate * rate)146*4882a593Smuzhiyun void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid,
147*4882a593Smuzhiyun 			    const struct ieee80211_tx_rate *rate)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun 	unsigned long flags;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
152*4882a593Smuzhiyun 	wcid->tx_rate = mt76_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
153*4882a593Smuzhiyun 	wcid->tx_rate_set = true;
154*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
mt7601u_mac_fetch_tx_status(struct mt7601u_dev * dev)157*4882a593Smuzhiyun struct mt76_tx_status mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	struct mt76_tx_status stat = {};
160*4882a593Smuzhiyun 	u32 val;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	val = mt7601u_rr(dev, MT_TX_STAT_FIFO);
163*4882a593Smuzhiyun 	stat.valid = !!(val & MT_TX_STAT_FIFO_VALID);
164*4882a593Smuzhiyun 	stat.success = !!(val & MT_TX_STAT_FIFO_SUCCESS);
165*4882a593Smuzhiyun 	stat.aggr = !!(val & MT_TX_STAT_FIFO_AGGR);
166*4882a593Smuzhiyun 	stat.ack_req = !!(val & MT_TX_STAT_FIFO_ACKREQ);
167*4882a593Smuzhiyun 	stat.pktid = FIELD_GET(MT_TX_STAT_FIFO_PID_TYPE, val);
168*4882a593Smuzhiyun 	stat.wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, val);
169*4882a593Smuzhiyun 	stat.rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, val);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	return stat;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
mt76_send_tx_status(struct mt7601u_dev * dev,struct mt76_tx_status * stat)174*4882a593Smuzhiyun void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	struct ieee80211_tx_info info = {};
177*4882a593Smuzhiyun 	struct ieee80211_sta *sta = NULL;
178*4882a593Smuzhiyun 	struct mt76_wcid *wcid = NULL;
179*4882a593Smuzhiyun 	void *msta;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	rcu_read_lock();
182*4882a593Smuzhiyun 	if (stat->wcid < ARRAY_SIZE(dev->wcid))
183*4882a593Smuzhiyun 		wcid = rcu_dereference(dev->wcid[stat->wcid]);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	if (wcid) {
186*4882a593Smuzhiyun 		msta = container_of(wcid, struct mt76_sta, wcid);
187*4882a593Smuzhiyun 		sta = container_of(msta, struct ieee80211_sta,
188*4882a593Smuzhiyun 				   drv_priv);
189*4882a593Smuzhiyun 	}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	mt76_mac_fill_tx_status(dev, &info, stat);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	spin_lock_bh(&dev->mac_lock);
194*4882a593Smuzhiyun 	ieee80211_tx_status_noskb(dev->hw, sta, &info);
195*4882a593Smuzhiyun 	spin_unlock_bh(&dev->mac_lock);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	rcu_read_unlock();
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
mt7601u_mac_set_protection(struct mt7601u_dev * dev,bool legacy_prot,int ht_mode)200*4882a593Smuzhiyun void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot,
201*4882a593Smuzhiyun 				int ht_mode)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION;
204*4882a593Smuzhiyun 	bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
205*4882a593Smuzhiyun 	u32 prot[6];
206*4882a593Smuzhiyun 	bool ht_rts[4] = {};
207*4882a593Smuzhiyun 	int i;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	prot[0] = MT_PROT_NAV_SHORT |
210*4882a593Smuzhiyun 		  MT_PROT_TXOP_ALLOW_ALL |
211*4882a593Smuzhiyun 		  MT_PROT_RTS_THR_EN;
212*4882a593Smuzhiyun 	prot[1] = prot[0];
213*4882a593Smuzhiyun 	if (legacy_prot)
214*4882a593Smuzhiyun 		prot[1] |= MT_PROT_CTRL_CTS2SELF;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	prot[2] = prot[4] = MT_PROT_NAV_SHORT | MT_PROT_TXOP_ALLOW_BW20;
217*4882a593Smuzhiyun 	prot[3] = prot[5] = MT_PROT_NAV_SHORT | MT_PROT_TXOP_ALLOW_ALL;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	if (legacy_prot) {
220*4882a593Smuzhiyun 		prot[2] |= MT_PROT_RATE_CCK_11;
221*4882a593Smuzhiyun 		prot[3] |= MT_PROT_RATE_CCK_11;
222*4882a593Smuzhiyun 		prot[4] |= MT_PROT_RATE_CCK_11;
223*4882a593Smuzhiyun 		prot[5] |= MT_PROT_RATE_CCK_11;
224*4882a593Smuzhiyun 	} else {
225*4882a593Smuzhiyun 		prot[2] |= MT_PROT_RATE_OFDM_24;
226*4882a593Smuzhiyun 		prot[3] |= MT_PROT_RATE_DUP_OFDM_24;
227*4882a593Smuzhiyun 		prot[4] |= MT_PROT_RATE_OFDM_24;
228*4882a593Smuzhiyun 		prot[5] |= MT_PROT_RATE_DUP_OFDM_24;
229*4882a593Smuzhiyun 	}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	switch (mode) {
232*4882a593Smuzhiyun 	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
233*4882a593Smuzhiyun 		break;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
236*4882a593Smuzhiyun 		ht_rts[0] = ht_rts[1] = ht_rts[2] = ht_rts[3] = true;
237*4882a593Smuzhiyun 		break;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
240*4882a593Smuzhiyun 		ht_rts[1] = ht_rts[3] = true;
241*4882a593Smuzhiyun 		break;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
244*4882a593Smuzhiyun 		ht_rts[0] = ht_rts[1] = ht_rts[2] = ht_rts[3] = true;
245*4882a593Smuzhiyun 		break;
246*4882a593Smuzhiyun 	}
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	if (non_gf)
249*4882a593Smuzhiyun 		ht_rts[2] = ht_rts[3] = true;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	for (i = 0; i < 4; i++)
252*4882a593Smuzhiyun 		if (ht_rts[i])
253*4882a593Smuzhiyun 			prot[i + 2] |= MT_PROT_CTRL_RTS_CTS;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	for (i = 0; i < 6; i++)
256*4882a593Smuzhiyun 		mt7601u_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
mt7601u_mac_set_short_preamble(struct mt7601u_dev * dev,bool short_preamb)259*4882a593Smuzhiyun void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	if (short_preamb)
262*4882a593Smuzhiyun 		mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT);
263*4882a593Smuzhiyun 	else
264*4882a593Smuzhiyun 		mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
mt7601u_mac_config_tsf(struct mt7601u_dev * dev,bool enable,int interval)267*4882a593Smuzhiyun void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	val &= ~(MT_BEACON_TIME_CFG_TIMER_EN |
272*4882a593Smuzhiyun 		 MT_BEACON_TIME_CFG_SYNC_MODE |
273*4882a593Smuzhiyun 		 MT_BEACON_TIME_CFG_TBTT_EN);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	if (!enable) {
276*4882a593Smuzhiyun 		mt7601u_wr(dev, MT_BEACON_TIME_CFG, val);
277*4882a593Smuzhiyun 		return;
278*4882a593Smuzhiyun 	}
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	val &= ~MT_BEACON_TIME_CFG_INTVAL;
281*4882a593Smuzhiyun 	val |= FIELD_PREP(MT_BEACON_TIME_CFG_INTVAL, interval << 4) |
282*4882a593Smuzhiyun 		MT_BEACON_TIME_CFG_TIMER_EN |
283*4882a593Smuzhiyun 		MT_BEACON_TIME_CFG_SYNC_MODE |
284*4882a593Smuzhiyun 		MT_BEACON_TIME_CFG_TBTT_EN;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
mt7601u_check_mac_err(struct mt7601u_dev * dev)287*4882a593Smuzhiyun static void mt7601u_check_mac_err(struct mt7601u_dev *dev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	u32 val = mt7601u_rr(dev, 0x10f4);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5))))
292*4882a593Smuzhiyun 		return;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	dev_err(dev->dev, "Error: MAC specific condition occurred\n");
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR);
297*4882a593Smuzhiyun 	udelay(10);
298*4882a593Smuzhiyun 	mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR);
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
mt7601u_mac_work(struct work_struct * work)301*4882a593Smuzhiyun void mt7601u_mac_work(struct work_struct *work)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
304*4882a593Smuzhiyun 					       mac_work.work);
305*4882a593Smuzhiyun 	struct {
306*4882a593Smuzhiyun 		u32 addr_base;
307*4882a593Smuzhiyun 		u32 span;
308*4882a593Smuzhiyun 		u64 *stat_base;
309*4882a593Smuzhiyun 	} spans[] = {
310*4882a593Smuzhiyun 		{ MT_RX_STA_CNT0,	3,	dev->stats.rx_stat },
311*4882a593Smuzhiyun 		{ MT_TX_STA_CNT0,	3,	dev->stats.tx_stat },
312*4882a593Smuzhiyun 		{ MT_TX_AGG_STAT,	1,	dev->stats.aggr_stat },
313*4882a593Smuzhiyun 		{ MT_MPDU_DENSITY_CNT,	1,	dev->stats.zero_len_del },
314*4882a593Smuzhiyun 		{ MT_TX_AGG_CNT_BASE0,	8,	&dev->stats.aggr_n[0] },
315*4882a593Smuzhiyun 		{ MT_TX_AGG_CNT_BASE1,	8,	&dev->stats.aggr_n[16] },
316*4882a593Smuzhiyun 	};
317*4882a593Smuzhiyun 	u32 sum, n;
318*4882a593Smuzhiyun 	int i, j, k;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	/* Note: using MCU_RANDOM_READ is actually slower then reading all the
321*4882a593Smuzhiyun 	 *	 registers by hand.  MCU takes ca. 20ms to complete read of 24
322*4882a593Smuzhiyun 	 *	 registers while reading them one by one will takes roughly
323*4882a593Smuzhiyun 	 *	 24*200us =~ 5ms.
324*4882a593Smuzhiyun 	 */
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	k = 0;
327*4882a593Smuzhiyun 	n = 0;
328*4882a593Smuzhiyun 	sum = 0;
329*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(spans); i++)
330*4882a593Smuzhiyun 		for (j = 0; j < spans[i].span; j++) {
331*4882a593Smuzhiyun 			u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 			spans[i].stat_base[j * 2] += val & 0xffff;
334*4882a593Smuzhiyun 			spans[i].stat_base[j * 2 + 1] += val >> 16;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 			/* Calculate average AMPDU length */
337*4882a593Smuzhiyun 			if (spans[i].addr_base != MT_TX_AGG_CNT_BASE0 &&
338*4882a593Smuzhiyun 			    spans[i].addr_base != MT_TX_AGG_CNT_BASE1)
339*4882a593Smuzhiyun 				continue;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 			n += (val >> 16) + (val & 0xffff);
342*4882a593Smuzhiyun 			sum += (val & 0xffff) * (1 + k * 2) +
343*4882a593Smuzhiyun 				(val >> 16) * (2 + k * 2);
344*4882a593Smuzhiyun 			k++;
345*4882a593Smuzhiyun 		}
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	atomic_set(&dev->avg_ampdu_len, n ? DIV_ROUND_CLOSEST(sum, n) : 1);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	mt7601u_check_mac_err(dev);
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	ieee80211_queue_delayed_work(dev->hw, &dev->mac_work, 10 * HZ);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun void
mt7601u_mac_wcid_setup(struct mt7601u_dev * dev,u8 idx,u8 vif_idx,u8 * mac)355*4882a593Smuzhiyun mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun 	u8 zmac[ETH_ALEN] = {};
358*4882a593Smuzhiyun 	u32 attr;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
361*4882a593Smuzhiyun 	       FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	mt76_wr(dev, MT_WCID_ATTR(idx), attr);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	if (mac)
366*4882a593Smuzhiyun 		memcpy(zmac, mac, sizeof(zmac));
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	mt7601u_addr_wr(dev, MT_WCID_ADDR(idx), zmac);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
mt7601u_mac_set_ampdu_factor(struct mt7601u_dev * dev)371*4882a593Smuzhiyun void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun 	struct ieee80211_sta *sta;
374*4882a593Smuzhiyun 	struct mt76_wcid *wcid;
375*4882a593Smuzhiyun 	void *msta;
376*4882a593Smuzhiyun 	u8 min_factor = 3;
377*4882a593Smuzhiyun 	int i;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	rcu_read_lock();
380*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(dev->wcid); i++) {
381*4882a593Smuzhiyun 		wcid = rcu_dereference(dev->wcid[i]);
382*4882a593Smuzhiyun 		if (!wcid)
383*4882a593Smuzhiyun 			continue;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 		msta = container_of(wcid, struct mt76_sta, wcid);
386*4882a593Smuzhiyun 		sta = container_of(msta, struct ieee80211_sta, drv_priv);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 		min_factor = min(min_factor, sta->ht_cap.ampdu_factor);
389*4882a593Smuzhiyun 	}
390*4882a593Smuzhiyun 	rcu_read_unlock();
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_MAX_LEN_CFG, 0xa0fff |
393*4882a593Smuzhiyun 		   FIELD_PREP(MT_MAX_LEN_CFG_AMPDU, min_factor));
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun static void
mt76_mac_process_rate(struct ieee80211_rx_status * status,u16 rate)397*4882a593Smuzhiyun mt76_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	u8 idx = FIELD_GET(MT_RXWI_RATE_MCS, rate);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
402*4882a593Smuzhiyun 	case MT_PHY_TYPE_OFDM:
403*4882a593Smuzhiyun 		if (WARN_ON(idx >= 8))
404*4882a593Smuzhiyun 			idx = 0;
405*4882a593Smuzhiyun 		idx += 4;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 		status->rate_idx = idx;
408*4882a593Smuzhiyun 		return;
409*4882a593Smuzhiyun 	case MT_PHY_TYPE_CCK:
410*4882a593Smuzhiyun 		if (idx >= 8) {
411*4882a593Smuzhiyun 			idx -= 8;
412*4882a593Smuzhiyun 			status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
413*4882a593Smuzhiyun 		}
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 		if (WARN_ON(idx >= 4))
416*4882a593Smuzhiyun 			idx = 0;
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 		status->rate_idx = idx;
419*4882a593Smuzhiyun 		return;
420*4882a593Smuzhiyun 	case MT_PHY_TYPE_HT_GF:
421*4882a593Smuzhiyun 		status->enc_flags |= RX_ENC_FLAG_HT_GF;
422*4882a593Smuzhiyun 		fallthrough;
423*4882a593Smuzhiyun 	case MT_PHY_TYPE_HT:
424*4882a593Smuzhiyun 		status->encoding = RX_ENC_HT;
425*4882a593Smuzhiyun 		status->rate_idx = idx;
426*4882a593Smuzhiyun 		break;
427*4882a593Smuzhiyun 	default:
428*4882a593Smuzhiyun 		WARN_ON(1);
429*4882a593Smuzhiyun 		return;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	if (rate & MT_RXWI_RATE_SGI)
433*4882a593Smuzhiyun 		status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	if (rate & MT_RXWI_RATE_STBC)
436*4882a593Smuzhiyun 		status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	if (rate & MT_RXWI_RATE_BW)
439*4882a593Smuzhiyun 		status->bw = RATE_INFO_BW_40;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun static void
mt7601u_rx_monitor_beacon(struct mt7601u_dev * dev,struct mt7601u_rxwi * rxwi,u16 rate,int rssi)443*4882a593Smuzhiyun mt7601u_rx_monitor_beacon(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi,
444*4882a593Smuzhiyun 			  u16 rate, int rssi)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	dev->bcn_freq_off = rxwi->freq_off;
447*4882a593Smuzhiyun 	dev->bcn_phy_mode = FIELD_GET(MT_RXWI_RATE_PHY, rate);
448*4882a593Smuzhiyun 	ewma_rssi_add(&dev->avg_rssi, -rssi);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun static int
mt7601u_rx_is_our_beacon(struct mt7601u_dev * dev,u8 * data)452*4882a593Smuzhiyun mt7601u_rx_is_our_beacon(struct mt7601u_dev *dev, u8 *data)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)data;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	return ieee80211_is_beacon(hdr->frame_control) &&
457*4882a593Smuzhiyun 		ether_addr_equal(hdr->addr2, dev->ap_bssid);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
mt76_mac_process_rx(struct mt7601u_dev * dev,struct sk_buff * skb,u8 * data,void * rxi)460*4882a593Smuzhiyun u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb,
461*4882a593Smuzhiyun 			u8 *data, void *rxi)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb);
464*4882a593Smuzhiyun 	struct mt7601u_rxwi *rxwi = rxi;
465*4882a593Smuzhiyun 	u32 len, ctl = le32_to_cpu(rxwi->ctl);
466*4882a593Smuzhiyun 	u16 rate = le16_to_cpu(rxwi->rate);
467*4882a593Smuzhiyun 	int rssi;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl);
470*4882a593Smuzhiyun 	if (len < 10)
471*4882a593Smuzhiyun 		return 0;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_DECRYPT)) {
474*4882a593Smuzhiyun 		status->flag |= RX_FLAG_DECRYPTED;
475*4882a593Smuzhiyun 		status->flag |= RX_FLAG_MMIC_STRIPPED;
476*4882a593Smuzhiyun 		status->flag |= RX_FLAG_MIC_STRIPPED;
477*4882a593Smuzhiyun 		status->flag |= RX_FLAG_ICV_STRIPPED;
478*4882a593Smuzhiyun 		status->flag |= RX_FLAG_IV_STRIPPED;
479*4882a593Smuzhiyun 	}
480*4882a593Smuzhiyun 	/* let mac80211 take care of PN validation since apparently
481*4882a593Smuzhiyun 	 * the hardware does not support it
482*4882a593Smuzhiyun 	 */
483*4882a593Smuzhiyun 	if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_PN_LEN))
484*4882a593Smuzhiyun 		status->flag &= ~RX_FLAG_IV_STRIPPED;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	status->chains = BIT(0);
487*4882a593Smuzhiyun 	rssi = mt7601u_phy_get_rssi(dev, rxwi, rate);
488*4882a593Smuzhiyun 	status->chain_signal[0] = status->signal = rssi;
489*4882a593Smuzhiyun 	status->freq = dev->chandef.chan->center_freq;
490*4882a593Smuzhiyun 	status->band = dev->chandef.chan->band;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	mt76_mac_process_rate(status, rate);
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	spin_lock_bh(&dev->con_mon_lock);
495*4882a593Smuzhiyun 	if (mt7601u_rx_is_our_beacon(dev, data))
496*4882a593Smuzhiyun 		mt7601u_rx_monitor_beacon(dev, rxwi, rate, rssi);
497*4882a593Smuzhiyun 	else if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_U2M))
498*4882a593Smuzhiyun 		ewma_rssi_add(&dev->avg_rssi, -rssi);
499*4882a593Smuzhiyun 	spin_unlock_bh(&dev->con_mon_lock);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	return len;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun static enum mt76_cipher_type
mt76_mac_get_key_info(struct ieee80211_key_conf * key,u8 * key_data)505*4882a593Smuzhiyun mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun 	memset(key_data, 0, 32);
508*4882a593Smuzhiyun 	if (!key)
509*4882a593Smuzhiyun 		return MT_CIPHER_NONE;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	if (key->keylen > 32)
512*4882a593Smuzhiyun 		return MT_CIPHER_NONE;
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	memcpy(key_data, key->key, key->keylen);
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	switch (key->cipher) {
517*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_WEP40:
518*4882a593Smuzhiyun 		return MT_CIPHER_WEP40;
519*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_WEP104:
520*4882a593Smuzhiyun 		return MT_CIPHER_WEP104;
521*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_TKIP:
522*4882a593Smuzhiyun 		return MT_CIPHER_TKIP;
523*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_CCMP:
524*4882a593Smuzhiyun 		return MT_CIPHER_AES_CCMP;
525*4882a593Smuzhiyun 	default:
526*4882a593Smuzhiyun 		return MT_CIPHER_NONE;
527*4882a593Smuzhiyun 	}
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun 
mt76_mac_wcid_set_key(struct mt7601u_dev * dev,u8 idx,struct ieee80211_key_conf * key)530*4882a593Smuzhiyun int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx,
531*4882a593Smuzhiyun 			  struct ieee80211_key_conf *key)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	enum mt76_cipher_type cipher;
534*4882a593Smuzhiyun 	u8 key_data[32];
535*4882a593Smuzhiyun 	u8 iv_data[8];
536*4882a593Smuzhiyun 	u32 val;
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	cipher = mt76_mac_get_key_info(key, key_data);
539*4882a593Smuzhiyun 	if (cipher == MT_CIPHER_NONE && key)
540*4882a593Smuzhiyun 		return -EINVAL;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	trace_set_key(dev, idx);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	mt7601u_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	memset(iv_data, 0, sizeof(iv_data));
547*4882a593Smuzhiyun 	if (key) {
548*4882a593Smuzhiyun 		iv_data[3] = key->keyidx << 6;
549*4882a593Smuzhiyun 		if (cipher >= MT_CIPHER_TKIP) {
550*4882a593Smuzhiyun 			/* Note: start with 1 to comply with spec,
551*4882a593Smuzhiyun 			 *	 (see comment on common/cmm_wpa.c:4291).
552*4882a593Smuzhiyun 			 */
553*4882a593Smuzhiyun 			iv_data[0] |= 1;
554*4882a593Smuzhiyun 			iv_data[3] |= 0x20;
555*4882a593Smuzhiyun 		}
556*4882a593Smuzhiyun 	}
557*4882a593Smuzhiyun 	mt7601u_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	val = mt7601u_rr(dev, MT_WCID_ATTR(idx));
560*4882a593Smuzhiyun 	val &= ~MT_WCID_ATTR_PKEY_MODE & ~MT_WCID_ATTR_PKEY_MODE_EXT;
561*4882a593Smuzhiyun 	val |= FIELD_PREP(MT_WCID_ATTR_PKEY_MODE, cipher & 7) |
562*4882a593Smuzhiyun 	       FIELD_PREP(MT_WCID_ATTR_PKEY_MODE_EXT, cipher >> 3);
563*4882a593Smuzhiyun 	val &= ~MT_WCID_ATTR_PAIRWISE;
564*4882a593Smuzhiyun 	val |= MT_WCID_ATTR_PAIRWISE *
565*4882a593Smuzhiyun 		!!(key && key->flags & IEEE80211_KEY_FLAG_PAIRWISE);
566*4882a593Smuzhiyun 	mt7601u_wr(dev, MT_WCID_ATTR(idx), val);
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	return 0;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun 
mt76_mac_shared_key_setup(struct mt7601u_dev * dev,u8 vif_idx,u8 key_idx,struct ieee80211_key_conf * key)571*4882a593Smuzhiyun int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx,
572*4882a593Smuzhiyun 			      struct ieee80211_key_conf *key)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun 	enum mt76_cipher_type cipher;
575*4882a593Smuzhiyun 	u8 key_data[32];
576*4882a593Smuzhiyun 	u32 val;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	cipher = mt76_mac_get_key_info(key, key_data);
579*4882a593Smuzhiyun 	if (cipher == MT_CIPHER_NONE && key)
580*4882a593Smuzhiyun 		return -EINVAL;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	trace_set_shared_key(dev, vif_idx, key_idx);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	mt7601u_wr_copy(dev, MT_SKEY(vif_idx, key_idx),
585*4882a593Smuzhiyun 			key_data, sizeof(key_data));
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	val = mt76_rr(dev, MT_SKEY_MODE(vif_idx));
588*4882a593Smuzhiyun 	val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx));
589*4882a593Smuzhiyun 	val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx);
590*4882a593Smuzhiyun 	mt76_wr(dev, MT_SKEY_MODE(vif_idx), val);
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	return 0;
593*4882a593Smuzhiyun }
594