1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4*4882a593Smuzhiyun * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __MT7601U_EEPROM_H
8*4882a593Smuzhiyun #define __MT7601U_EEPROM_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun struct mt7601u_dev;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define MT7601U_EE_MAX_VER 0x0d
13*4882a593Smuzhiyun #define MT7601U_EEPROM_SIZE 256
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define MT7601U_DEFAULT_TX_POWER 6
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun enum mt76_eeprom_field {
18*4882a593Smuzhiyun MT_EE_CHIP_ID = 0x00,
19*4882a593Smuzhiyun MT_EE_VERSION_FAE = 0x02,
20*4882a593Smuzhiyun MT_EE_VERSION_EE = 0x03,
21*4882a593Smuzhiyun MT_EE_MAC_ADDR = 0x04,
22*4882a593Smuzhiyun MT_EE_NIC_CONF_0 = 0x34,
23*4882a593Smuzhiyun MT_EE_NIC_CONF_1 = 0x36,
24*4882a593Smuzhiyun MT_EE_COUNTRY_REGION = 0x39,
25*4882a593Smuzhiyun MT_EE_FREQ_OFFSET = 0x3a,
26*4882a593Smuzhiyun MT_EE_NIC_CONF_2 = 0x42,
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun MT_EE_LNA_GAIN = 0x44,
29*4882a593Smuzhiyun MT_EE_RSSI_OFFSET = 0x46,
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun MT_EE_TX_POWER_DELTA_BW40 = 0x50,
32*4882a593Smuzhiyun MT_EE_TX_POWER_OFFSET = 0x52,
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun MT_EE_TX_TSSI_SLOPE = 0x6e,
35*4882a593Smuzhiyun MT_EE_TX_TSSI_OFFSET_GROUP = 0x6f,
36*4882a593Smuzhiyun MT_EE_TX_TSSI_OFFSET = 0x76,
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun MT_EE_TX_TSSI_TARGET_POWER = 0xd0,
39*4882a593Smuzhiyun MT_EE_REF_TEMP = 0xd1,
40*4882a593Smuzhiyun MT_EE_FREQ_OFFSET_COMPENSATION = 0xdb,
41*4882a593Smuzhiyun MT_EE_TX_POWER_BYRATE_BASE = 0xde,
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun MT_EE_USAGE_MAP_START = 0x1e0,
44*4882a593Smuzhiyun MT_EE_USAGE_MAP_END = 0x1fc,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
48*4882a593Smuzhiyun #define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
49*4882a593Smuzhiyun #define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0)
52*4882a593Smuzhiyun #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)
53*4882a593Smuzhiyun #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)
54*4882a593Smuzhiyun #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)
55*4882a593Smuzhiyun #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0)
58*4882a593Smuzhiyun #define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4)
59*4882a593Smuzhiyun #define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8)
60*4882a593Smuzhiyun #define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)
61*4882a593Smuzhiyun #define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11)
62*4882a593Smuzhiyun #define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define MT_EE_TX_POWER_BYRATE(i) (MT_EE_TX_POWER_BYRATE_BASE + \
65*4882a593Smuzhiyun (i) * 4)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \
68*4882a593Smuzhiyun MT_EE_USAGE_MAP_START + 1)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun enum mt7601u_eeprom_access_modes {
71*4882a593Smuzhiyun MT_EE_READ = 0,
72*4882a593Smuzhiyun MT_EE_PHYSICAL_READ = 1,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun struct power_per_rate {
76*4882a593Smuzhiyun u8 raw; /* validated s6 value */
77*4882a593Smuzhiyun s8 bw20; /* sign-extended int */
78*4882a593Smuzhiyun s8 bw40; /* sign-extended int */
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Power per rate - one value per two rates */
82*4882a593Smuzhiyun struct mt7601u_rate_power {
83*4882a593Smuzhiyun struct power_per_rate cck[2];
84*4882a593Smuzhiyun struct power_per_rate ofdm[4];
85*4882a593Smuzhiyun struct power_per_rate ht[4];
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct reg_channel_bounds {
89*4882a593Smuzhiyun u8 start;
90*4882a593Smuzhiyun u8 num;
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun struct mt7601u_eeprom_params {
94*4882a593Smuzhiyun bool tssi_enabled;
95*4882a593Smuzhiyun u8 rf_freq_off;
96*4882a593Smuzhiyun s8 rssi_offset[2];
97*4882a593Smuzhiyun s8 ref_temp;
98*4882a593Smuzhiyun s8 lna_gain;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun u8 chan_pwr[14];
101*4882a593Smuzhiyun struct mt7601u_rate_power power_rate_table;
102*4882a593Smuzhiyun s8 real_cck_bw20[2];
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* TSSI stuff - only with internal TX ALC */
105*4882a593Smuzhiyun struct tssi_data {
106*4882a593Smuzhiyun int tx0_delta_offset;
107*4882a593Smuzhiyun u8 slope;
108*4882a593Smuzhiyun u8 offset[3];
109*4882a593Smuzhiyun } tssi_data;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun struct reg_channel_bounds reg;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun int mt7601u_eeprom_init(struct mt7601u_dev *dev);
115*4882a593Smuzhiyun
s6_validate(u32 reg)116*4882a593Smuzhiyun static inline u32 s6_validate(u32 reg)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun WARN_ON(reg & ~GENMASK(5, 0));
119*4882a593Smuzhiyun return reg & GENMASK(5, 0);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
s6_to_int(u32 reg)122*4882a593Smuzhiyun static inline int s6_to_int(u32 reg)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun int s6;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun s6 = s6_validate(reg);
127*4882a593Smuzhiyun if (s6 & BIT(5))
128*4882a593Smuzhiyun s6 -= BIT(6);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return s6;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
int_to_s6(int val)133*4882a593Smuzhiyun static inline u32 int_to_s6(int val)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun if (val < -0x20)
136*4882a593Smuzhiyun return 0x20;
137*4882a593Smuzhiyun if (val > 0x1f)
138*4882a593Smuzhiyun return 0x1f;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return val & 0x3f;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #endif
144