1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4*4882a593Smuzhiyun * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __MT7601U_DMA_H
8*4882a593Smuzhiyun #define __MT7601U_DMA_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/unaligned.h>
11*4882a593Smuzhiyun #include <linux/skbuff.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define MT_DMA_HDR_LEN 4
14*4882a593Smuzhiyun #define MT_RX_INFO_LEN 4
15*4882a593Smuzhiyun #define MT_FCE_INFO_LEN 4
16*4882a593Smuzhiyun #define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN)
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Common Tx DMA descriptor fields */
19*4882a593Smuzhiyun #define MT_TXD_INFO_LEN GENMASK(15, 0)
20*4882a593Smuzhiyun #define MT_TXD_INFO_D_PORT GENMASK(29, 27)
21*4882a593Smuzhiyun #define MT_TXD_INFO_TYPE GENMASK(31, 30)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun enum mt76_msg_port {
24*4882a593Smuzhiyun WLAN_PORT,
25*4882a593Smuzhiyun CPU_RX_PORT,
26*4882a593Smuzhiyun CPU_TX_PORT,
27*4882a593Smuzhiyun HOST_PORT,
28*4882a593Smuzhiyun VIRTUAL_CPU_RX_PORT,
29*4882a593Smuzhiyun VIRTUAL_CPU_TX_PORT,
30*4882a593Smuzhiyun DISCARD,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun enum mt76_info_type {
34*4882a593Smuzhiyun DMA_PACKET,
35*4882a593Smuzhiyun DMA_COMMAND,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Tx DMA packet specific flags */
39*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_NEXT_VLD BIT(16)
40*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_TX_BURST BIT(17)
41*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_80211 BIT(19)
42*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_TSO BIT(20)
43*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_CSO BIT(21)
44*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_WIV BIT(24)
45*4882a593Smuzhiyun #define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun enum mt76_qsel {
48*4882a593Smuzhiyun MT_QSEL_MGMT,
49*4882a593Smuzhiyun MT_QSEL_HCCA,
50*4882a593Smuzhiyun MT_QSEL_EDCA,
51*4882a593Smuzhiyun MT_QSEL_EDCA_2,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Tx DMA MCU command specific flags */
55*4882a593Smuzhiyun #define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16)
56*4882a593Smuzhiyun #define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20)
57*4882a593Smuzhiyun
mt7601u_dma_skb_wrap(struct sk_buff * skb,enum mt76_msg_port d_port,enum mt76_info_type type,u32 flags)58*4882a593Smuzhiyun static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb,
59*4882a593Smuzhiyun enum mt76_msg_port d_port,
60*4882a593Smuzhiyun enum mt76_info_type type, u32 flags)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun u32 info;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Buffer layout:
65*4882a593Smuzhiyun * | 4B | xfer len | pad | 4B |
66*4882a593Smuzhiyun * | TXINFO | pkt/cmd | zero pad to 4B | zero |
67*4882a593Smuzhiyun *
68*4882a593Smuzhiyun * length field of TXINFO should be set to 'xfer len'.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun info = flags |
72*4882a593Smuzhiyun FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
73*4882a593Smuzhiyun FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) |
74*4882a593Smuzhiyun FIELD_PREP(MT_TXD_INFO_TYPE, type);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun put_unaligned_le32(info, skb_push(skb, sizeof(info)));
77*4882a593Smuzhiyun return skb_put_padto(skb, round_up(skb->len, 4) + 4);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static inline int
mt7601u_dma_skb_wrap_pkt(struct sk_buff * skb,enum mt76_qsel qsel,u32 flags)81*4882a593Smuzhiyun mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel);
84*4882a593Smuzhiyun return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Common Rx DMA descriptor fields */
88*4882a593Smuzhiyun #define MT_RXD_INFO_LEN GENMASK(13, 0)
89*4882a593Smuzhiyun #define MT_RXD_INFO_PCIE_INTR BIT(24)
90*4882a593Smuzhiyun #define MT_RXD_INFO_QSEL GENMASK(26, 25)
91*4882a593Smuzhiyun #define MT_RXD_INFO_PORT GENMASK(29, 27)
92*4882a593Smuzhiyun #define MT_RXD_INFO_TYPE GENMASK(31, 30)
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Rx DMA packet specific flags */
95*4882a593Smuzhiyun #define MT_RXD_PKT_INFO_UDP_ERR BIT(16)
96*4882a593Smuzhiyun #define MT_RXD_PKT_INFO_TCP_ERR BIT(17)
97*4882a593Smuzhiyun #define MT_RXD_PKT_INFO_IP_ERR BIT(18)
98*4882a593Smuzhiyun #define MT_RXD_PKT_INFO_PKT_80211 BIT(19)
99*4882a593Smuzhiyun #define MT_RXD_PKT_INFO_L3L4_DONE BIT(20)
100*4882a593Smuzhiyun #define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21)
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Rx DMA MCU command specific flags */
103*4882a593Smuzhiyun #define MT_RXD_CMD_INFO_SELF_GEN BIT(15)
104*4882a593Smuzhiyun #define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16)
105*4882a593Smuzhiyun #define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20)
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun enum mt76_evt_type {
108*4882a593Smuzhiyun CMD_DONE,
109*4882a593Smuzhiyun CMD_ERROR,
110*4882a593Smuzhiyun CMD_RETRY,
111*4882a593Smuzhiyun EVENT_PWR_RSP,
112*4882a593Smuzhiyun EVENT_WOW_RSP,
113*4882a593Smuzhiyun EVENT_CARRIER_DETECT_RSP,
114*4882a593Smuzhiyun EVENT_DFS_DETECT_RSP,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #endif
118