1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include "mt76.h"
8*4882a593Smuzhiyun
__mt76_poll(struct mt76_dev * dev,u32 offset,u32 mask,u32 val,int timeout)9*4882a593Smuzhiyun bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
10*4882a593Smuzhiyun int timeout)
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun u32 cur;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun timeout /= 10;
15*4882a593Smuzhiyun do {
16*4882a593Smuzhiyun cur = __mt76_rr(dev, offset) & mask;
17*4882a593Smuzhiyun if (cur == val)
18*4882a593Smuzhiyun return true;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun udelay(10);
21*4882a593Smuzhiyun } while (timeout-- > 0);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun return false;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__mt76_poll);
26*4882a593Smuzhiyun
__mt76_poll_msec(struct mt76_dev * dev,u32 offset,u32 mask,u32 val,int timeout)27*4882a593Smuzhiyun bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
28*4882a593Smuzhiyun int timeout)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun u32 cur;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun timeout /= 10;
33*4882a593Smuzhiyun do {
34*4882a593Smuzhiyun cur = __mt76_rr(dev, offset) & mask;
35*4882a593Smuzhiyun if (cur == val)
36*4882a593Smuzhiyun return true;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun usleep_range(10000, 20000);
39*4882a593Smuzhiyun } while (timeout-- > 0);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return false;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__mt76_poll_msec);
44*4882a593Smuzhiyun
mt76_wcid_alloc(u32 * mask,int size)45*4882a593Smuzhiyun int mt76_wcid_alloc(u32 *mask, int size)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun int i, idx = 0, cur;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun for (i = 0; i < DIV_ROUND_UP(size, 32); i++) {
50*4882a593Smuzhiyun idx = ffs(~mask[i]);
51*4882a593Smuzhiyun if (!idx)
52*4882a593Smuzhiyun continue;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun idx--;
55*4882a593Smuzhiyun cur = i * 32 + idx;
56*4882a593Smuzhiyun if (cur >= size)
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun mask[i] |= BIT(idx);
60*4882a593Smuzhiyun return cur;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return -1;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_wcid_alloc);
66*4882a593Smuzhiyun
mt76_get_min_avg_rssi(struct mt76_dev * dev,bool ext_phy)67*4882a593Smuzhiyun int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct mt76_wcid *wcid;
70*4882a593Smuzhiyun int i, j, min_rssi = 0;
71*4882a593Smuzhiyun s8 cur_rssi;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun local_bh_disable();
74*4882a593Smuzhiyun rcu_read_lock();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(dev->wcid_mask); i++) {
77*4882a593Smuzhiyun u32 mask = dev->wcid_mask[i];
78*4882a593Smuzhiyun u32 phy_mask = dev->wcid_phy_mask[i];
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (!mask)
81*4882a593Smuzhiyun continue;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun for (j = i * 32; mask; j++, mask >>= 1, phy_mask >>= 1) {
84*4882a593Smuzhiyun if (!(mask & 1))
85*4882a593Smuzhiyun continue;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (!!(phy_mask & 1) != ext_phy)
88*4882a593Smuzhiyun continue;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun wcid = rcu_dereference(dev->wcid[j]);
91*4882a593Smuzhiyun if (!wcid)
92*4882a593Smuzhiyun continue;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun spin_lock(&dev->rx_lock);
95*4882a593Smuzhiyun if (wcid->inactive_count++ < 5)
96*4882a593Smuzhiyun cur_rssi = -ewma_signal_read(&wcid->rssi);
97*4882a593Smuzhiyun else
98*4882a593Smuzhiyun cur_rssi = 0;
99*4882a593Smuzhiyun spin_unlock(&dev->rx_lock);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (cur_rssi < min_rssi)
102*4882a593Smuzhiyun min_rssi = cur_rssi;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun rcu_read_unlock();
107*4882a593Smuzhiyun local_bh_enable();
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return min_rssi;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_get_min_avg_rssi);
112*4882a593Smuzhiyun
__mt76_worker_fn(void * ptr)113*4882a593Smuzhiyun int __mt76_worker_fn(void *ptr)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct mt76_worker *w = ptr;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun while (!kthread_should_stop()) {
118*4882a593Smuzhiyun set_current_state(TASK_INTERRUPTIBLE);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (kthread_should_park()) {
121*4882a593Smuzhiyun kthread_parkme();
122*4882a593Smuzhiyun continue;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (!test_and_clear_bit(MT76_WORKER_SCHEDULED, &w->state)) {
126*4882a593Smuzhiyun schedule();
127*4882a593Smuzhiyun continue;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun set_bit(MT76_WORKER_RUNNING, &w->state);
131*4882a593Smuzhiyun set_current_state(TASK_RUNNING);
132*4882a593Smuzhiyun w->fn(w);
133*4882a593Smuzhiyun cond_resched();
134*4882a593Smuzhiyun clear_bit(MT76_WORKER_RUNNING, &w->state);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__mt76_worker_fn);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
142