xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/tx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include "mt76.h"
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun static int
mt76_txq_get_qid(struct ieee80211_txq * txq)9*4882a593Smuzhiyun mt76_txq_get_qid(struct ieee80211_txq *txq)
10*4882a593Smuzhiyun {
11*4882a593Smuzhiyun 	if (!txq->sta)
12*4882a593Smuzhiyun 		return MT_TXQ_BE;
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun 	return txq->ac;
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun void
mt76_tx_check_agg_ssn(struct ieee80211_sta * sta,struct sk_buff * skb)18*4882a593Smuzhiyun mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
21*4882a593Smuzhiyun 	struct ieee80211_txq *txq;
22*4882a593Smuzhiyun 	struct mt76_txq *mtxq;
23*4882a593Smuzhiyun 	u8 tid;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	if (!sta || !ieee80211_is_data_qos(hdr->frame_control) ||
26*4882a593Smuzhiyun 	    !ieee80211_is_data_present(hdr->frame_control))
27*4882a593Smuzhiyun 		return;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
30*4882a593Smuzhiyun 	txq = sta->txq[tid];
31*4882a593Smuzhiyun 	mtxq = (struct mt76_txq *)txq->drv_priv;
32*4882a593Smuzhiyun 	if (!mtxq->aggr)
33*4882a593Smuzhiyun 		return;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	mtxq->agg_ssn = le16_to_cpu(hdr->seq_ctrl) + 0x10;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_check_agg_ssn);
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun void
mt76_tx_status_lock(struct mt76_dev * dev,struct sk_buff_head * list)40*4882a593Smuzhiyun mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
41*4882a593Smuzhiyun 		   __acquires(&dev->status_list.lock)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	__skb_queue_head_init(list);
44*4882a593Smuzhiyun 	spin_lock_bh(&dev->status_list.lock);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_status_lock);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun void
mt76_tx_status_unlock(struct mt76_dev * dev,struct sk_buff_head * list)49*4882a593Smuzhiyun mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
50*4882a593Smuzhiyun 		      __releases(&dev->status_list.lock)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	struct ieee80211_hw *hw;
53*4882a593Smuzhiyun 	struct sk_buff *skb;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	spin_unlock_bh(&dev->status_list.lock);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	while ((skb = __skb_dequeue(list)) != NULL) {
58*4882a593Smuzhiyun 		hw = mt76_tx_status_get_hw(dev, skb);
59*4882a593Smuzhiyun 		ieee80211_tx_status(hw, skb);
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_status_unlock);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static void
__mt76_tx_status_skb_done(struct mt76_dev * dev,struct sk_buff * skb,u8 flags,struct sk_buff_head * list)66*4882a593Smuzhiyun __mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, u8 flags,
67*4882a593Smuzhiyun 			  struct sk_buff_head *list)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
70*4882a593Smuzhiyun 	struct mt76_tx_cb *cb = mt76_tx_skb_cb(skb);
71*4882a593Smuzhiyun 	u8 done = MT_TX_CB_DMA_DONE | MT_TX_CB_TXS_DONE;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	flags |= cb->flags;
74*4882a593Smuzhiyun 	cb->flags = flags;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	if ((flags & done) != done)
77*4882a593Smuzhiyun 		return;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	__skb_unlink(skb, &dev->status_list);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	/* Tx status can be unreliable. if it fails, mark the frame as ACKed */
82*4882a593Smuzhiyun 	if (flags & MT_TX_CB_TXS_FAILED) {
83*4882a593Smuzhiyun 		ieee80211_tx_info_clear_status(info);
84*4882a593Smuzhiyun 		info->status.rates[0].idx = -1;
85*4882a593Smuzhiyun 		info->flags |= IEEE80211_TX_STAT_ACK;
86*4882a593Smuzhiyun 	}
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	__skb_queue_tail(list, skb);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun void
mt76_tx_status_skb_done(struct mt76_dev * dev,struct sk_buff * skb,struct sk_buff_head * list)92*4882a593Smuzhiyun mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
93*4882a593Smuzhiyun 			struct sk_buff_head *list)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	__mt76_tx_status_skb_done(dev, skb, MT_TX_CB_TXS_DONE, list);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_status_skb_done);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun int
mt76_tx_status_skb_add(struct mt76_dev * dev,struct mt76_wcid * wcid,struct sk_buff * skb)100*4882a593Smuzhiyun mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
101*4882a593Smuzhiyun 		       struct sk_buff *skb)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
104*4882a593Smuzhiyun 	struct mt76_tx_cb *cb = mt76_tx_skb_cb(skb);
105*4882a593Smuzhiyun 	int pid;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	if (!wcid)
108*4882a593Smuzhiyun 		return MT_PACKET_ID_NO_ACK;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (info->flags & IEEE80211_TX_CTL_NO_ACK)
111*4882a593Smuzhiyun 		return MT_PACKET_ID_NO_ACK;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	if (!(info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
114*4882a593Smuzhiyun 			     IEEE80211_TX_CTL_RATE_CTRL_PROBE)))
115*4882a593Smuzhiyun 		return MT_PACKET_ID_NO_SKB;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	spin_lock_bh(&dev->status_list.lock);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	memset(cb, 0, sizeof(*cb));
120*4882a593Smuzhiyun 	wcid->packet_id = (wcid->packet_id + 1) & MT_PACKET_ID_MASK;
121*4882a593Smuzhiyun 	if (wcid->packet_id == MT_PACKET_ID_NO_ACK ||
122*4882a593Smuzhiyun 	    wcid->packet_id == MT_PACKET_ID_NO_SKB)
123*4882a593Smuzhiyun 		wcid->packet_id = MT_PACKET_ID_FIRST;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	pid = wcid->packet_id;
126*4882a593Smuzhiyun 	cb->wcid = wcid->idx;
127*4882a593Smuzhiyun 	cb->pktid = pid;
128*4882a593Smuzhiyun 	cb->jiffies = jiffies;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	__skb_queue_tail(&dev->status_list, skb);
131*4882a593Smuzhiyun 	spin_unlock_bh(&dev->status_list.lock);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return pid;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_status_skb_add);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun struct sk_buff *
mt76_tx_status_skb_get(struct mt76_dev * dev,struct mt76_wcid * wcid,int pktid,struct sk_buff_head * list)138*4882a593Smuzhiyun mt76_tx_status_skb_get(struct mt76_dev *dev, struct mt76_wcid *wcid, int pktid,
139*4882a593Smuzhiyun 		       struct sk_buff_head *list)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	struct sk_buff *skb, *tmp;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	skb_queue_walk_safe(&dev->status_list, skb, tmp) {
144*4882a593Smuzhiyun 		struct mt76_tx_cb *cb = mt76_tx_skb_cb(skb);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 		if (wcid && cb->wcid != wcid->idx)
147*4882a593Smuzhiyun 			continue;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 		if (cb->pktid == pktid)
150*4882a593Smuzhiyun 			return skb;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 		if (pktid >= 0 && !time_after(jiffies, cb->jiffies +
153*4882a593Smuzhiyun 					      MT_TX_STATUS_SKB_TIMEOUT))
154*4882a593Smuzhiyun 			continue;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 		__mt76_tx_status_skb_done(dev, skb, MT_TX_CB_TXS_FAILED |
157*4882a593Smuzhiyun 						    MT_TX_CB_TXS_DONE, list);
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return NULL;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_status_skb_get);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun void
mt76_tx_status_check(struct mt76_dev * dev,struct mt76_wcid * wcid,bool flush)165*4882a593Smuzhiyun mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, bool flush)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	struct sk_buff_head list;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	mt76_tx_status_lock(dev, &list);
170*4882a593Smuzhiyun 	mt76_tx_status_skb_get(dev, wcid, flush ? -1 : 0, &list);
171*4882a593Smuzhiyun 	mt76_tx_status_unlock(dev, &list);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_status_check);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static void
mt76_tx_check_non_aql(struct mt76_dev * dev,u16 wcid_idx,struct sk_buff * skb)176*4882a593Smuzhiyun mt76_tx_check_non_aql(struct mt76_dev *dev, u16 wcid_idx, struct sk_buff *skb)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
179*4882a593Smuzhiyun 	struct mt76_wcid *wcid;
180*4882a593Smuzhiyun 	int pending;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	if (info->tx_time_est)
183*4882a593Smuzhiyun 		return;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	if (wcid_idx >= ARRAY_SIZE(dev->wcid))
186*4882a593Smuzhiyun 		return;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	rcu_read_lock();
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	wcid = rcu_dereference(dev->wcid[wcid_idx]);
191*4882a593Smuzhiyun 	if (wcid) {
192*4882a593Smuzhiyun 		pending = atomic_dec_return(&wcid->non_aql_packets);
193*4882a593Smuzhiyun 		if (pending < 0)
194*4882a593Smuzhiyun 			atomic_cmpxchg(&wcid->non_aql_packets, pending, 0);
195*4882a593Smuzhiyun 	}
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	rcu_read_unlock();
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
mt76_tx_complete_skb(struct mt76_dev * dev,u16 wcid_idx,struct sk_buff * skb)200*4882a593Smuzhiyun void mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid_idx, struct sk_buff *skb)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 	struct ieee80211_hw *hw;
203*4882a593Smuzhiyun 	struct sk_buff_head list;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #ifdef CONFIG_NL80211_TESTMODE
206*4882a593Smuzhiyun 	if (skb == dev->test.tx_skb) {
207*4882a593Smuzhiyun 		dev->test.tx_done++;
208*4882a593Smuzhiyun 		if (dev->test.tx_queued == dev->test.tx_done)
209*4882a593Smuzhiyun 			wake_up(&dev->tx_wait);
210*4882a593Smuzhiyun 	}
211*4882a593Smuzhiyun #endif
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	mt76_tx_check_non_aql(dev, wcid_idx, skb);
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	if (!skb->prev) {
216*4882a593Smuzhiyun 		hw = mt76_tx_status_get_hw(dev, skb);
217*4882a593Smuzhiyun 		ieee80211_free_txskb(hw, skb);
218*4882a593Smuzhiyun 		return;
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	mt76_tx_status_lock(dev, &list);
222*4882a593Smuzhiyun 	__mt76_tx_status_skb_done(dev, skb, MT_TX_CB_DMA_DONE, &list);
223*4882a593Smuzhiyun 	mt76_tx_status_unlock(dev, &list);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx_complete_skb);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static int
__mt76_tx_queue_skb(struct mt76_dev * dev,int qid,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_sta * sta,bool * stop)228*4882a593Smuzhiyun __mt76_tx_queue_skb(struct mt76_dev *dev, int qid, struct sk_buff *skb,
229*4882a593Smuzhiyun 		    struct mt76_wcid *wcid, struct ieee80211_sta *sta,
230*4882a593Smuzhiyun 		    bool *stop)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
233*4882a593Smuzhiyun 	struct mt76_queue *q;
234*4882a593Smuzhiyun 	bool non_aql;
235*4882a593Smuzhiyun 	int pending;
236*4882a593Smuzhiyun 	int idx;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	non_aql = !info->tx_time_est;
239*4882a593Smuzhiyun 	idx = dev->queue_ops->tx_queue_skb(dev, qid, skb, wcid, sta);
240*4882a593Smuzhiyun 	if (idx < 0 || !sta || !non_aql)
241*4882a593Smuzhiyun 		return idx;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	wcid = (struct mt76_wcid *)sta->drv_priv;
244*4882a593Smuzhiyun 	q = dev->q_tx[qid];
245*4882a593Smuzhiyun 	q->entry[idx].wcid = wcid->idx;
246*4882a593Smuzhiyun 	pending = atomic_inc_return(&wcid->non_aql_packets);
247*4882a593Smuzhiyun 	if (stop && pending >= MT_MAX_NON_AQL_PKT)
248*4882a593Smuzhiyun 		*stop = true;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	return idx;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun void
mt76_tx(struct mt76_phy * phy,struct ieee80211_sta * sta,struct mt76_wcid * wcid,struct sk_buff * skb)254*4882a593Smuzhiyun mt76_tx(struct mt76_phy *phy, struct ieee80211_sta *sta,
255*4882a593Smuzhiyun 	struct mt76_wcid *wcid, struct sk_buff *skb)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	struct mt76_dev *dev = phy->dev;
258*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
259*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
260*4882a593Smuzhiyun 	struct mt76_queue *q;
261*4882a593Smuzhiyun 	int qid = skb_get_queue_mapping(skb);
262*4882a593Smuzhiyun 	bool ext_phy = phy != &dev->phy;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	if (mt76_testmode_enabled(dev)) {
265*4882a593Smuzhiyun 		ieee80211_free_txskb(phy->hw, skb);
266*4882a593Smuzhiyun 		return;
267*4882a593Smuzhiyun 	}
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	if (WARN_ON(qid >= MT_TXQ_PSD)) {
270*4882a593Smuzhiyun 		qid = MT_TXQ_BE;
271*4882a593Smuzhiyun 		skb_set_queue_mapping(skb, qid);
272*4882a593Smuzhiyun 	}
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	if ((dev->drv->drv_flags & MT_DRV_HW_MGMT_TXQ) &&
275*4882a593Smuzhiyun 	    !ieee80211_is_data(hdr->frame_control) &&
276*4882a593Smuzhiyun 	    !ieee80211_is_bufferable_mmpdu(hdr->frame_control)) {
277*4882a593Smuzhiyun 		qid = MT_TXQ_PSD;
278*4882a593Smuzhiyun 		skb_set_queue_mapping(skb, qid);
279*4882a593Smuzhiyun 	}
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	if (wcid && !(wcid->tx_info & MT_WCID_TX_INFO_SET))
282*4882a593Smuzhiyun 		ieee80211_get_tx_rates(info->control.vif, sta, skb,
283*4882a593Smuzhiyun 				       info->control.rates, 1);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	if (ext_phy)
286*4882a593Smuzhiyun 		info->hw_queue |= MT_TX_HW_QUEUE_EXT_PHY;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	q = dev->q_tx[qid];
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	spin_lock_bh(&q->lock);
291*4882a593Smuzhiyun 	__mt76_tx_queue_skb(dev, qid, skb, wcid, sta, NULL);
292*4882a593Smuzhiyun 	dev->queue_ops->kick(dev, q);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	if (q->queued > q->ndesc - 8 && !q->stopped) {
295*4882a593Smuzhiyun 		ieee80211_stop_queue(phy->hw, skb_get_queue_mapping(skb));
296*4882a593Smuzhiyun 		q->stopped = true;
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	spin_unlock_bh(&q->lock);
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_tx);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun static struct sk_buff *
mt76_txq_dequeue(struct mt76_phy * phy,struct mt76_txq * mtxq)304*4882a593Smuzhiyun mt76_txq_dequeue(struct mt76_phy *phy, struct mt76_txq *mtxq)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun 	struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
307*4882a593Smuzhiyun 	struct ieee80211_tx_info *info;
308*4882a593Smuzhiyun 	bool ext_phy = phy != &phy->dev->phy;
309*4882a593Smuzhiyun 	struct sk_buff *skb;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	skb = ieee80211_tx_dequeue(phy->hw, txq);
312*4882a593Smuzhiyun 	if (!skb)
313*4882a593Smuzhiyun 		return NULL;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	info = IEEE80211_SKB_CB(skb);
316*4882a593Smuzhiyun 	if (ext_phy)
317*4882a593Smuzhiyun 		info->hw_queue |= MT_TX_HW_QUEUE_EXT_PHY;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	return skb;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun static void
mt76_queue_ps_skb(struct mt76_dev * dev,struct ieee80211_sta * sta,struct sk_buff * skb,bool last)323*4882a593Smuzhiyun mt76_queue_ps_skb(struct mt76_dev *dev, struct ieee80211_sta *sta,
324*4882a593Smuzhiyun 		  struct sk_buff *skb, bool last)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv;
327*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	info->control.flags |= IEEE80211_TX_CTRL_PS_RESPONSE;
330*4882a593Smuzhiyun 	if (last)
331*4882a593Smuzhiyun 		info->flags |= IEEE80211_TX_STATUS_EOSP |
332*4882a593Smuzhiyun 			       IEEE80211_TX_CTL_REQ_TX_STATUS;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	mt76_skb_set_moredata(skb, !last);
335*4882a593Smuzhiyun 	__mt76_tx_queue_skb(dev, MT_TXQ_PSD, skb, wcid, sta, NULL);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun void
mt76_release_buffered_frames(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u16 tids,int nframes,enum ieee80211_frame_release_type reason,bool more_data)339*4882a593Smuzhiyun mt76_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
340*4882a593Smuzhiyun 			     u16 tids, int nframes,
341*4882a593Smuzhiyun 			     enum ieee80211_frame_release_type reason,
342*4882a593Smuzhiyun 			     bool more_data)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun 	struct mt76_phy *phy = hw->priv;
345*4882a593Smuzhiyun 	struct mt76_dev *dev = phy->dev;
346*4882a593Smuzhiyun 	struct sk_buff *last_skb = NULL;
347*4882a593Smuzhiyun 	struct mt76_queue *hwq = dev->q_tx[MT_TXQ_PSD];
348*4882a593Smuzhiyun 	int i;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	spin_lock_bh(&hwq->lock);
351*4882a593Smuzhiyun 	for (i = 0; tids && nframes; i++, tids >>= 1) {
352*4882a593Smuzhiyun 		struct ieee80211_txq *txq = sta->txq[i];
353*4882a593Smuzhiyun 		struct mt76_txq *mtxq = (struct mt76_txq *)txq->drv_priv;
354*4882a593Smuzhiyun 		struct sk_buff *skb;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 		if (!(tids & 1))
357*4882a593Smuzhiyun 			continue;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 		do {
360*4882a593Smuzhiyun 			skb = mt76_txq_dequeue(phy, mtxq);
361*4882a593Smuzhiyun 			if (!skb)
362*4882a593Smuzhiyun 				break;
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 			nframes--;
365*4882a593Smuzhiyun 			if (last_skb)
366*4882a593Smuzhiyun 				mt76_queue_ps_skb(dev, sta, last_skb, false);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 			last_skb = skb;
369*4882a593Smuzhiyun 		} while (nframes);
370*4882a593Smuzhiyun 	}
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	if (last_skb) {
373*4882a593Smuzhiyun 		mt76_queue_ps_skb(dev, sta, last_skb, true);
374*4882a593Smuzhiyun 		dev->queue_ops->kick(dev, hwq);
375*4882a593Smuzhiyun 	} else {
376*4882a593Smuzhiyun 		ieee80211_sta_eosp(sta);
377*4882a593Smuzhiyun 	}
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	spin_unlock_bh(&hwq->lock);
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_release_buffered_frames);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun static int
mt76_txq_send_burst(struct mt76_phy * phy,struct mt76_queue * q,struct mt76_txq * mtxq)384*4882a593Smuzhiyun mt76_txq_send_burst(struct mt76_phy *phy, struct mt76_queue *q,
385*4882a593Smuzhiyun 		    struct mt76_txq *mtxq)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun 	struct mt76_dev *dev = phy->dev;
388*4882a593Smuzhiyun 	struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
389*4882a593Smuzhiyun 	enum mt76_txq_id qid = mt76_txq_get_qid(txq);
390*4882a593Smuzhiyun 	struct mt76_wcid *wcid = mtxq->wcid;
391*4882a593Smuzhiyun 	struct ieee80211_tx_info *info;
392*4882a593Smuzhiyun 	struct sk_buff *skb;
393*4882a593Smuzhiyun 	int n_frames = 1;
394*4882a593Smuzhiyun 	bool stop = false;
395*4882a593Smuzhiyun 	int idx;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	if (test_bit(MT_WCID_FLAG_PS, &wcid->flags))
398*4882a593Smuzhiyun 		return 0;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	if (atomic_read(&wcid->non_aql_packets) >= MT_MAX_NON_AQL_PKT)
401*4882a593Smuzhiyun 		return 0;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	skb = mt76_txq_dequeue(phy, mtxq);
404*4882a593Smuzhiyun 	if (!skb)
405*4882a593Smuzhiyun 		return 0;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	info = IEEE80211_SKB_CB(skb);
408*4882a593Smuzhiyun 	if (!(wcid->tx_info & MT_WCID_TX_INFO_SET))
409*4882a593Smuzhiyun 		ieee80211_get_tx_rates(txq->vif, txq->sta, skb,
410*4882a593Smuzhiyun 				       info->control.rates, 1);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	idx = __mt76_tx_queue_skb(dev, qid, skb, wcid, txq->sta, &stop);
413*4882a593Smuzhiyun 	if (idx < 0)
414*4882a593Smuzhiyun 		return idx;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	do {
417*4882a593Smuzhiyun 		if (test_bit(MT76_STATE_PM, &phy->state) ||
418*4882a593Smuzhiyun 		    test_bit(MT76_RESET, &phy->state))
419*4882a593Smuzhiyun 			return -EBUSY;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 		if (stop)
422*4882a593Smuzhiyun 			break;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 		if (q->queued + MT_TXQ_FREE_THR >= q->ndesc)
425*4882a593Smuzhiyun 			break;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 		skb = mt76_txq_dequeue(phy, mtxq);
428*4882a593Smuzhiyun 		if (!skb)
429*4882a593Smuzhiyun 			break;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 		info = IEEE80211_SKB_CB(skb);
432*4882a593Smuzhiyun 		if (!(wcid->tx_info & MT_WCID_TX_INFO_SET))
433*4882a593Smuzhiyun 			ieee80211_get_tx_rates(txq->vif, txq->sta, skb,
434*4882a593Smuzhiyun 					       info->control.rates, 1);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 		idx = __mt76_tx_queue_skb(dev, qid, skb, wcid, txq->sta, &stop);
437*4882a593Smuzhiyun 		if (idx < 0)
438*4882a593Smuzhiyun 			break;
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 		n_frames++;
441*4882a593Smuzhiyun 	} while (1);
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	dev->queue_ops->kick(dev, q);
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	return n_frames;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun static int
mt76_txq_schedule_list(struct mt76_phy * phy,enum mt76_txq_id qid)449*4882a593Smuzhiyun mt76_txq_schedule_list(struct mt76_phy *phy, enum mt76_txq_id qid)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	struct mt76_dev *dev = phy->dev;
452*4882a593Smuzhiyun 	struct mt76_queue *q = dev->q_tx[qid];
453*4882a593Smuzhiyun 	struct ieee80211_txq *txq;
454*4882a593Smuzhiyun 	struct mt76_txq *mtxq;
455*4882a593Smuzhiyun 	struct mt76_wcid *wcid;
456*4882a593Smuzhiyun 	int ret = 0;
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	spin_lock_bh(&q->lock);
459*4882a593Smuzhiyun 	while (1) {
460*4882a593Smuzhiyun 		if (test_bit(MT76_STATE_PM, &phy->state) ||
461*4882a593Smuzhiyun 		    test_bit(MT76_RESET, &phy->state)) {
462*4882a593Smuzhiyun 			ret = -EBUSY;
463*4882a593Smuzhiyun 			break;
464*4882a593Smuzhiyun 		}
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 		if (q->queued + MT_TXQ_FREE_THR >= q->ndesc)
467*4882a593Smuzhiyun 			break;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 		txq = ieee80211_next_txq(phy->hw, qid);
470*4882a593Smuzhiyun 		if (!txq)
471*4882a593Smuzhiyun 			break;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 		mtxq = (struct mt76_txq *)txq->drv_priv;
474*4882a593Smuzhiyun 		wcid = mtxq->wcid;
475*4882a593Smuzhiyun 		if (wcid && test_bit(MT_WCID_FLAG_PS, &wcid->flags))
476*4882a593Smuzhiyun 			continue;
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 		if (mtxq->send_bar && mtxq->aggr) {
479*4882a593Smuzhiyun 			struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
480*4882a593Smuzhiyun 			struct ieee80211_sta *sta = txq->sta;
481*4882a593Smuzhiyun 			struct ieee80211_vif *vif = txq->vif;
482*4882a593Smuzhiyun 			u16 agg_ssn = mtxq->agg_ssn;
483*4882a593Smuzhiyun 			u8 tid = txq->tid;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 			mtxq->send_bar = false;
486*4882a593Smuzhiyun 			spin_unlock_bh(&q->lock);
487*4882a593Smuzhiyun 			ieee80211_send_bar(vif, sta->addr, tid, agg_ssn);
488*4882a593Smuzhiyun 			spin_lock_bh(&q->lock);
489*4882a593Smuzhiyun 		}
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 		ret += mt76_txq_send_burst(phy, q, mtxq);
492*4882a593Smuzhiyun 		ieee80211_return_txq(phy->hw, txq, false);
493*4882a593Smuzhiyun 	}
494*4882a593Smuzhiyun 	spin_unlock_bh(&q->lock);
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	return ret;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun 
mt76_txq_schedule(struct mt76_phy * phy,enum mt76_txq_id qid)499*4882a593Smuzhiyun void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid)
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun 	int len;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	if (qid >= 4)
504*4882a593Smuzhiyun 		return;
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	rcu_read_lock();
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	do {
509*4882a593Smuzhiyun 		ieee80211_txq_schedule_start(phy->hw, qid);
510*4882a593Smuzhiyun 		len = mt76_txq_schedule_list(phy, qid);
511*4882a593Smuzhiyun 		ieee80211_txq_schedule_end(phy->hw, qid);
512*4882a593Smuzhiyun 	} while (len > 0);
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	rcu_read_unlock();
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_txq_schedule);
517*4882a593Smuzhiyun 
mt76_txq_schedule_all(struct mt76_phy * phy)518*4882a593Smuzhiyun void mt76_txq_schedule_all(struct mt76_phy *phy)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun 	int i;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	for (i = 0; i <= MT_TXQ_BK; i++)
523*4882a593Smuzhiyun 		mt76_txq_schedule(phy, i);
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_txq_schedule_all);
526*4882a593Smuzhiyun 
mt76_tx_worker(struct mt76_worker * w)527*4882a593Smuzhiyun void mt76_tx_worker(struct mt76_worker *w)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	struct mt76_dev *dev = container_of(w, struct mt76_dev, tx_worker);
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	mt76_txq_schedule_all(&dev->phy);
532*4882a593Smuzhiyun 	if (dev->phy2)
533*4882a593Smuzhiyun 		mt76_txq_schedule_all(dev->phy2);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun #ifdef CONFIG_NL80211_TESTMODE
536*4882a593Smuzhiyun 	if (dev->test.tx_pending)
537*4882a593Smuzhiyun 		mt76_testmode_tx_pending(dev);
538*4882a593Smuzhiyun #endif
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
mt76_stop_tx_queues(struct mt76_dev * dev,struct ieee80211_sta * sta,bool send_bar)541*4882a593Smuzhiyun void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta,
542*4882a593Smuzhiyun 			 bool send_bar)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun 	int i;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(sta->txq); i++) {
547*4882a593Smuzhiyun 		struct ieee80211_txq *txq = sta->txq[i];
548*4882a593Smuzhiyun 		struct mt76_queue *hwq;
549*4882a593Smuzhiyun 		struct mt76_txq *mtxq;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 		if (!txq)
552*4882a593Smuzhiyun 			continue;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 		hwq = dev->q_tx[mt76_txq_get_qid(txq)];
555*4882a593Smuzhiyun 		mtxq = (struct mt76_txq *)txq->drv_priv;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 		spin_lock_bh(&hwq->lock);
558*4882a593Smuzhiyun 		mtxq->send_bar = mtxq->aggr && send_bar;
559*4882a593Smuzhiyun 		spin_unlock_bh(&hwq->lock);
560*4882a593Smuzhiyun 	}
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_stop_tx_queues);
563*4882a593Smuzhiyun 
mt76_wake_tx_queue(struct ieee80211_hw * hw,struct ieee80211_txq * txq)564*4882a593Smuzhiyun void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun 	struct mt76_phy *phy = hw->priv;
567*4882a593Smuzhiyun 	struct mt76_dev *dev = phy->dev;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	if (!test_bit(MT76_STATE_RUNNING, &phy->state))
570*4882a593Smuzhiyun 		return;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	mt76_worker_schedule(&dev->tx_worker);
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_wake_tx_queue);
575*4882a593Smuzhiyun 
mt76_ac_to_hwq(u8 ac)576*4882a593Smuzhiyun u8 mt76_ac_to_hwq(u8 ac)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	static const u8 wmm_queue_map[] = {
579*4882a593Smuzhiyun 		[IEEE80211_AC_BE] = 0,
580*4882a593Smuzhiyun 		[IEEE80211_AC_BK] = 1,
581*4882a593Smuzhiyun 		[IEEE80211_AC_VI] = 2,
582*4882a593Smuzhiyun 		[IEEE80211_AC_VO] = 3,
583*4882a593Smuzhiyun 	};
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	if (WARN_ON(ac >= IEEE80211_NUM_ACS))
586*4882a593Smuzhiyun 		return 0;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	return wmm_queue_map[ac];
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_ac_to_hwq);
591*4882a593Smuzhiyun 
mt76_skb_adjust_pad(struct sk_buff * skb,int pad)592*4882a593Smuzhiyun int mt76_skb_adjust_pad(struct sk_buff *skb, int pad)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun 	struct sk_buff *iter, *last = skb;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	/* First packet of a A-MSDU burst keeps track of the whole burst
597*4882a593Smuzhiyun 	 * length, need to update length of it and the last packet.
598*4882a593Smuzhiyun 	 */
599*4882a593Smuzhiyun 	skb_walk_frags(skb, iter) {
600*4882a593Smuzhiyun 		last = iter;
601*4882a593Smuzhiyun 		if (!iter->next) {
602*4882a593Smuzhiyun 			skb->data_len += pad;
603*4882a593Smuzhiyun 			skb->len += pad;
604*4882a593Smuzhiyun 			break;
605*4882a593Smuzhiyun 		}
606*4882a593Smuzhiyun 	}
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	if (skb_pad(last, pad))
609*4882a593Smuzhiyun 		return -ENOMEM;
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	__skb_put(last, pad);
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	return 0;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_skb_adjust_pad);
616*4882a593Smuzhiyun 
mt76_queue_tx_complete(struct mt76_dev * dev,struct mt76_queue * q,struct mt76_queue_entry * e)617*4882a593Smuzhiyun void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
618*4882a593Smuzhiyun 			    struct mt76_queue_entry *e)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun 	if (e->skb)
621*4882a593Smuzhiyun 		dev->drv->tx_complete_skb(dev, e);
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	spin_lock_bh(&q->lock);
624*4882a593Smuzhiyun 	q->tail = (q->tail + 1) % q->ndesc;
625*4882a593Smuzhiyun 	q->queued--;
626*4882a593Smuzhiyun 	spin_unlock_bh(&q->lock);
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_queue_tx_complete);
629