xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */
2*4882a593Smuzhiyun /* Copyright (C) 2020 MediaTek Inc. */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #ifndef __MT7915_H
5*4882a593Smuzhiyun #define __MT7915_H
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/interrupt.h>
8*4882a593Smuzhiyun #include <linux/ktime.h>
9*4882a593Smuzhiyun #include "../mt76.h"
10*4882a593Smuzhiyun #include "regs.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define MT7915_MAX_INTERFACES		4
13*4882a593Smuzhiyun #define MT7915_MAX_WMM_SETS		4
14*4882a593Smuzhiyun #define MT7915_WTBL_SIZE		288
15*4882a593Smuzhiyun #define MT7915_WTBL_RESERVED		(MT7915_WTBL_SIZE - 1)
16*4882a593Smuzhiyun #define MT7915_WTBL_STA			(MT7915_WTBL_RESERVED - \
17*4882a593Smuzhiyun 					 MT7915_MAX_INTERFACES)
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define MT7915_WATCHDOG_TIME		(HZ / 10)
20*4882a593Smuzhiyun #define MT7915_RESET_TIMEOUT		(30 * HZ)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define MT7915_TX_RING_SIZE		2048
23*4882a593Smuzhiyun #define MT7915_TX_MCU_RING_SIZE		256
24*4882a593Smuzhiyun #define MT7915_TX_FWDL_RING_SIZE	128
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define MT7915_RX_RING_SIZE		1536
27*4882a593Smuzhiyun #define MT7915_RX_MCU_RING_SIZE		512
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define MT7915_FIRMWARE_WA		"mediatek/mt7915_wa.bin"
30*4882a593Smuzhiyun #define MT7915_FIRMWARE_WM		"mediatek/mt7915_wm.bin"
31*4882a593Smuzhiyun #define MT7915_ROM_PATCH		"mediatek/mt7915_rom_patch.bin"
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define MT7915_EEPROM_SIZE		3584
34*4882a593Smuzhiyun #define MT7915_TOKEN_SIZE		8192
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MT7915_CFEND_RATE_DEFAULT	0x49	/* OFDM 24M */
37*4882a593Smuzhiyun #define MT7915_CFEND_RATE_11B		0x03	/* 11B LP, 11M */
38*4882a593Smuzhiyun #define MT7915_5G_RATE_DEFAULT		0x4b	/* OFDM 6M */
39*4882a593Smuzhiyun #define MT7915_2G_RATE_DEFAULT		0x0	/* CCK 1M */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define MT7915_SKU_RATE_NUM		161
42*4882a593Smuzhiyun #define MT7915_SKU_MAX_DELTA_IDX	MT7915_SKU_RATE_NUM
43*4882a593Smuzhiyun #define MT7915_SKU_TABLE_SIZE		(MT7915_SKU_RATE_NUM + 1)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun struct mt7915_vif;
46*4882a593Smuzhiyun struct mt7915_sta;
47*4882a593Smuzhiyun struct mt7915_dfs_pulse;
48*4882a593Smuzhiyun struct mt7915_dfs_pattern;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun enum mt7915_txq_id {
51*4882a593Smuzhiyun 	MT7915_TXQ_FWDL = 16,
52*4882a593Smuzhiyun 	MT7915_TXQ_MCU_WM,
53*4882a593Smuzhiyun 	MT7915_TXQ_BAND0,
54*4882a593Smuzhiyun 	MT7915_TXQ_BAND1,
55*4882a593Smuzhiyun 	MT7915_TXQ_MCU_WA,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun enum mt7915_rxq_id {
59*4882a593Smuzhiyun 	MT7915_RXQ_BAND0 = 0,
60*4882a593Smuzhiyun 	MT7915_RXQ_BAND1,
61*4882a593Smuzhiyun 	MT7915_RXQ_MCU_WM = 0,
62*4882a593Smuzhiyun 	MT7915_RXQ_MCU_WA,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun struct mt7915_sta_stats {
66*4882a593Smuzhiyun 	struct rate_info prob_rate;
67*4882a593Smuzhiyun 	struct rate_info tx_rate;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	unsigned long per;
70*4882a593Smuzhiyun 	unsigned long changed;
71*4882a593Smuzhiyun 	unsigned long jiffies;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct mt7915_sta {
75*4882a593Smuzhiyun 	struct mt76_wcid wcid; /* must be first */
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	struct mt7915_vif *vif;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	struct list_head stats_list;
80*4882a593Smuzhiyun 	struct list_head poll_list;
81*4882a593Smuzhiyun 	struct list_head rc_list;
82*4882a593Smuzhiyun 	u32 airtime_ac[8];
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	struct mt7915_sta_stats stats;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	unsigned long ampdu_state;
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun struct mt7915_vif {
90*4882a593Smuzhiyun 	u16 idx;
91*4882a593Smuzhiyun 	u8 omac_idx;
92*4882a593Smuzhiyun 	u8 band_idx;
93*4882a593Smuzhiyun 	u8 wmm_idx;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	struct mt7915_sta sta;
96*4882a593Smuzhiyun 	struct mt7915_phy *phy;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct mib_stats {
102*4882a593Smuzhiyun 	u32 ack_fail_cnt;
103*4882a593Smuzhiyun 	u32 fcs_err_cnt;
104*4882a593Smuzhiyun 	u32 rts_cnt;
105*4882a593Smuzhiyun 	u32 rts_retries_cnt;
106*4882a593Smuzhiyun 	u32 ba_miss_cnt;
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun struct mt7915_phy {
110*4882a593Smuzhiyun 	struct mt76_phy *mt76;
111*4882a593Smuzhiyun 	struct mt7915_dev *dev;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	struct ieee80211_sband_iftype_data iftype[2][NUM_NL80211_IFTYPES];
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	u32 rxfilter;
116*4882a593Smuzhiyun 	u32 omac_mask;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	u16 noise;
119*4882a593Smuzhiyun 	u16 chainmask;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	s16 coverage_class;
122*4882a593Smuzhiyun 	u8 slottime;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	u8 rdd_state;
125*4882a593Smuzhiyun 	int dfs_state;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	__le32 rx_ampdu_ts;
128*4882a593Smuzhiyun 	u32 ampdu_ref;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	struct mib_stats mib;
131*4882a593Smuzhiyun 	struct list_head stats_list;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	struct delayed_work mac_work;
134*4882a593Smuzhiyun 	u8 mac_work_count;
135*4882a593Smuzhiyun 	u8 sta_work_count;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun struct mt7915_dev {
139*4882a593Smuzhiyun 	union { /* must be first */
140*4882a593Smuzhiyun 		struct mt76_dev mt76;
141*4882a593Smuzhiyun 		struct mt76_phy mphy;
142*4882a593Smuzhiyun 	};
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	const struct mt76_bus_ops *bus_ops;
145*4882a593Smuzhiyun 	struct mt7915_phy phy;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	u16 chainmask;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	struct work_struct init_work;
150*4882a593Smuzhiyun 	struct work_struct rc_work;
151*4882a593Smuzhiyun 	struct work_struct reset_work;
152*4882a593Smuzhiyun 	wait_queue_head_t reset_wait;
153*4882a593Smuzhiyun 	u32 reset_state;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	struct list_head sta_rc_list;
156*4882a593Smuzhiyun 	struct list_head sta_poll_list;
157*4882a593Smuzhiyun 	spinlock_t sta_poll_lock;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	u32 hw_pattern;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	spinlock_t token_lock;
162*4882a593Smuzhiyun 	struct idr token;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	s8 **rate_power; /* TODO: use mt76_rate_power */
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	bool fw_debug;
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun enum {
170*4882a593Smuzhiyun 	HW_BSSID_0 = 0x0,
171*4882a593Smuzhiyun 	HW_BSSID_1,
172*4882a593Smuzhiyun 	HW_BSSID_2,
173*4882a593Smuzhiyun 	HW_BSSID_3,
174*4882a593Smuzhiyun 	HW_BSSID_MAX,
175*4882a593Smuzhiyun 	EXT_BSSID_START = 0x10,
176*4882a593Smuzhiyun 	EXT_BSSID_1,
177*4882a593Smuzhiyun 	EXT_BSSID_2,
178*4882a593Smuzhiyun 	EXT_BSSID_3,
179*4882a593Smuzhiyun 	EXT_BSSID_4,
180*4882a593Smuzhiyun 	EXT_BSSID_5,
181*4882a593Smuzhiyun 	EXT_BSSID_6,
182*4882a593Smuzhiyun 	EXT_BSSID_7,
183*4882a593Smuzhiyun 	EXT_BSSID_8,
184*4882a593Smuzhiyun 	EXT_BSSID_9,
185*4882a593Smuzhiyun 	EXT_BSSID_10,
186*4882a593Smuzhiyun 	EXT_BSSID_11,
187*4882a593Smuzhiyun 	EXT_BSSID_12,
188*4882a593Smuzhiyun 	EXT_BSSID_13,
189*4882a593Smuzhiyun 	EXT_BSSID_14,
190*4882a593Smuzhiyun 	EXT_BSSID_15,
191*4882a593Smuzhiyun 	EXT_BSSID_END
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun enum {
195*4882a593Smuzhiyun 	MT_LMAC_AC00,
196*4882a593Smuzhiyun 	MT_LMAC_AC01,
197*4882a593Smuzhiyun 	MT_LMAC_AC02,
198*4882a593Smuzhiyun 	MT_LMAC_AC03,
199*4882a593Smuzhiyun 	MT_LMAC_ALTX0 = 0x10,
200*4882a593Smuzhiyun 	MT_LMAC_BMC0,
201*4882a593Smuzhiyun 	MT_LMAC_BCN0,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun enum {
205*4882a593Smuzhiyun 	MT_RX_SEL0,
206*4882a593Smuzhiyun 	MT_RX_SEL1,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun enum mt7915_rdd_cmd {
210*4882a593Smuzhiyun 	RDD_STOP,
211*4882a593Smuzhiyun 	RDD_START,
212*4882a593Smuzhiyun 	RDD_DET_MODE,
213*4882a593Smuzhiyun 	RDD_RADAR_EMULATE,
214*4882a593Smuzhiyun 	RDD_START_TXQ = 20,
215*4882a593Smuzhiyun 	RDD_CAC_START = 50,
216*4882a593Smuzhiyun 	RDD_CAC_END,
217*4882a593Smuzhiyun 	RDD_NORMAL_START,
218*4882a593Smuzhiyun 	RDD_DISABLE_DFS_CAL,
219*4882a593Smuzhiyun 	RDD_PULSE_DBG,
220*4882a593Smuzhiyun 	RDD_READ_PULSE,
221*4882a593Smuzhiyun 	RDD_RESUME_BF,
222*4882a593Smuzhiyun 	RDD_IRQ_OFF,
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun enum {
226*4882a593Smuzhiyun 	RATE_CTRL_RU_INFO,
227*4882a593Smuzhiyun 	RATE_CTRL_FIXED_RATE_INFO,
228*4882a593Smuzhiyun 	RATE_CTRL_DUMP_INFO,
229*4882a593Smuzhiyun 	RATE_CTRL_MU_INFO,
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static inline struct mt7915_phy *
mt7915_hw_phy(struct ieee80211_hw * hw)233*4882a593Smuzhiyun mt7915_hw_phy(struct ieee80211_hw *hw)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	struct mt76_phy *phy = hw->priv;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	return phy->priv;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun static inline struct mt7915_dev *
mt7915_hw_dev(struct ieee80211_hw * hw)241*4882a593Smuzhiyun mt7915_hw_dev(struct ieee80211_hw *hw)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	struct mt76_phy *phy = hw->priv;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	return container_of(phy->dev, struct mt7915_dev, mt76);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun static inline struct mt7915_phy *
mt7915_ext_phy(struct mt7915_dev * dev)249*4882a593Smuzhiyun mt7915_ext_phy(struct mt7915_dev *dev)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	struct mt76_phy *phy = dev->mt76.phy2;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	if (!phy)
254*4882a593Smuzhiyun 		return NULL;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	return phy->priv;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
mt7915_lmac_mapping(struct mt7915_dev * dev,u8 ac)259*4882a593Smuzhiyun static inline u8 mt7915_lmac_mapping(struct mt7915_dev *dev, u8 ac)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	/* LMAC uses the reverse order of mac80211 AC indexes */
262*4882a593Smuzhiyun 	return 3 - ac;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun extern const struct ieee80211_ops mt7915_ops;
266*4882a593Smuzhiyun extern struct pci_driver mt7915_pci_driver;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun u32 mt7915_reg_map(struct mt7915_dev *dev, u32 addr);
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun int mt7915_register_device(struct mt7915_dev *dev);
271*4882a593Smuzhiyun void mt7915_unregister_device(struct mt7915_dev *dev);
272*4882a593Smuzhiyun int mt7915_register_ext_phy(struct mt7915_dev *dev);
273*4882a593Smuzhiyun void mt7915_unregister_ext_phy(struct mt7915_dev *dev);
274*4882a593Smuzhiyun int mt7915_eeprom_init(struct mt7915_dev *dev);
275*4882a593Smuzhiyun u32 mt7915_eeprom_read(struct mt7915_dev *dev, u32 offset);
276*4882a593Smuzhiyun int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
277*4882a593Smuzhiyun 				   struct ieee80211_channel *chan,
278*4882a593Smuzhiyun 				   u8 chain_idx);
279*4882a593Smuzhiyun void mt7915_eeprom_init_sku(struct mt7915_dev *dev);
280*4882a593Smuzhiyun int mt7915_dma_init(struct mt7915_dev *dev);
281*4882a593Smuzhiyun void mt7915_dma_prefetch(struct mt7915_dev *dev);
282*4882a593Smuzhiyun void mt7915_dma_cleanup(struct mt7915_dev *dev);
283*4882a593Smuzhiyun int mt7915_mcu_init(struct mt7915_dev *dev);
284*4882a593Smuzhiyun int mt7915_mcu_add_dev_info(struct mt7915_dev *dev,
285*4882a593Smuzhiyun 			    struct ieee80211_vif *vif, bool enable);
286*4882a593Smuzhiyun int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
287*4882a593Smuzhiyun 			    struct ieee80211_vif *vif, int enable);
288*4882a593Smuzhiyun int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
289*4882a593Smuzhiyun 		       struct ieee80211_sta *sta, bool enable);
290*4882a593Smuzhiyun int mt7915_mcu_add_sta_adv(struct mt7915_dev *dev, struct ieee80211_vif *vif,
291*4882a593Smuzhiyun 			   struct ieee80211_sta *sta, bool enable);
292*4882a593Smuzhiyun int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,
293*4882a593Smuzhiyun 			 struct ieee80211_ampdu_params *params,
294*4882a593Smuzhiyun 			 bool add);
295*4882a593Smuzhiyun int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,
296*4882a593Smuzhiyun 			 struct ieee80211_ampdu_params *params,
297*4882a593Smuzhiyun 			 bool add);
298*4882a593Smuzhiyun int mt7915_mcu_add_key(struct mt7915_dev *dev, struct ieee80211_vif *vif,
299*4882a593Smuzhiyun 		       struct mt7915_sta *msta, struct ieee80211_key_conf *key,
300*4882a593Smuzhiyun 		       enum set_key_cmd cmd);
301*4882a593Smuzhiyun int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
302*4882a593Smuzhiyun 			  int enable);
303*4882a593Smuzhiyun int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif,
304*4882a593Smuzhiyun                             bool enable);
305*4882a593Smuzhiyun int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,
306*4882a593Smuzhiyun 			     struct ieee80211_sta *sta);
307*4882a593Smuzhiyun int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,
308*4882a593Smuzhiyun 			struct ieee80211_sta *sta);
309*4882a593Smuzhiyun int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd);
310*4882a593Smuzhiyun int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif);
311*4882a593Smuzhiyun int mt7915_mcu_set_fixed_rate(struct mt7915_dev *dev,
312*4882a593Smuzhiyun 			      struct ieee80211_sta *sta, u32 rate);
313*4882a593Smuzhiyun int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
314*4882a593Smuzhiyun int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
315*4882a593Smuzhiyun int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
316*4882a593Smuzhiyun 		       bool hdr_trans);
317*4882a593Smuzhiyun int mt7915_mcu_set_scs(struct mt7915_dev *dev, u8 band, bool enable);
318*4882a593Smuzhiyun int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band);
319*4882a593Smuzhiyun int mt7915_mcu_set_rts_thresh(struct mt7915_phy *phy, u32 val);
320*4882a593Smuzhiyun int mt7915_mcu_set_pm(struct mt7915_dev *dev, int band, int enter);
321*4882a593Smuzhiyun int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable);
322*4882a593Smuzhiyun int mt7915_mcu_set_sku(struct mt7915_phy *phy);
323*4882a593Smuzhiyun int mt7915_mcu_set_txbf_type(struct mt7915_dev *dev);
324*4882a593Smuzhiyun int mt7915_mcu_set_txbf_sounding(struct mt7915_dev *dev);
325*4882a593Smuzhiyun int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val);
326*4882a593Smuzhiyun int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,
327*4882a593Smuzhiyun 			    const struct mt7915_dfs_pulse *pulse);
328*4882a593Smuzhiyun int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,
329*4882a593Smuzhiyun 			    const struct mt7915_dfs_pattern *pattern);
330*4882a593Smuzhiyun int mt7915_mcu_get_rate_info(struct mt7915_dev *dev, u32 cmd, u16 wlan_idx);
331*4882a593Smuzhiyun int mt7915_mcu_get_temperature(struct mt7915_dev *dev, int index);
332*4882a593Smuzhiyun int mt7915_mcu_rdd_cmd(struct mt7915_dev *dev, enum mt7915_rdd_cmd cmd,
333*4882a593Smuzhiyun 		       u8 index, u8 rx_sel, u8 val);
334*4882a593Smuzhiyun int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 ctrl);
335*4882a593Smuzhiyun int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
336*4882a593Smuzhiyun void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
337*4882a593Smuzhiyun void mt7915_mcu_exit(struct mt7915_dev *dev);
338*4882a593Smuzhiyun 
is_mt7915(struct mt76_dev * dev)339*4882a593Smuzhiyun static inline bool is_mt7915(struct mt76_dev *dev)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	return mt76_chip(dev) == 0x7915;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun 
mt7915_irq_enable(struct mt7915_dev * dev,u32 mask)344*4882a593Smuzhiyun static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun 	mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
mt7915_irq_disable(struct mt7915_dev * dev,u32 mask)349*4882a593Smuzhiyun static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun 	mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun static inline u32
mt7915_reg_map_l1(struct mt7915_dev * dev,u32 addr)355*4882a593Smuzhiyun mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun 	u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
358*4882a593Smuzhiyun 	u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_HIF_REMAP_L1, MT_HIF_REMAP_L1_MASK, base);
361*4882a593Smuzhiyun 	/* use read to push write */
362*4882a593Smuzhiyun 	mt76_rr(dev, MT_HIF_REMAP_L1);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	return MT_HIF_REMAP_BASE_L1 + offset;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun static inline u32
mt7915_l1_rr(struct mt7915_dev * dev,u32 addr)368*4882a593Smuzhiyun mt7915_l1_rr(struct mt7915_dev *dev, u32 addr)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun 	return mt76_rr(dev, mt7915_reg_map_l1(dev, addr));
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun static inline void
mt7915_l1_wr(struct mt7915_dev * dev,u32 addr,u32 val)374*4882a593Smuzhiyun mt7915_l1_wr(struct mt7915_dev *dev, u32 addr, u32 val)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun 	mt76_wr(dev, mt7915_reg_map_l1(dev, addr), val);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun static inline u32
mt7915_l1_rmw(struct mt7915_dev * dev,u32 addr,u32 mask,u32 val)380*4882a593Smuzhiyun mt7915_l1_rmw(struct mt7915_dev *dev, u32 addr, u32 mask, u32 val)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	val |= mt7915_l1_rr(dev, addr) & ~mask;
383*4882a593Smuzhiyun 	mt7915_l1_wr(dev, addr, val);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	return val;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun #define mt7915_l1_set(dev, addr, val)	mt7915_l1_rmw(dev, addr, 0, val)
389*4882a593Smuzhiyun #define mt7915_l1_clear(dev, addr, val)	mt7915_l1_rmw(dev, addr, val, 0)
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun static inline u32
mt7915_reg_map_l2(struct mt7915_dev * dev,u32 addr)392*4882a593Smuzhiyun mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
395*4882a593Smuzhiyun 	u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_HIF_REMAP_L2, MT_HIF_REMAP_L2_MASK, base);
398*4882a593Smuzhiyun 	/* use read to push write */
399*4882a593Smuzhiyun 	mt76_rr(dev, MT_HIF_REMAP_L2);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	return MT_HIF_REMAP_BASE_L2 + offset;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun static inline u32
mt7915_l2_rr(struct mt7915_dev * dev,u32 addr)405*4882a593Smuzhiyun mt7915_l2_rr(struct mt7915_dev *dev, u32 addr)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun 	return mt76_rr(dev, mt7915_reg_map_l2(dev, addr));
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun static inline void
mt7915_l2_wr(struct mt7915_dev * dev,u32 addr,u32 val)411*4882a593Smuzhiyun mt7915_l2_wr(struct mt7915_dev *dev, u32 addr, u32 val)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun 	mt76_wr(dev, mt7915_reg_map_l2(dev, addr), val);
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun static inline u32
mt7915_l2_rmw(struct mt7915_dev * dev,u32 addr,u32 mask,u32 val)417*4882a593Smuzhiyun mt7915_l2_rmw(struct mt7915_dev *dev, u32 addr, u32 mask, u32 val)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun 	val |= mt7915_l2_rr(dev, addr) & ~mask;
420*4882a593Smuzhiyun 	mt7915_l2_wr(dev, addr, val);
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	return val;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun #define mt7915_l2_set(dev, addr, val)	mt7915_l2_rmw(dev, addr, 0, val)
426*4882a593Smuzhiyun #define mt7915_l2_clear(dev, addr, val)	mt7915_l2_rmw(dev, addr, val, 0)
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask);
429*4882a593Smuzhiyun void mt7915_mac_reset_counters(struct mt7915_phy *phy);
430*4882a593Smuzhiyun void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy);
431*4882a593Smuzhiyun void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
432*4882a593Smuzhiyun 			   struct sk_buff *skb, struct mt76_wcid *wcid,
433*4882a593Smuzhiyun 			   struct ieee80211_key_conf *key, bool beacon);
434*4882a593Smuzhiyun void mt7915_mac_set_timing(struct mt7915_phy *phy);
435*4882a593Smuzhiyun int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb);
436*4882a593Smuzhiyun void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb);
437*4882a593Smuzhiyun int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
438*4882a593Smuzhiyun 		       struct ieee80211_sta *sta);
439*4882a593Smuzhiyun void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
440*4882a593Smuzhiyun 			   struct ieee80211_sta *sta);
441*4882a593Smuzhiyun void mt7915_mac_work(struct work_struct *work);
442*4882a593Smuzhiyun void mt7915_mac_reset_work(struct work_struct *work);
443*4882a593Smuzhiyun void mt7915_mac_sta_rc_work(struct work_struct *work);
444*4882a593Smuzhiyun int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
445*4882a593Smuzhiyun 			  enum mt76_txq_id qid, struct mt76_wcid *wcid,
446*4882a593Smuzhiyun 			  struct ieee80211_sta *sta,
447*4882a593Smuzhiyun 			  struct mt76_tx_info *tx_info);
448*4882a593Smuzhiyun void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
449*4882a593Smuzhiyun void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
450*4882a593Smuzhiyun 			 struct sk_buff *skb);
451*4882a593Smuzhiyun void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
452*4882a593Smuzhiyun void mt7915_stats_work(struct work_struct *work);
453*4882a593Smuzhiyun void mt7915_txp_skb_unmap(struct mt76_dev *dev,
454*4882a593Smuzhiyun 			  struct mt76_txwi_cache *txwi);
455*4882a593Smuzhiyun int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force);
456*4882a593Smuzhiyun int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy);
457*4882a593Smuzhiyun void mt7915_set_stream_he_caps(struct mt7915_phy *phy);
458*4882a593Smuzhiyun void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy);
459*4882a593Smuzhiyun void mt7915_update_channel(struct mt76_dev *mdev);
460*4882a593Smuzhiyun int mt7915_init_debugfs(struct mt7915_dev *dev);
461*4882a593Smuzhiyun #ifdef CONFIG_MAC80211_DEBUGFS
462*4882a593Smuzhiyun void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
463*4882a593Smuzhiyun 			    struct ieee80211_sta *sta, struct dentry *dir);
464*4882a593Smuzhiyun #endif
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun #endif
467