xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */
2*4882a593Smuzhiyun /* Copyright (C) 2020 MediaTek Inc. */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #ifndef __MT7915_MCU_H
5*4882a593Smuzhiyun #define __MT7915_MCU_H
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun struct mt7915_mcu_txd {
8*4882a593Smuzhiyun 	__le32 txd[8];
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun 	__le16 len;
11*4882a593Smuzhiyun 	__le16 pq_id;
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun 	u8 cid;
14*4882a593Smuzhiyun 	u8 pkt_type;
15*4882a593Smuzhiyun 	u8 set_query; /* FW don't care */
16*4882a593Smuzhiyun 	u8 seq;
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 	u8 uc_d2b0_rev;
19*4882a593Smuzhiyun 	u8 ext_cid;
20*4882a593Smuzhiyun 	u8 s2d_index;
21*4882a593Smuzhiyun 	u8 ext_cid_ack;
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	u32 reserved[5];
24*4882a593Smuzhiyun } __packed __aligned(4);
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /* event table */
27*4882a593Smuzhiyun enum {
28*4882a593Smuzhiyun 	MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29*4882a593Smuzhiyun 	MCU_EVENT_FW_START = 0x01,
30*4882a593Smuzhiyun 	MCU_EVENT_GENERIC = 0x01,
31*4882a593Smuzhiyun 	MCU_EVENT_ACCESS_REG = 0x02,
32*4882a593Smuzhiyun 	MCU_EVENT_MT_PATCH_SEM = 0x04,
33*4882a593Smuzhiyun 	MCU_EVENT_CH_PRIVILEGE = 0x18,
34*4882a593Smuzhiyun 	MCU_EVENT_EXT = 0xed,
35*4882a593Smuzhiyun 	MCU_EVENT_RESTART_DL = 0xef,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* ext event table */
39*4882a593Smuzhiyun enum {
40*4882a593Smuzhiyun 	MCU_EXT_EVENT_PS_SYNC = 0x5,
41*4882a593Smuzhiyun 	MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42*4882a593Smuzhiyun 	MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43*4882a593Smuzhiyun 	MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44*4882a593Smuzhiyun 	MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45*4882a593Smuzhiyun 	MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46*4882a593Smuzhiyun 	MCU_EXT_EVENT_RATE_REPORT = 0x87,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun struct mt7915_mcu_rxd {
50*4882a593Smuzhiyun 	__le32 rxd[6];
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	__le16 len;
53*4882a593Smuzhiyun 	__le16 pkt_type_id;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	u8 eid;
56*4882a593Smuzhiyun 	u8 seq;
57*4882a593Smuzhiyun 	__le16 __rsv;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	u8 ext_eid;
60*4882a593Smuzhiyun 	u8 __rsv1[2];
61*4882a593Smuzhiyun 	u8 s2d_index;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun struct mt7915_mcu_rdd_report {
65*4882a593Smuzhiyun 	struct mt7915_mcu_rxd rxd;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	u8 idx;
68*4882a593Smuzhiyun 	u8 long_detected;
69*4882a593Smuzhiyun 	u8 constant_prf_detected;
70*4882a593Smuzhiyun 	u8 staggered_prf_detected;
71*4882a593Smuzhiyun 	u8 radar_type_idx;
72*4882a593Smuzhiyun 	u8 periodic_pulse_num;
73*4882a593Smuzhiyun 	u8 long_pulse_num;
74*4882a593Smuzhiyun 	u8 hw_pulse_num;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	u8 out_lpn;
77*4882a593Smuzhiyun 	u8 out_spn;
78*4882a593Smuzhiyun 	u8 out_crpn;
79*4882a593Smuzhiyun 	u8 out_crpw;
80*4882a593Smuzhiyun 	u8 out_crbn;
81*4882a593Smuzhiyun 	u8 out_stgpn;
82*4882a593Smuzhiyun 	u8 out_stgpw;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	u8 rsv;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	__le32 out_pri_const;
87*4882a593Smuzhiyun 	__le32 out_pri_stg[3];
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	struct {
90*4882a593Smuzhiyun 		__le32 start;
91*4882a593Smuzhiyun 		__le16 pulse_width;
92*4882a593Smuzhiyun 		__le16 pulse_power;
93*4882a593Smuzhiyun 		u8 mdrdy_flag;
94*4882a593Smuzhiyun 		u8 rsv[3];
95*4882a593Smuzhiyun 	} long_pulse[32];
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	struct {
98*4882a593Smuzhiyun 		__le32 start;
99*4882a593Smuzhiyun 		__le16 pulse_width;
100*4882a593Smuzhiyun 		__le16 pulse_power;
101*4882a593Smuzhiyun 		u8 mdrdy_flag;
102*4882a593Smuzhiyun 		u8 rsv[3];
103*4882a593Smuzhiyun 	} periodic_pulse[32];
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	struct {
106*4882a593Smuzhiyun 		__le32 start;
107*4882a593Smuzhiyun 		__le16 pulse_width;
108*4882a593Smuzhiyun 		__le16 pulse_power;
109*4882a593Smuzhiyun 		u8 sc_pass;
110*4882a593Smuzhiyun 		u8 sw_reset;
111*4882a593Smuzhiyun 		u8 mdrdy_flag;
112*4882a593Smuzhiyun 		u8 tx_active;
113*4882a593Smuzhiyun 	} hw_pulse[32];
114*4882a593Smuzhiyun } __packed;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun struct mt7915_mcu_eeprom_info {
117*4882a593Smuzhiyun 	__le32 addr;
118*4882a593Smuzhiyun 	__le32 valid;
119*4882a593Smuzhiyun 	u8 data[16];
120*4882a593Smuzhiyun } __packed;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct mt7915_mcu_ra_info {
123*4882a593Smuzhiyun 	struct mt7915_mcu_rxd rxd;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	__le32 event_id;
126*4882a593Smuzhiyun 	__le16 wlan_idx;
127*4882a593Smuzhiyun 	__le16 ru_idx;
128*4882a593Smuzhiyun 	__le16 direction;
129*4882a593Smuzhiyun 	__le16 dump_group;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	__le32 suggest_rate;
132*4882a593Smuzhiyun 	__le32 min_rate;	/* for dynamic sounding */
133*4882a593Smuzhiyun 	__le32 max_rate;	/* for dynamic sounding */
134*4882a593Smuzhiyun 	__le32 init_rate_down_rate;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	__le16 curr_rate;
137*4882a593Smuzhiyun 	__le16 init_rate_down_total;
138*4882a593Smuzhiyun 	__le16 init_rate_down_succ;
139*4882a593Smuzhiyun 	__le16 success;
140*4882a593Smuzhiyun 	__le16 attempts;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	__le16 prev_rate;
143*4882a593Smuzhiyun 	__le16 prob_up_rate;
144*4882a593Smuzhiyun 	u8 no_rate_up_cnt;
145*4882a593Smuzhiyun 	u8 ppdu_cnt;
146*4882a593Smuzhiyun 	u8 gi;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	u8 try_up_fail;
149*4882a593Smuzhiyun 	u8 try_up_total;
150*4882a593Smuzhiyun 	u8 suggest_wf;
151*4882a593Smuzhiyun 	u8 try_up_check;
152*4882a593Smuzhiyun 	u8 prob_up_period;
153*4882a593Smuzhiyun 	u8 prob_down_pending;
154*4882a593Smuzhiyun } __packed;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun #define MT_RA_RATE_NSS			GENMASK(8, 6)
157*4882a593Smuzhiyun #define MT_RA_RATE_MCS			GENMASK(3, 0)
158*4882a593Smuzhiyun #define MT_RA_RATE_TX_MODE		GENMASK(12, 9)
159*4882a593Smuzhiyun #define MT_RA_RATE_DCM_EN		BIT(4)
160*4882a593Smuzhiyun #define MT_RA_RATE_BW			GENMASK(14, 13)
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun #define MCU_PQ_ID(p, q)			(((p) << 15) | ((q) << 10))
163*4882a593Smuzhiyun #define MCU_PKT_ID			0xa0
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun enum {
166*4882a593Smuzhiyun 	MCU_Q_QUERY,
167*4882a593Smuzhiyun 	MCU_Q_SET,
168*4882a593Smuzhiyun 	MCU_Q_RESERVED,
169*4882a593Smuzhiyun 	MCU_Q_NA
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun enum {
173*4882a593Smuzhiyun 	MCU_S2D_H2N,
174*4882a593Smuzhiyun 	MCU_S2D_C2N,
175*4882a593Smuzhiyun 	MCU_S2D_H2C,
176*4882a593Smuzhiyun 	MCU_S2D_H2CN
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun enum {
180*4882a593Smuzhiyun 	MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
181*4882a593Smuzhiyun 	MCU_CMD_FW_START_REQ = 0x02,
182*4882a593Smuzhiyun 	MCU_CMD_INIT_ACCESS_REG = 0x3,
183*4882a593Smuzhiyun 	MCU_CMD_NIC_POWER_CTRL = 0x4,
184*4882a593Smuzhiyun 	MCU_CMD_PATCH_START_REQ = 0x05,
185*4882a593Smuzhiyun 	MCU_CMD_PATCH_FINISH_REQ = 0x07,
186*4882a593Smuzhiyun 	MCU_CMD_PATCH_SEM_CONTROL = 0x10,
187*4882a593Smuzhiyun 	MCU_CMD_EXT_CID = 0xED,
188*4882a593Smuzhiyun 	MCU_CMD_FW_SCATTER = 0xEE,
189*4882a593Smuzhiyun 	MCU_CMD_RESTART_DL_REQ = 0xEF,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun enum {
193*4882a593Smuzhiyun 	MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
194*4882a593Smuzhiyun 	MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
195*4882a593Smuzhiyun 	MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
196*4882a593Smuzhiyun 	MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
197*4882a593Smuzhiyun 	MCU_EXT_CMD_TXBF_ACTION = 0x1e,
198*4882a593Smuzhiyun 	MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
199*4882a593Smuzhiyun 	MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
200*4882a593Smuzhiyun 	MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
201*4882a593Smuzhiyun 	MCU_EXT_CMD_EDCA_UPDATE = 0x27,
202*4882a593Smuzhiyun 	MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
203*4882a593Smuzhiyun 	MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
204*4882a593Smuzhiyun 	MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
205*4882a593Smuzhiyun 	MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
206*4882a593Smuzhiyun 	MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
207*4882a593Smuzhiyun 	MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
208*4882a593Smuzhiyun 	MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
209*4882a593Smuzhiyun 	MCU_EXT_CMD_SET_RX_PATH = 0x4e,
210*4882a593Smuzhiyun 	MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
211*4882a593Smuzhiyun 	MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
212*4882a593Smuzhiyun 	MCU_EXT_CMD_SCS_CTRL = 0x82,
213*4882a593Smuzhiyun 	MCU_EXT_CMD_RATE_CTRL = 0x87,
214*4882a593Smuzhiyun 	MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
215*4882a593Smuzhiyun 	MCU_EXT_CMD_SET_RDD_TH = 0x9d,
216*4882a593Smuzhiyun 	MCU_EXT_CMD_SET_SPR = 0xa8,
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun enum {
220*4882a593Smuzhiyun 	PATCH_SEM_RELEASE,
221*4882a593Smuzhiyun 	PATCH_SEM_GET
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun enum {
225*4882a593Smuzhiyun 	PATCH_NOT_DL_SEM_FAIL,
226*4882a593Smuzhiyun 	PATCH_IS_DL,
227*4882a593Smuzhiyun 	PATCH_NOT_DL_SEM_SUCCESS,
228*4882a593Smuzhiyun 	PATCH_REL_SEM_SUCCESS
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun enum {
232*4882a593Smuzhiyun 	FW_STATE_INITIAL,
233*4882a593Smuzhiyun 	FW_STATE_FW_DOWNLOAD,
234*4882a593Smuzhiyun 	FW_STATE_NORMAL_OPERATION,
235*4882a593Smuzhiyun 	FW_STATE_NORMAL_TRX,
236*4882a593Smuzhiyun 	FW_STATE_WACPU_RDY        = 7
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun enum {
240*4882a593Smuzhiyun 	EE_MODE_EFUSE,
241*4882a593Smuzhiyun 	EE_MODE_BUFFER,
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun enum {
245*4882a593Smuzhiyun 	EE_FORMAT_BIN,
246*4882a593Smuzhiyun 	EE_FORMAT_WHOLE,
247*4882a593Smuzhiyun 	EE_FORMAT_MULTIPLE,
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun #define STA_TYPE_STA			BIT(0)
251*4882a593Smuzhiyun #define STA_TYPE_AP			BIT(1)
252*4882a593Smuzhiyun #define STA_TYPE_ADHOC			BIT(2)
253*4882a593Smuzhiyun #define STA_TYPE_WDS			BIT(4)
254*4882a593Smuzhiyun #define STA_TYPE_BC			BIT(5)
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun #define NETWORK_INFRA			BIT(16)
257*4882a593Smuzhiyun #define NETWORK_P2P			BIT(17)
258*4882a593Smuzhiyun #define NETWORK_IBSS			BIT(18)
259*4882a593Smuzhiyun #define NETWORK_WDS			BIT(21)
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun #define CONNECTION_INFRA_STA		(STA_TYPE_STA | NETWORK_INFRA)
262*4882a593Smuzhiyun #define CONNECTION_INFRA_AP		(STA_TYPE_AP | NETWORK_INFRA)
263*4882a593Smuzhiyun #define CONNECTION_P2P_GC		(STA_TYPE_STA | NETWORK_P2P)
264*4882a593Smuzhiyun #define CONNECTION_P2P_GO		(STA_TYPE_AP | NETWORK_P2P)
265*4882a593Smuzhiyun #define CONNECTION_IBSS_ADHOC		(STA_TYPE_ADHOC | NETWORK_IBSS)
266*4882a593Smuzhiyun #define CONNECTION_WDS			(STA_TYPE_WDS | NETWORK_WDS)
267*4882a593Smuzhiyun #define CONNECTION_INFRA_BC		(STA_TYPE_BC | NETWORK_INFRA)
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun #define CONN_STATE_DISCONNECT		0
270*4882a593Smuzhiyun #define CONN_STATE_CONNECT		1
271*4882a593Smuzhiyun #define CONN_STATE_PORT_SECURE		2
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun enum {
274*4882a593Smuzhiyun 	DEV_INFO_ACTIVE,
275*4882a593Smuzhiyun 	DEV_INFO_MAX_NUM
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun enum {
279*4882a593Smuzhiyun 	SCS_SEND_DATA,
280*4882a593Smuzhiyun 	SCS_SET_MANUAL_PD_TH,
281*4882a593Smuzhiyun 	SCS_CONFIG,
282*4882a593Smuzhiyun 	SCS_ENABLE,
283*4882a593Smuzhiyun 	SCS_SHOW_INFO,
284*4882a593Smuzhiyun 	SCS_GET_GLO_ADDR,
285*4882a593Smuzhiyun 	SCS_GET_GLO_ADDR_EVENT,
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun enum {
289*4882a593Smuzhiyun 	CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
290*4882a593Smuzhiyun 	CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
291*4882a593Smuzhiyun 	CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
292*4882a593Smuzhiyun 	CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
293*4882a593Smuzhiyun 	CMD_CBW_10MHZ,
294*4882a593Smuzhiyun 	CMD_CBW_5MHZ,
295*4882a593Smuzhiyun 	CMD_CBW_8080MHZ,
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	CMD_HE_MCS_BW80 = 0,
298*4882a593Smuzhiyun 	CMD_HE_MCS_BW160,
299*4882a593Smuzhiyun 	CMD_HE_MCS_BW8080,
300*4882a593Smuzhiyun 	CMD_HE_MCS_BW_NUM
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun struct tlv {
304*4882a593Smuzhiyun 	__le16 tag;
305*4882a593Smuzhiyun 	__le16 len;
306*4882a593Smuzhiyun } __packed;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun struct bss_info_omac {
309*4882a593Smuzhiyun 	__le16 tag;
310*4882a593Smuzhiyun 	__le16 len;
311*4882a593Smuzhiyun 	u8 hw_bss_idx;
312*4882a593Smuzhiyun 	u8 omac_idx;
313*4882a593Smuzhiyun 	u8 band_idx;
314*4882a593Smuzhiyun 	u8 rsv0;
315*4882a593Smuzhiyun 	__le32 conn_type;
316*4882a593Smuzhiyun 	u32 rsv1;
317*4882a593Smuzhiyun } __packed;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun struct bss_info_basic {
320*4882a593Smuzhiyun 	__le16 tag;
321*4882a593Smuzhiyun 	__le16 len;
322*4882a593Smuzhiyun 	__le32 network_type;
323*4882a593Smuzhiyun 	u8 active;
324*4882a593Smuzhiyun 	u8 rsv0;
325*4882a593Smuzhiyun 	__le16 bcn_interval;
326*4882a593Smuzhiyun 	u8 bssid[ETH_ALEN];
327*4882a593Smuzhiyun 	u8 wmm_idx;
328*4882a593Smuzhiyun 	u8 dtim_period;
329*4882a593Smuzhiyun 	u8 bmc_wcid_lo;
330*4882a593Smuzhiyun 	u8 cipher;
331*4882a593Smuzhiyun 	u8 phy_mode;
332*4882a593Smuzhiyun 	u8 max_bssid;	/* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
333*4882a593Smuzhiyun 	u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
334*4882a593Smuzhiyun 	u8 bmc_wcid_hi;	/* high Byte and version */
335*4882a593Smuzhiyun 	u8 rsv[2];
336*4882a593Smuzhiyun } __packed;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun struct bss_info_rf_ch {
339*4882a593Smuzhiyun 	__le16 tag;
340*4882a593Smuzhiyun 	__le16 len;
341*4882a593Smuzhiyun 	u8 pri_ch;
342*4882a593Smuzhiyun 	u8 center_ch0;
343*4882a593Smuzhiyun 	u8 center_ch1;
344*4882a593Smuzhiyun 	u8 bw;
345*4882a593Smuzhiyun 	u8 he_ru26_block;	/* 1: don't send HETB in RU26, 0: allow */
346*4882a593Smuzhiyun 	u8 he_all_disable;	/* 1: disallow all HETB, 0: allow */
347*4882a593Smuzhiyun 	u8 rsv[2];
348*4882a593Smuzhiyun } __packed;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun struct bss_info_ext_bss {
351*4882a593Smuzhiyun 	__le16 tag;
352*4882a593Smuzhiyun 	__le16 len;
353*4882a593Smuzhiyun 	__le32 mbss_tsf_offset; /* in unit of us */
354*4882a593Smuzhiyun 	u8 rsv[8];
355*4882a593Smuzhiyun } __packed;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun struct bss_info_sync_mode {
358*4882a593Smuzhiyun 	__le16 tag;
359*4882a593Smuzhiyun 	__le16 len;
360*4882a593Smuzhiyun 	__le16 bcn_interval;
361*4882a593Smuzhiyun 	u8 enable;
362*4882a593Smuzhiyun 	u8 dtim_period;
363*4882a593Smuzhiyun 	u8 rsv[8];
364*4882a593Smuzhiyun } __packed;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun struct bss_info_bmc_rate {
367*4882a593Smuzhiyun 	__le16 tag;
368*4882a593Smuzhiyun 	__le16 len;
369*4882a593Smuzhiyun 	__le16 bc_trans;
370*4882a593Smuzhiyun 	__le16 mc_trans;
371*4882a593Smuzhiyun 	u8 short_preamble;
372*4882a593Smuzhiyun 	u8 rsv[7];
373*4882a593Smuzhiyun } __packed;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun struct bss_info_ra {
376*4882a593Smuzhiyun 	__le16 tag;
377*4882a593Smuzhiyun 	__le16 len;
378*4882a593Smuzhiyun 	u8 op_mode;
379*4882a593Smuzhiyun 	u8 adhoc_en;
380*4882a593Smuzhiyun 	u8 short_preamble;
381*4882a593Smuzhiyun 	u8 tx_streams;
382*4882a593Smuzhiyun 	u8 rx_streams;
383*4882a593Smuzhiyun 	u8 algo;
384*4882a593Smuzhiyun 	u8 force_sgi;
385*4882a593Smuzhiyun 	u8 force_gf;
386*4882a593Smuzhiyun 	u8 ht_mode;
387*4882a593Smuzhiyun 	u8 has_20_sta;		/* Check if any sta support GF. */
388*4882a593Smuzhiyun 	u8 bss_width_trigger_events;
389*4882a593Smuzhiyun 	u8 vht_nss_cap;
390*4882a593Smuzhiyun 	u8 vht_bw_signal;	/* not use */
391*4882a593Smuzhiyun 	u8 vht_force_sgi;	/* not use */
392*4882a593Smuzhiyun 	u8 se_off;
393*4882a593Smuzhiyun 	u8 antenna_idx;
394*4882a593Smuzhiyun 	u8 train_up_rule;
395*4882a593Smuzhiyun 	u8 rsv[3];
396*4882a593Smuzhiyun 	unsigned short train_up_high_thres;
397*4882a593Smuzhiyun 	short train_up_rule_rssi;
398*4882a593Smuzhiyun 	unsigned short low_traffic_thres;
399*4882a593Smuzhiyun 	__le16 max_phyrate;
400*4882a593Smuzhiyun 	__le32 phy_cap;
401*4882a593Smuzhiyun 	__le32 interval;
402*4882a593Smuzhiyun 	__le32 fast_interval;
403*4882a593Smuzhiyun } __packed;
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun struct bss_info_hw_amsdu {
406*4882a593Smuzhiyun 	__le16 tag;
407*4882a593Smuzhiyun 	__le16 len;
408*4882a593Smuzhiyun 	__le32 cmp_bitmap_0;
409*4882a593Smuzhiyun 	__le32 cmp_bitmap_1;
410*4882a593Smuzhiyun 	__le16 trig_thres;
411*4882a593Smuzhiyun 	u8 enable;
412*4882a593Smuzhiyun 	u8 rsv;
413*4882a593Smuzhiyun } __packed;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun struct bss_info_he {
416*4882a593Smuzhiyun 	__le16 tag;
417*4882a593Smuzhiyun 	__le16 len;
418*4882a593Smuzhiyun 	u8 he_pe_duration;
419*4882a593Smuzhiyun 	u8 vht_op_info_present;
420*4882a593Smuzhiyun 	__le16 he_rts_thres;
421*4882a593Smuzhiyun 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
422*4882a593Smuzhiyun 	u8 rsv[6];
423*4882a593Smuzhiyun } __packed;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun struct bss_info_bcn {
426*4882a593Smuzhiyun 	__le16 tag;
427*4882a593Smuzhiyun 	__le16 len;
428*4882a593Smuzhiyun 	u8 ver;
429*4882a593Smuzhiyun 	u8 enable;
430*4882a593Smuzhiyun 	__le16 sub_ntlv;
431*4882a593Smuzhiyun } __packed __aligned(4);
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun struct bss_info_bcn_csa {
434*4882a593Smuzhiyun 	__le16 tag;
435*4882a593Smuzhiyun 	__le16 len;
436*4882a593Smuzhiyun 	u8 cnt;
437*4882a593Smuzhiyun 	u8 rsv[3];
438*4882a593Smuzhiyun } __packed __aligned(4);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun struct bss_info_bcn_bcc {
441*4882a593Smuzhiyun 	__le16 tag;
442*4882a593Smuzhiyun 	__le16 len;
443*4882a593Smuzhiyun 	u8 cnt;
444*4882a593Smuzhiyun 	u8 rsv[3];
445*4882a593Smuzhiyun } __packed __aligned(4);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun struct bss_info_bcn_mbss {
448*4882a593Smuzhiyun #define MAX_BEACON_NUM	32
449*4882a593Smuzhiyun 	__le16 tag;
450*4882a593Smuzhiyun 	__le16 len;
451*4882a593Smuzhiyun 	__le32 bitmap;
452*4882a593Smuzhiyun 	__le16 offset[MAX_BEACON_NUM];
453*4882a593Smuzhiyun 	u8 rsv[8];
454*4882a593Smuzhiyun } __packed __aligned(4);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun struct bss_info_bcn_cont {
457*4882a593Smuzhiyun 	__le16 tag;
458*4882a593Smuzhiyun 	__le16 len;
459*4882a593Smuzhiyun 	__le16 tim_ofs;
460*4882a593Smuzhiyun 	__le16 csa_ofs;
461*4882a593Smuzhiyun 	__le16 bcc_ofs;
462*4882a593Smuzhiyun 	__le16 pkt_len;
463*4882a593Smuzhiyun } __packed __aligned(4);
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun enum {
466*4882a593Smuzhiyun 	BSS_INFO_BCN_CSA,
467*4882a593Smuzhiyun 	BSS_INFO_BCN_BCC,
468*4882a593Smuzhiyun 	BSS_INFO_BCN_MBSSID,
469*4882a593Smuzhiyun 	BSS_INFO_BCN_CONTENT,
470*4882a593Smuzhiyun 	BSS_INFO_BCN_MAX
471*4882a593Smuzhiyun };
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun enum {
474*4882a593Smuzhiyun 	BSS_INFO_OMAC,
475*4882a593Smuzhiyun 	BSS_INFO_BASIC,
476*4882a593Smuzhiyun 	BSS_INFO_RF_CH,		/* optional, for BT/LTE coex */
477*4882a593Smuzhiyun 	BSS_INFO_PM,		/* sta only */
478*4882a593Smuzhiyun 	BSS_INFO_UAPSD,		/* sta only */
479*4882a593Smuzhiyun 	BSS_INFO_ROAM_DETECT,	/* obsoleted */
480*4882a593Smuzhiyun 	BSS_INFO_LQ_RM,		/* obsoleted */
481*4882a593Smuzhiyun 	BSS_INFO_EXT_BSS,
482*4882a593Smuzhiyun 	BSS_INFO_BMC_RATE,	/* for bmc rate control in CR4 */
483*4882a593Smuzhiyun 	BSS_INFO_SYNC_MODE,
484*4882a593Smuzhiyun 	BSS_INFO_RA,
485*4882a593Smuzhiyun 	BSS_INFO_HW_AMSDU,
486*4882a593Smuzhiyun 	BSS_INFO_BSS_COLOR,
487*4882a593Smuzhiyun 	BSS_INFO_HE_BASIC,
488*4882a593Smuzhiyun 	BSS_INFO_PROTECT_INFO,
489*4882a593Smuzhiyun 	BSS_INFO_OFFLOAD,
490*4882a593Smuzhiyun 	BSS_INFO_11V_MBSSID,
491*4882a593Smuzhiyun 	BSS_INFO_MAX_NUM
492*4882a593Smuzhiyun };
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun enum {
495*4882a593Smuzhiyun 	WTBL_RESET_AND_SET = 1,
496*4882a593Smuzhiyun 	WTBL_SET,
497*4882a593Smuzhiyun 	WTBL_QUERY,
498*4882a593Smuzhiyun 	WTBL_RESET_ALL
499*4882a593Smuzhiyun };
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun struct wtbl_req_hdr {
502*4882a593Smuzhiyun 	u8 wlan_idx_lo;
503*4882a593Smuzhiyun 	u8 operation;
504*4882a593Smuzhiyun 	__le16 tlv_num;
505*4882a593Smuzhiyun 	u8 wlan_idx_hi;
506*4882a593Smuzhiyun 	u8 rsv[3];
507*4882a593Smuzhiyun } __packed;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun struct wtbl_generic {
510*4882a593Smuzhiyun 	__le16 tag;
511*4882a593Smuzhiyun 	__le16 len;
512*4882a593Smuzhiyun 	u8 peer_addr[ETH_ALEN];
513*4882a593Smuzhiyun 	u8 muar_idx;
514*4882a593Smuzhiyun 	u8 skip_tx;
515*4882a593Smuzhiyun 	u8 cf_ack;
516*4882a593Smuzhiyun 	u8 qos;
517*4882a593Smuzhiyun 	u8 mesh;
518*4882a593Smuzhiyun 	u8 adm;
519*4882a593Smuzhiyun 	__le16 partial_aid;
520*4882a593Smuzhiyun 	u8 baf_en;
521*4882a593Smuzhiyun 	u8 aad_om;
522*4882a593Smuzhiyun } __packed;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun struct wtbl_rx {
525*4882a593Smuzhiyun 	__le16 tag;
526*4882a593Smuzhiyun 	__le16 len;
527*4882a593Smuzhiyun 	u8 rcid;
528*4882a593Smuzhiyun 	u8 rca1;
529*4882a593Smuzhiyun 	u8 rca2;
530*4882a593Smuzhiyun 	u8 rv;
531*4882a593Smuzhiyun 	u8 rsv[4];
532*4882a593Smuzhiyun } __packed;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun struct wtbl_ht {
535*4882a593Smuzhiyun 	__le16 tag;
536*4882a593Smuzhiyun 	__le16 len;
537*4882a593Smuzhiyun 	u8 ht;
538*4882a593Smuzhiyun 	u8 ldpc;
539*4882a593Smuzhiyun 	u8 af;
540*4882a593Smuzhiyun 	u8 mm;
541*4882a593Smuzhiyun 	u8 rsv[4];
542*4882a593Smuzhiyun } __packed;
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun struct wtbl_vht {
545*4882a593Smuzhiyun 	__le16 tag;
546*4882a593Smuzhiyun 	__le16 len;
547*4882a593Smuzhiyun 	u8 ldpc;
548*4882a593Smuzhiyun 	u8 dyn_bw;
549*4882a593Smuzhiyun 	u8 vht;
550*4882a593Smuzhiyun 	u8 txop_ps;
551*4882a593Smuzhiyun 	u8 rsv[4];
552*4882a593Smuzhiyun } __packed;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun enum {
555*4882a593Smuzhiyun 	MT_BA_TYPE_INVALID,
556*4882a593Smuzhiyun 	MT_BA_TYPE_ORIGINATOR,
557*4882a593Smuzhiyun 	MT_BA_TYPE_RECIPIENT
558*4882a593Smuzhiyun };
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun enum {
561*4882a593Smuzhiyun 	RST_BA_MAC_TID_MATCH,
562*4882a593Smuzhiyun 	RST_BA_MAC_MATCH,
563*4882a593Smuzhiyun 	RST_BA_NO_MATCH
564*4882a593Smuzhiyun };
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun struct wtbl_ba {
567*4882a593Smuzhiyun 	__le16 tag;
568*4882a593Smuzhiyun 	__le16 len;
569*4882a593Smuzhiyun 	/* common */
570*4882a593Smuzhiyun 	u8 tid;
571*4882a593Smuzhiyun 	u8 ba_type;
572*4882a593Smuzhiyun 	u8 rsv0[2];
573*4882a593Smuzhiyun 	/* originator only */
574*4882a593Smuzhiyun 	__le16 sn;
575*4882a593Smuzhiyun 	u8 ba_en;
576*4882a593Smuzhiyun 	u8 ba_winsize_idx;
577*4882a593Smuzhiyun 	__le16 ba_winsize;
578*4882a593Smuzhiyun 	/* recipient only */
579*4882a593Smuzhiyun 	u8 peer_addr[ETH_ALEN];
580*4882a593Smuzhiyun 	u8 rst_ba_tid;
581*4882a593Smuzhiyun 	u8 rst_ba_sel;
582*4882a593Smuzhiyun 	u8 rst_ba_sb;
583*4882a593Smuzhiyun 	u8 band_idx;
584*4882a593Smuzhiyun 	u8 rsv1[4];
585*4882a593Smuzhiyun } __packed;
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun struct wtbl_smps {
588*4882a593Smuzhiyun 	__le16 tag;
589*4882a593Smuzhiyun 	__le16 len;
590*4882a593Smuzhiyun 	u8 smps;
591*4882a593Smuzhiyun 	u8 rsv[3];
592*4882a593Smuzhiyun } __packed;
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun enum {
595*4882a593Smuzhiyun 	WTBL_GENERIC,
596*4882a593Smuzhiyun 	WTBL_RX,
597*4882a593Smuzhiyun 	WTBL_HT,
598*4882a593Smuzhiyun 	WTBL_VHT,
599*4882a593Smuzhiyun 	WTBL_PEER_PS,		/* not used */
600*4882a593Smuzhiyun 	WTBL_TX_PS,
601*4882a593Smuzhiyun 	WTBL_HDR_TRANS,
602*4882a593Smuzhiyun 	WTBL_SEC_KEY,
603*4882a593Smuzhiyun 	WTBL_BA,
604*4882a593Smuzhiyun 	WTBL_RDG,		/* obsoleted */
605*4882a593Smuzhiyun 	WTBL_PROTECT,		/* not used */
606*4882a593Smuzhiyun 	WTBL_CLEAR,		/* not used */
607*4882a593Smuzhiyun 	WTBL_BF,
608*4882a593Smuzhiyun 	WTBL_SMPS,
609*4882a593Smuzhiyun 	WTBL_RAW_DATA,		/* debug only */
610*4882a593Smuzhiyun 	WTBL_PN,
611*4882a593Smuzhiyun 	WTBL_SPE,
612*4882a593Smuzhiyun 	WTBL_MAX_NUM
613*4882a593Smuzhiyun };
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun struct sta_ntlv_hdr {
616*4882a593Smuzhiyun 	u8 rsv[2];
617*4882a593Smuzhiyun 	__le16 tlv_num;
618*4882a593Smuzhiyun } __packed;
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun struct sta_req_hdr {
621*4882a593Smuzhiyun 	u8 bss_idx;
622*4882a593Smuzhiyun 	u8 wlan_idx_lo;
623*4882a593Smuzhiyun 	__le16 tlv_num;
624*4882a593Smuzhiyun 	u8 is_tlv_append;
625*4882a593Smuzhiyun 	u8 muar_idx;
626*4882a593Smuzhiyun 	u8 wlan_idx_hi;
627*4882a593Smuzhiyun 	u8 rsv;
628*4882a593Smuzhiyun } __packed;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun struct sta_rec_basic {
631*4882a593Smuzhiyun 	__le16 tag;
632*4882a593Smuzhiyun 	__le16 len;
633*4882a593Smuzhiyun 	__le32 conn_type;
634*4882a593Smuzhiyun 	u8 conn_state;
635*4882a593Smuzhiyun 	u8 qos;
636*4882a593Smuzhiyun 	__le16 aid;
637*4882a593Smuzhiyun 	u8 peer_addr[ETH_ALEN];
638*4882a593Smuzhiyun 	__le16 extra_info;
639*4882a593Smuzhiyun } __packed;
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun struct sta_rec_ht {
642*4882a593Smuzhiyun 	__le16 tag;
643*4882a593Smuzhiyun 	__le16 len;
644*4882a593Smuzhiyun 	__le16 ht_cap;
645*4882a593Smuzhiyun 	u16 rsv;
646*4882a593Smuzhiyun } __packed;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun struct sta_rec_vht {
649*4882a593Smuzhiyun 	__le16 tag;
650*4882a593Smuzhiyun 	__le16 len;
651*4882a593Smuzhiyun 	__le32 vht_cap;
652*4882a593Smuzhiyun 	__le16 vht_rx_mcs_map;
653*4882a593Smuzhiyun 	__le16 vht_tx_mcs_map;
654*4882a593Smuzhiyun 	u8 rts_bw_sig;
655*4882a593Smuzhiyun 	u8 rsv[3];
656*4882a593Smuzhiyun } __packed;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun struct sta_rec_uapsd {
659*4882a593Smuzhiyun 	__le16 tag;
660*4882a593Smuzhiyun 	__le16 len;
661*4882a593Smuzhiyun 	u8 dac_map;
662*4882a593Smuzhiyun 	u8 tac_map;
663*4882a593Smuzhiyun 	u8 max_sp;
664*4882a593Smuzhiyun 	u8 rsv0;
665*4882a593Smuzhiyun 	__le16 listen_interval;
666*4882a593Smuzhiyun 	u8 rsv1[2];
667*4882a593Smuzhiyun } __packed;
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun struct sta_rec_muru {
670*4882a593Smuzhiyun 	__le16 tag;
671*4882a593Smuzhiyun 	__le16 len;
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	struct {
674*4882a593Smuzhiyun 		bool ofdma_dl_en;
675*4882a593Smuzhiyun 		bool ofdma_ul_en;
676*4882a593Smuzhiyun 		bool mimo_dl_en;
677*4882a593Smuzhiyun 		bool mimo_ul_en;
678*4882a593Smuzhiyun 		u8 rsv[4];
679*4882a593Smuzhiyun 	} cfg;
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	struct {
682*4882a593Smuzhiyun 		u8 punc_pream_rx;
683*4882a593Smuzhiyun 		bool he_20m_in_40m_2g;
684*4882a593Smuzhiyun 		bool he_20m_in_160m;
685*4882a593Smuzhiyun 		bool he_80m_in_160m;
686*4882a593Smuzhiyun 		bool lt16_sigb;
687*4882a593Smuzhiyun 		bool rx_su_comp_sigb;
688*4882a593Smuzhiyun 		bool rx_su_non_comp_sigb;
689*4882a593Smuzhiyun 		u8 rsv;
690*4882a593Smuzhiyun 	} ofdma_dl;
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	struct {
693*4882a593Smuzhiyun 		u8 t_frame_dur;
694*4882a593Smuzhiyun 		u8 mu_cascading;
695*4882a593Smuzhiyun 		u8 uo_ra;
696*4882a593Smuzhiyun 		u8 he_2x996_tone;
697*4882a593Smuzhiyun 		u8 rx_t_frame_11ac;
698*4882a593Smuzhiyun 		u8 rsv[3];
699*4882a593Smuzhiyun 	} ofdma_ul;
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 	struct {
702*4882a593Smuzhiyun 		bool vht_mu_bfee;
703*4882a593Smuzhiyun 		bool partial_bw_dl_mimo;
704*4882a593Smuzhiyun 		u8 rsv[2];
705*4882a593Smuzhiyun 	} mimo_dl;
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	struct {
708*4882a593Smuzhiyun 		bool full_ul_mimo;
709*4882a593Smuzhiyun 		bool partial_ul_mimo;
710*4882a593Smuzhiyun 		u8 rsv[2];
711*4882a593Smuzhiyun 	} mimo_ul;
712*4882a593Smuzhiyun } __packed;
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun struct sta_rec_he {
715*4882a593Smuzhiyun 	__le16 tag;
716*4882a593Smuzhiyun 	__le16 len;
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	__le32 he_cap;
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	u8 t_frame_dur;
721*4882a593Smuzhiyun 	u8 max_ampdu_exp;
722*4882a593Smuzhiyun 	u8 bw_set;
723*4882a593Smuzhiyun 	u8 device_class;
724*4882a593Smuzhiyun 	u8 dcm_tx_mode;
725*4882a593Smuzhiyun 	u8 dcm_tx_max_nss;
726*4882a593Smuzhiyun 	u8 dcm_rx_mode;
727*4882a593Smuzhiyun 	u8 dcm_rx_max_nss;
728*4882a593Smuzhiyun 	u8 dcm_max_ru;
729*4882a593Smuzhiyun 	u8 punc_pream_rx;
730*4882a593Smuzhiyun 	u8 pkt_ext;
731*4882a593Smuzhiyun 	u8 rsv1;
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	u8 rsv2[2];
736*4882a593Smuzhiyun } __packed;
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun struct sta_rec_ba {
739*4882a593Smuzhiyun 	__le16 tag;
740*4882a593Smuzhiyun 	__le16 len;
741*4882a593Smuzhiyun 	u8 tid;
742*4882a593Smuzhiyun 	u8 ba_type;
743*4882a593Smuzhiyun 	u8 amsdu;
744*4882a593Smuzhiyun 	u8 ba_en;
745*4882a593Smuzhiyun 	__le16 ssn;
746*4882a593Smuzhiyun 	__le16 winsize;
747*4882a593Smuzhiyun } __packed;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun struct sta_rec_amsdu {
750*4882a593Smuzhiyun 	__le16 tag;
751*4882a593Smuzhiyun 	__le16 len;
752*4882a593Smuzhiyun 	u8 max_amsdu_num;
753*4882a593Smuzhiyun 	u8 max_mpdu_size;
754*4882a593Smuzhiyun 	u8 amsdu_en;
755*4882a593Smuzhiyun 	u8 rsv;
756*4882a593Smuzhiyun } __packed;
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun struct sec_key {
759*4882a593Smuzhiyun 	u8 cipher_id;
760*4882a593Smuzhiyun 	u8 cipher_len;
761*4882a593Smuzhiyun 	u8 key_id;
762*4882a593Smuzhiyun 	u8 key_len;
763*4882a593Smuzhiyun 	u8 key[32];
764*4882a593Smuzhiyun } __packed;
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun struct sta_rec_sec {
767*4882a593Smuzhiyun 	__le16 tag;
768*4882a593Smuzhiyun 	__le16 len;
769*4882a593Smuzhiyun 	u8 add;
770*4882a593Smuzhiyun 	u8 n_cipher;
771*4882a593Smuzhiyun 	u8 rsv[2];
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	struct sec_key key[2];
774*4882a593Smuzhiyun } __packed;
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun struct ra_phy {
777*4882a593Smuzhiyun 	u8 type;
778*4882a593Smuzhiyun 	u8 flag;
779*4882a593Smuzhiyun 	u8 stbc;
780*4882a593Smuzhiyun 	u8 sgi;
781*4882a593Smuzhiyun 	u8 bw;
782*4882a593Smuzhiyun 	u8 ldpc;
783*4882a593Smuzhiyun 	u8 mcs;
784*4882a593Smuzhiyun 	u8 nss;
785*4882a593Smuzhiyun 	u8 he_ltf;
786*4882a593Smuzhiyun };
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun struct sta_rec_ra {
789*4882a593Smuzhiyun 	__le16 tag;
790*4882a593Smuzhiyun 	__le16 len;
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun 	u8 valid;
793*4882a593Smuzhiyun 	u8 auto_rate;
794*4882a593Smuzhiyun 	u8 phy_mode;
795*4882a593Smuzhiyun 	u8 channel;
796*4882a593Smuzhiyun 	u8 bw;
797*4882a593Smuzhiyun 	u8 disable_cck;
798*4882a593Smuzhiyun 	u8 ht_mcs32;
799*4882a593Smuzhiyun 	u8 ht_gf;
800*4882a593Smuzhiyun 	u8 ht_mcs[4];
801*4882a593Smuzhiyun 	u8 mmps_mode;
802*4882a593Smuzhiyun 	u8 gband_256;
803*4882a593Smuzhiyun 	u8 af;
804*4882a593Smuzhiyun 	u8 auth_wapi_mode;
805*4882a593Smuzhiyun 	u8 rate_len;
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	u8 supp_mode;
808*4882a593Smuzhiyun 	u8 supp_cck_rate;
809*4882a593Smuzhiyun 	u8 supp_ofdm_rate;
810*4882a593Smuzhiyun 	__le32 supp_ht_mcs;
811*4882a593Smuzhiyun 	__le16 supp_vht_mcs[4];
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	u8 op_mode;
814*4882a593Smuzhiyun 	u8 op_vht_chan_width;
815*4882a593Smuzhiyun 	u8 op_vht_rx_nss;
816*4882a593Smuzhiyun 	u8 op_vht_rx_nss_type;
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun 	__le32 sta_status;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	struct ra_phy phy;
821*4882a593Smuzhiyun } __packed;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun struct sta_rec_ra_fixed {
824*4882a593Smuzhiyun 	__le16 tag;
825*4882a593Smuzhiyun 	__le16 len;
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun 	__le32 field;
828*4882a593Smuzhiyun 	u8 op_mode;
829*4882a593Smuzhiyun 	u8 op_vht_chan_width;
830*4882a593Smuzhiyun 	u8 op_vht_rx_nss;
831*4882a593Smuzhiyun 	u8 op_vht_rx_nss_type;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	struct ra_phy phy;
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun 	u8 spe_en;
836*4882a593Smuzhiyun 	u8 short_preamble;
837*4882a593Smuzhiyun 	u8 is_5g;
838*4882a593Smuzhiyun 	u8 mmps_mode;
839*4882a593Smuzhiyun } __packed;
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun #define RATE_PARAM_FIXED		3
842*4882a593Smuzhiyun #define RATE_PARAM_AUTO			20
843*4882a593Smuzhiyun #define RATE_CFG_MCS			GENMASK(3, 0)
844*4882a593Smuzhiyun #define RATE_CFG_NSS			GENMASK(7, 4)
845*4882a593Smuzhiyun #define RATE_CFG_GI			GENMASK(11, 8)
846*4882a593Smuzhiyun #define RATE_CFG_BW			GENMASK(15, 12)
847*4882a593Smuzhiyun #define RATE_CFG_STBC			GENMASK(19, 16)
848*4882a593Smuzhiyun #define RATE_CFG_LDPC			GENMASK(23, 20)
849*4882a593Smuzhiyun #define RATE_CFG_PHY_TYPE		GENMASK(27, 24)
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun struct sta_rec_bf {
852*4882a593Smuzhiyun 	__le16 tag;
853*4882a593Smuzhiyun 	__le16 len;
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun 	__le16 pfmu;		/* 0xffff: no access right for PFMU */
856*4882a593Smuzhiyun 	bool su_mu;		/* 0: SU, 1: MU */
857*4882a593Smuzhiyun 	u8 bf_cap;		/* 0: iBF, 1: eBF */
858*4882a593Smuzhiyun 	u8 sounding_phy;	/* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
859*4882a593Smuzhiyun 	u8 ndpa_rate;
860*4882a593Smuzhiyun 	u8 ndp_rate;
861*4882a593Smuzhiyun 	u8 rept_poll_rate;
862*4882a593Smuzhiyun 	u8 tx_mode;		/* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
863*4882a593Smuzhiyun 	u8 nc;
864*4882a593Smuzhiyun 	u8 nr;
865*4882a593Smuzhiyun 	u8 bw;			/* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	u8 mem_total;
868*4882a593Smuzhiyun 	u8 mem_20m;
869*4882a593Smuzhiyun 	struct {
870*4882a593Smuzhiyun 		u8 row;
871*4882a593Smuzhiyun 		u8 col: 6, row_msb: 2;
872*4882a593Smuzhiyun 	} mem[4];
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun 	__le16 smart_ant;
875*4882a593Smuzhiyun 	u8 se_idx;
876*4882a593Smuzhiyun 	u8 auto_sounding;	/* b7: low traffic indicator
877*4882a593Smuzhiyun 				 * b6: Stop sounding for this entry
878*4882a593Smuzhiyun 				 * b5 ~ b0: postpone sounding
879*4882a593Smuzhiyun 				 */
880*4882a593Smuzhiyun 	u8 ibf_timeout;
881*4882a593Smuzhiyun 	u8 ibf_dbw;
882*4882a593Smuzhiyun 	u8 ibf_ncol;
883*4882a593Smuzhiyun 	u8 ibf_nrow;
884*4882a593Smuzhiyun 	u8 nr_bw160;
885*4882a593Smuzhiyun 	u8 nc_bw160;
886*4882a593Smuzhiyun 	u8 ru_start_idx;
887*4882a593Smuzhiyun 	u8 ru_end_idx;
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	bool trigger_su;
890*4882a593Smuzhiyun 	bool trigger_mu;
891*4882a593Smuzhiyun 	bool ng16_su;
892*4882a593Smuzhiyun 	bool ng16_mu;
893*4882a593Smuzhiyun 	bool codebook42_su;
894*4882a593Smuzhiyun 	bool codebook75_mu;
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	u8 he_ltf;
897*4882a593Smuzhiyun 	u8 rsv[2];
898*4882a593Smuzhiyun } __packed;
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun struct sta_rec_bfee {
901*4882a593Smuzhiyun 	__le16 tag;
902*4882a593Smuzhiyun 	__le16 len;
903*4882a593Smuzhiyun 	bool fb_identity_matrix;	/* 1: feedback identity matrix */
904*4882a593Smuzhiyun 	bool ignore_feedback;		/* 1: ignore */
905*4882a593Smuzhiyun 	u8 rsv[2];
906*4882a593Smuzhiyun } __packed;
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun enum {
909*4882a593Smuzhiyun 	STA_REC_BASIC,
910*4882a593Smuzhiyun 	STA_REC_RA,
911*4882a593Smuzhiyun 	STA_REC_RA_CMM_INFO,
912*4882a593Smuzhiyun 	STA_REC_RA_UPDATE,
913*4882a593Smuzhiyun 	STA_REC_BF,
914*4882a593Smuzhiyun 	STA_REC_AMSDU,
915*4882a593Smuzhiyun 	STA_REC_BA,
916*4882a593Smuzhiyun 	STA_REC_RED,		/* not used */
917*4882a593Smuzhiyun 	STA_REC_TX_PROC,	/* for hdr trans and CSO in CR4 */
918*4882a593Smuzhiyun 	STA_REC_HT,
919*4882a593Smuzhiyun 	STA_REC_VHT,
920*4882a593Smuzhiyun 	STA_REC_APPS,
921*4882a593Smuzhiyun 	STA_REC_KEY,
922*4882a593Smuzhiyun 	STA_REC_WTBL,
923*4882a593Smuzhiyun 	STA_REC_HE,
924*4882a593Smuzhiyun 	STA_REC_HW_AMSDU,
925*4882a593Smuzhiyun 	STA_REC_WTBL_AADOM,
926*4882a593Smuzhiyun 	STA_REC_KEY_V2,
927*4882a593Smuzhiyun 	STA_REC_MURU,
928*4882a593Smuzhiyun 	STA_REC_MUEDCA,
929*4882a593Smuzhiyun 	STA_REC_BFEE,
930*4882a593Smuzhiyun 	STA_REC_MAX_NUM
931*4882a593Smuzhiyun };
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun enum mt7915_cipher_type {
934*4882a593Smuzhiyun 	MT_CIPHER_NONE,
935*4882a593Smuzhiyun 	MT_CIPHER_WEP40,
936*4882a593Smuzhiyun 	MT_CIPHER_WEP104,
937*4882a593Smuzhiyun 	MT_CIPHER_WEP128,
938*4882a593Smuzhiyun 	MT_CIPHER_TKIP,
939*4882a593Smuzhiyun 	MT_CIPHER_AES_CCMP,
940*4882a593Smuzhiyun 	MT_CIPHER_CCMP_256,
941*4882a593Smuzhiyun 	MT_CIPHER_GCMP,
942*4882a593Smuzhiyun 	MT_CIPHER_GCMP_256,
943*4882a593Smuzhiyun 	MT_CIPHER_WAPI,
944*4882a593Smuzhiyun 	MT_CIPHER_BIP_CMAC_128,
945*4882a593Smuzhiyun };
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun enum {
948*4882a593Smuzhiyun 	CH_SWITCH_NORMAL = 0,
949*4882a593Smuzhiyun 	CH_SWITCH_SCAN = 3,
950*4882a593Smuzhiyun 	CH_SWITCH_MCC = 4,
951*4882a593Smuzhiyun 	CH_SWITCH_DFS = 5,
952*4882a593Smuzhiyun 	CH_SWITCH_BACKGROUND_SCAN_START = 6,
953*4882a593Smuzhiyun 	CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
954*4882a593Smuzhiyun 	CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
955*4882a593Smuzhiyun 	CH_SWITCH_SCAN_BYPASS_DPD = 9
956*4882a593Smuzhiyun };
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun enum {
959*4882a593Smuzhiyun 	THERMAL_SENSOR_TEMP_QUERY,
960*4882a593Smuzhiyun 	THERMAL_SENSOR_MANUAL_CTRL,
961*4882a593Smuzhiyun 	THERMAL_SENSOR_INFO_QUERY,
962*4882a593Smuzhiyun 	THERMAL_SENSOR_TASK_CTRL,
963*4882a593Smuzhiyun };
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun enum {
966*4882a593Smuzhiyun 	MT_EBF = BIT(0),	/* explicit beamforming */
967*4882a593Smuzhiyun 	MT_IBF = BIT(1)		/* implicit beamforming */
968*4882a593Smuzhiyun };
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun #define MT7915_WTBL_UPDATE_MAX_SIZE	(sizeof(struct wtbl_req_hdr) +	\
971*4882a593Smuzhiyun 					 sizeof(struct wtbl_generic) +	\
972*4882a593Smuzhiyun 					 sizeof(struct wtbl_rx) +	\
973*4882a593Smuzhiyun 					 sizeof(struct wtbl_ht) +	\
974*4882a593Smuzhiyun 					 sizeof(struct wtbl_vht) +	\
975*4882a593Smuzhiyun 					 sizeof(struct wtbl_ba) +	\
976*4882a593Smuzhiyun 					 sizeof(struct wtbl_smps))
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun #define MT7915_STA_UPDATE_MAX_SIZE	(sizeof(struct sta_req_hdr) +	\
979*4882a593Smuzhiyun 					 sizeof(struct sta_rec_basic) +	\
980*4882a593Smuzhiyun 					 sizeof(struct sta_rec_ht) +	\
981*4882a593Smuzhiyun 					 sizeof(struct sta_rec_he) +	\
982*4882a593Smuzhiyun 					 sizeof(struct sta_rec_ba) +	\
983*4882a593Smuzhiyun 					 sizeof(struct sta_rec_vht) +	\
984*4882a593Smuzhiyun 					 sizeof(struct sta_rec_uapsd) + \
985*4882a593Smuzhiyun 					 sizeof(struct sta_rec_amsdu) +	\
986*4882a593Smuzhiyun 					 sizeof(struct tlv) +		\
987*4882a593Smuzhiyun 					 MT7915_WTBL_UPDATE_MAX_SIZE)
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun #define MT7915_WTBL_UPDATE_BA_SIZE	(sizeof(struct wtbl_req_hdr) +	\
990*4882a593Smuzhiyun 					 sizeof(struct wtbl_ba))
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun #define MT7915_BSS_UPDATE_MAX_SIZE	(sizeof(struct sta_req_hdr) +	\
993*4882a593Smuzhiyun 					 sizeof(struct bss_info_omac) +	\
994*4882a593Smuzhiyun 					 sizeof(struct bss_info_basic) +\
995*4882a593Smuzhiyun 					 sizeof(struct bss_info_rf_ch) +\
996*4882a593Smuzhiyun 					 sizeof(struct bss_info_ra) +	\
997*4882a593Smuzhiyun 					 sizeof(struct bss_info_hw_amsdu) +\
998*4882a593Smuzhiyun 					 sizeof(struct bss_info_he) +	\
999*4882a593Smuzhiyun 					 sizeof(struct bss_info_bmc_rate) +\
1000*4882a593Smuzhiyun 					 sizeof(struct bss_info_ext_bss) +\
1001*4882a593Smuzhiyun 					 sizeof(struct bss_info_sync_mode))
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun #define MT7915_BEACON_UPDATE_SIZE	(sizeof(struct sta_req_hdr) +	\
1004*4882a593Smuzhiyun 					 sizeof(struct bss_info_bcn_csa) + \
1005*4882a593Smuzhiyun 					 sizeof(struct bss_info_bcn_bcc) + \
1006*4882a593Smuzhiyun 					 sizeof(struct bss_info_bcn_mbss) + \
1007*4882a593Smuzhiyun 					 sizeof(struct bss_info_bcn_cont))
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun #define PHY_MODE_A			BIT(0)
1010*4882a593Smuzhiyun #define PHY_MODE_B			BIT(1)
1011*4882a593Smuzhiyun #define PHY_MODE_G			BIT(2)
1012*4882a593Smuzhiyun #define PHY_MODE_GN			BIT(3)
1013*4882a593Smuzhiyun #define PHY_MODE_AN			BIT(4)
1014*4882a593Smuzhiyun #define PHY_MODE_AC			BIT(5)
1015*4882a593Smuzhiyun #define PHY_MODE_AX_24G			BIT(6)
1016*4882a593Smuzhiyun #define PHY_MODE_AX_5G			BIT(7)
1017*4882a593Smuzhiyun #define PHY_MODE_AX_6G			BIT(8)
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun #define MODE_CCK			BIT(0)
1020*4882a593Smuzhiyun #define MODE_OFDM			BIT(1)
1021*4882a593Smuzhiyun #define MODE_HT				BIT(2)
1022*4882a593Smuzhiyun #define MODE_VHT			BIT(3)
1023*4882a593Smuzhiyun #define MODE_HE				BIT(4)
1024*4882a593Smuzhiyun 
1025*4882a593Smuzhiyun #define STA_CAP_WMM			BIT(0)
1026*4882a593Smuzhiyun #define STA_CAP_SGI_20			BIT(4)
1027*4882a593Smuzhiyun #define STA_CAP_SGI_40			BIT(5)
1028*4882a593Smuzhiyun #define STA_CAP_TX_STBC			BIT(6)
1029*4882a593Smuzhiyun #define STA_CAP_RX_STBC			BIT(7)
1030*4882a593Smuzhiyun #define STA_CAP_VHT_SGI_80		BIT(16)
1031*4882a593Smuzhiyun #define STA_CAP_VHT_SGI_160		BIT(17)
1032*4882a593Smuzhiyun #define STA_CAP_VHT_TX_STBC		BIT(18)
1033*4882a593Smuzhiyun #define STA_CAP_VHT_RX_STBC		BIT(19)
1034*4882a593Smuzhiyun #define STA_CAP_VHT_LDPC		BIT(23)
1035*4882a593Smuzhiyun #define STA_CAP_LDPC			BIT(24)
1036*4882a593Smuzhiyun #define STA_CAP_HT			BIT(26)
1037*4882a593Smuzhiyun #define STA_CAP_VHT			BIT(27)
1038*4882a593Smuzhiyun #define STA_CAP_HE			BIT(28)
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun /* HE MAC */
1041*4882a593Smuzhiyun #define STA_REC_HE_CAP_HTC			BIT(0)
1042*4882a593Smuzhiyun #define STA_REC_HE_CAP_BQR			BIT(1)
1043*4882a593Smuzhiyun #define STA_REC_HE_CAP_BSR			BIT(2)
1044*4882a593Smuzhiyun #define STA_REC_HE_CAP_OM			BIT(3)
1045*4882a593Smuzhiyun #define STA_REC_HE_CAP_AMSDU_IN_AMPDU		BIT(4)
1046*4882a593Smuzhiyun /* HE PHY */
1047*4882a593Smuzhiyun #define STA_REC_HE_CAP_DUAL_BAND		BIT(5)
1048*4882a593Smuzhiyun #define STA_REC_HE_CAP_LDPC			BIT(6)
1049*4882a593Smuzhiyun #define STA_REC_HE_CAP_TRIG_CQI_FK		BIT(7)
1050*4882a593Smuzhiyun #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE	BIT(8)
1051*4882a593Smuzhiyun /* STBC */
1052*4882a593Smuzhiyun #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC	BIT(9)
1053*4882a593Smuzhiyun #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC	BIT(10)
1054*4882a593Smuzhiyun #define STA_REC_HE_CAP_GT_80M_TX_STBC		BIT(11)
1055*4882a593Smuzhiyun #define STA_REC_HE_CAP_GT_80M_RX_STBC		BIT(12)
1056*4882a593Smuzhiyun /* GI */
1057*4882a593Smuzhiyun #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI	BIT(13)
1058*4882a593Smuzhiyun #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI	BIT(14)
1059*4882a593Smuzhiyun #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI	BIT(15)
1060*4882a593Smuzhiyun #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI	BIT(16)
1061*4882a593Smuzhiyun #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI	BIT(17)
1062*4882a593Smuzhiyun /* 242 TONE */
1063*4882a593Smuzhiyun #define STA_REC_HE_CAP_BW20_RU242_SUPPORT	BIT(18)
1064*4882a593Smuzhiyun #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242	BIT(19)
1065*4882a593Smuzhiyun #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242	BIT(20)
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun #endif
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