1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /* Copyright (C) 2020 MediaTek Inc. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/firmware.h>
5*4882a593Smuzhiyun #include <linux/fs.h>
6*4882a593Smuzhiyun #include "mt7915.h"
7*4882a593Smuzhiyun #include "mcu.h"
8*4882a593Smuzhiyun #include "mac.h"
9*4882a593Smuzhiyun #include "eeprom.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct mt7915_patch_hdr {
12*4882a593Smuzhiyun char build_date[16];
13*4882a593Smuzhiyun char platform[4];
14*4882a593Smuzhiyun __be32 hw_sw_ver;
15*4882a593Smuzhiyun __be32 patch_ver;
16*4882a593Smuzhiyun __be16 checksum;
17*4882a593Smuzhiyun u16 reserved;
18*4882a593Smuzhiyun struct {
19*4882a593Smuzhiyun __be32 patch_ver;
20*4882a593Smuzhiyun __be32 subsys;
21*4882a593Smuzhiyun __be32 feature;
22*4882a593Smuzhiyun __be32 n_region;
23*4882a593Smuzhiyun __be32 crc;
24*4882a593Smuzhiyun u32 reserved[11];
25*4882a593Smuzhiyun } desc;
26*4882a593Smuzhiyun } __packed;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct mt7915_patch_sec {
29*4882a593Smuzhiyun __be32 type;
30*4882a593Smuzhiyun __be32 offs;
31*4882a593Smuzhiyun __be32 size;
32*4882a593Smuzhiyun union {
33*4882a593Smuzhiyun __be32 spec[13];
34*4882a593Smuzhiyun struct {
35*4882a593Smuzhiyun __be32 addr;
36*4882a593Smuzhiyun __be32 len;
37*4882a593Smuzhiyun __be32 sec_key_idx;
38*4882a593Smuzhiyun __be32 align_len;
39*4882a593Smuzhiyun u32 reserved[9];
40*4882a593Smuzhiyun } info;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun } __packed;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct mt7915_fw_trailer {
45*4882a593Smuzhiyun u8 chip_id;
46*4882a593Smuzhiyun u8 eco_code;
47*4882a593Smuzhiyun u8 n_region;
48*4882a593Smuzhiyun u8 format_ver;
49*4882a593Smuzhiyun u8 format_flag;
50*4882a593Smuzhiyun u8 reserved[2];
51*4882a593Smuzhiyun char fw_ver[10];
52*4882a593Smuzhiyun char build_date[15];
53*4882a593Smuzhiyun u32 crc;
54*4882a593Smuzhiyun } __packed;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun struct mt7915_fw_region {
57*4882a593Smuzhiyun __le32 decomp_crc;
58*4882a593Smuzhiyun __le32 decomp_len;
59*4882a593Smuzhiyun __le32 decomp_blk_sz;
60*4882a593Smuzhiyun u8 reserved[4];
61*4882a593Smuzhiyun __le32 addr;
62*4882a593Smuzhiyun __le32 len;
63*4882a593Smuzhiyun u8 feature_set;
64*4882a593Smuzhiyun u8 reserved1[15];
65*4882a593Smuzhiyun } __packed;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define MCU_PATCH_ADDRESS 0x200000
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define MT_STA_BFER BIT(0)
70*4882a593Smuzhiyun #define MT_STA_BFEE BIT(1)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define FW_FEATURE_SET_ENCRYPT BIT(0)
73*4882a593Smuzhiyun #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
74*4882a593Smuzhiyun #define FW_FEATURE_OVERRIDE_ADDR BIT(5)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define DL_MODE_ENCRYPT BIT(0)
77*4882a593Smuzhiyun #define DL_MODE_KEY_IDX GENMASK(2, 1)
78*4882a593Smuzhiyun #define DL_MODE_RESET_SEC_IV BIT(3)
79*4882a593Smuzhiyun #define DL_MODE_WORKING_PDA_CR4 BIT(4)
80*4882a593Smuzhiyun #define DL_MODE_NEED_RSP BIT(31)
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define FW_START_OVERRIDE BIT(0)
83*4882a593Smuzhiyun #define FW_START_WORKING_PDA_CR4 BIT(2)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
86*4882a593Smuzhiyun #define PATCH_SEC_TYPE_INFO 0x2
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
89*4882a593Smuzhiyun #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define HE_PHY(p, c) u8_get_bits(c, IEEE80211_HE_PHY_##p)
92*4882a593Smuzhiyun #define HE_MAC(m, c) u8_get_bits(c, IEEE80211_HE_MAC_##m)
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static enum mt7915_cipher_type
mt7915_mcu_get_cipher(int cipher)95*4882a593Smuzhiyun mt7915_mcu_get_cipher(int cipher)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun switch (cipher) {
98*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
99*4882a593Smuzhiyun return MT_CIPHER_WEP40;
100*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
101*4882a593Smuzhiyun return MT_CIPHER_WEP104;
102*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
103*4882a593Smuzhiyun return MT_CIPHER_TKIP;
104*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_AES_CMAC:
105*4882a593Smuzhiyun return MT_CIPHER_BIP_CMAC_128;
106*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
107*4882a593Smuzhiyun return MT_CIPHER_AES_CCMP;
108*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP_256:
109*4882a593Smuzhiyun return MT_CIPHER_CCMP_256;
110*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_GCMP:
111*4882a593Smuzhiyun return MT_CIPHER_GCMP;
112*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_GCMP_256:
113*4882a593Smuzhiyun return MT_CIPHER_GCMP_256;
114*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_SMS4:
115*4882a593Smuzhiyun return MT_CIPHER_WAPI;
116*4882a593Smuzhiyun default:
117*4882a593Smuzhiyun return MT_CIPHER_NONE;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
mt7915_mcu_chan_bw(struct cfg80211_chan_def * chandef)121*4882a593Smuzhiyun static u8 mt7915_mcu_chan_bw(struct cfg80211_chan_def *chandef)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun static const u8 width_to_bw[] = {
124*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
125*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
126*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
127*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
128*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
129*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
130*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
131*4882a593Smuzhiyun [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (chandef->width >= ARRAY_SIZE(width_to_bw))
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return width_to_bw[chandef->width];
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun static const struct ieee80211_sta_he_cap *
mt7915_get_he_phy_cap(struct mt7915_phy * phy,struct ieee80211_vif * vif)141*4882a593Smuzhiyun mt7915_get_he_phy_cap(struct mt7915_phy *phy, struct ieee80211_vif *vif)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct ieee80211_supported_band *sband;
144*4882a593Smuzhiyun enum nl80211_band band;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun band = phy->mt76->chandef.chan->band;
147*4882a593Smuzhiyun sband = phy->mt76->hw->wiphy->bands[band];
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun return ieee80211_get_he_iftype_cap(sband, vif->type);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static u8
mt7915_get_phy_mode(struct mt7915_dev * dev,struct ieee80211_vif * vif,enum nl80211_band band,struct ieee80211_sta * sta)153*4882a593Smuzhiyun mt7915_get_phy_mode(struct mt7915_dev *dev, struct ieee80211_vif *vif,
154*4882a593Smuzhiyun enum nl80211_band band, struct ieee80211_sta *sta)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun struct ieee80211_sta_ht_cap *ht_cap;
157*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *vht_cap;
158*4882a593Smuzhiyun const struct ieee80211_sta_he_cap *he_cap;
159*4882a593Smuzhiyun u8 mode = 0;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (sta) {
162*4882a593Smuzhiyun ht_cap = &sta->ht_cap;
163*4882a593Smuzhiyun vht_cap = &sta->vht_cap;
164*4882a593Smuzhiyun he_cap = &sta->he_cap;
165*4882a593Smuzhiyun } else {
166*4882a593Smuzhiyun struct ieee80211_supported_band *sband;
167*4882a593Smuzhiyun struct mt7915_phy *phy;
168*4882a593Smuzhiyun struct mt7915_vif *mvif;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun mvif = (struct mt7915_vif *)vif->drv_priv;
171*4882a593Smuzhiyun phy = mvif->band_idx ? mt7915_ext_phy(dev) : &dev->phy;
172*4882a593Smuzhiyun sband = phy->mt76->hw->wiphy->bands[band];
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ht_cap = &sband->ht_cap;
175*4882a593Smuzhiyun vht_cap = &sband->vht_cap;
176*4882a593Smuzhiyun he_cap = ieee80211_get_he_iftype_cap(sband, vif->type);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (band == NL80211_BAND_2GHZ) {
180*4882a593Smuzhiyun mode |= PHY_MODE_B | PHY_MODE_G;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun if (ht_cap->ht_supported)
183*4882a593Smuzhiyun mode |= PHY_MODE_GN;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (he_cap && he_cap->has_he)
186*4882a593Smuzhiyun mode |= PHY_MODE_AX_24G;
187*4882a593Smuzhiyun } else if (band == NL80211_BAND_5GHZ) {
188*4882a593Smuzhiyun mode |= PHY_MODE_A;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (ht_cap->ht_supported)
191*4882a593Smuzhiyun mode |= PHY_MODE_AN;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun if (vht_cap->vht_supported)
194*4882a593Smuzhiyun mode |= PHY_MODE_AC;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (he_cap && he_cap->has_he)
197*4882a593Smuzhiyun mode |= PHY_MODE_AX_5G;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return mode;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static u8
mt7915_mcu_get_sta_nss(u16 mcs_map)204*4882a593Smuzhiyun mt7915_mcu_get_sta_nss(u16 mcs_map)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun u8 nss;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun for (nss = 8; nss > 0; nss--) {
209*4882a593Smuzhiyun u8 nss_mcs = (mcs_map >> (2 * (nss - 1))) & 3;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (nss_mcs != IEEE80211_VHT_MCS_NOT_SUPPORTED)
212*4882a593Smuzhiyun break;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun return nss - 1;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
__mt7915_mcu_msg_send(struct mt7915_dev * dev,struct sk_buff * skb,int cmd,int * wait_seq)218*4882a593Smuzhiyun static int __mt7915_mcu_msg_send(struct mt7915_dev *dev, struct sk_buff *skb,
219*4882a593Smuzhiyun int cmd, int *wait_seq)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun struct mt7915_mcu_txd *mcu_txd;
222*4882a593Smuzhiyun u8 seq, pkt_fmt, qidx;
223*4882a593Smuzhiyun enum mt76_txq_id txq;
224*4882a593Smuzhiyun __le32 *txd;
225*4882a593Smuzhiyun u32 val;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun seq = ++dev->mt76.mcu.msg_seq & 0xf;
228*4882a593Smuzhiyun if (!seq)
229*4882a593Smuzhiyun seq = ++dev->mt76.mcu.msg_seq & 0xf;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (cmd == -MCU_CMD_FW_SCATTER) {
232*4882a593Smuzhiyun txq = MT_TXQ_FWDL;
233*4882a593Smuzhiyun goto exit;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun mcu_txd = (struct mt7915_mcu_txd *)skb_push(skb, sizeof(*mcu_txd));
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state)) {
239*4882a593Smuzhiyun txq = MT_TXQ_MCU_WA;
240*4882a593Smuzhiyun qidx = MT_TX_MCU_PORT_RX_Q0;
241*4882a593Smuzhiyun pkt_fmt = MT_TX_TYPE_CMD;
242*4882a593Smuzhiyun } else {
243*4882a593Smuzhiyun txq = MT_TXQ_MCU;
244*4882a593Smuzhiyun qidx = MT_TX_MCU_PORT_RX_Q0;
245*4882a593Smuzhiyun pkt_fmt = MT_TX_TYPE_CMD;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun txd = mcu_txd->txd;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) |
251*4882a593Smuzhiyun FIELD_PREP(MT_TXD0_PKT_FMT, pkt_fmt) |
252*4882a593Smuzhiyun FIELD_PREP(MT_TXD0_Q_IDX, qidx);
253*4882a593Smuzhiyun txd[0] = cpu_to_le32(val);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun val = MT_TXD1_LONG_FORMAT |
256*4882a593Smuzhiyun FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD);
257*4882a593Smuzhiyun txd[1] = cpu_to_le32(val);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd));
260*4882a593Smuzhiyun mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, qidx));
261*4882a593Smuzhiyun mcu_txd->pkt_type = MCU_PKT_ID;
262*4882a593Smuzhiyun mcu_txd->seq = seq;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (cmd < 0) {
265*4882a593Smuzhiyun mcu_txd->set_query = MCU_Q_NA;
266*4882a593Smuzhiyun mcu_txd->cid = -cmd;
267*4882a593Smuzhiyun } else {
268*4882a593Smuzhiyun mcu_txd->cid = MCU_CMD_EXT_CID;
269*4882a593Smuzhiyun mcu_txd->ext_cid = cmd;
270*4882a593Smuzhiyun mcu_txd->ext_cid_ack = 1;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* do not use Q_SET for efuse */
273*4882a593Smuzhiyun if (cmd == MCU_EXT_CMD_EFUSE_ACCESS)
274*4882a593Smuzhiyun mcu_txd->set_query = MCU_Q_QUERY;
275*4882a593Smuzhiyun else
276*4882a593Smuzhiyun mcu_txd->set_query = MCU_Q_SET;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun mcu_txd->s2d_index = MCU_S2D_H2N;
280*4882a593Smuzhiyun WARN_ON(cmd == MCU_EXT_CMD_EFUSE_ACCESS &&
281*4882a593Smuzhiyun mcu_txd->set_query != MCU_Q_QUERY);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun exit:
284*4882a593Smuzhiyun if (wait_seq)
285*4882a593Smuzhiyun *wait_seq = seq;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return mt76_tx_queue_skb_raw(dev, txq, skb, 0);
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun static int
mt7915_mcu_parse_eeprom(struct mt7915_dev * dev,struct sk_buff * skb)291*4882a593Smuzhiyun mt7915_mcu_parse_eeprom(struct mt7915_dev *dev, struct sk_buff *skb)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun struct mt7915_mcu_eeprom_info *res;
294*4882a593Smuzhiyun u8 *buf;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun if (!skb)
297*4882a593Smuzhiyun return -EINVAL;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun skb_pull(skb, sizeof(struct mt7915_mcu_rxd));
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun res = (struct mt7915_mcu_eeprom_info *)skb->data;
302*4882a593Smuzhiyun buf = dev->mt76.eeprom.data + le32_to_cpu(res->addr);
303*4882a593Smuzhiyun memcpy(buf, res->data, 16);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static int
mt7915_mcu_parse_response(struct mt7915_dev * dev,int cmd,struct sk_buff * skb,int seq)309*4882a593Smuzhiyun mt7915_mcu_parse_response(struct mt7915_dev *dev, int cmd,
310*4882a593Smuzhiyun struct sk_buff *skb, int seq)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
313*4882a593Smuzhiyun int ret = 0;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (seq != rxd->seq) {
316*4882a593Smuzhiyun ret = -EAGAIN;
317*4882a593Smuzhiyun goto out;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun switch (cmd) {
321*4882a593Smuzhiyun case -MCU_CMD_PATCH_SEM_CONTROL:
322*4882a593Smuzhiyun skb_pull(skb, sizeof(*rxd) - 4);
323*4882a593Smuzhiyun ret = *skb->data;
324*4882a593Smuzhiyun break;
325*4882a593Smuzhiyun case MCU_EXT_CMD_THERMAL_CTRL:
326*4882a593Smuzhiyun skb_pull(skb, sizeof(*rxd) + 4);
327*4882a593Smuzhiyun ret = le32_to_cpu(*(__le32 *)skb->data);
328*4882a593Smuzhiyun break;
329*4882a593Smuzhiyun case MCU_EXT_CMD_EFUSE_ACCESS:
330*4882a593Smuzhiyun ret = mt7915_mcu_parse_eeprom(dev, skb);
331*4882a593Smuzhiyun break;
332*4882a593Smuzhiyun default:
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun out:
336*4882a593Smuzhiyun dev_kfree_skb(skb);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun return ret;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun static int
mt7915_mcu_wait_response(struct mt7915_dev * dev,int cmd,int seq)342*4882a593Smuzhiyun mt7915_mcu_wait_response(struct mt7915_dev *dev, int cmd, int seq)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun unsigned long expires = jiffies + 20 * HZ;
345*4882a593Smuzhiyun struct sk_buff *skb;
346*4882a593Smuzhiyun int ret = 0;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun while (true) {
349*4882a593Smuzhiyun skb = mt76_mcu_get_response(&dev->mt76, expires);
350*4882a593Smuzhiyun if (!skb) {
351*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Message %d (seq %d) timeout\n",
352*4882a593Smuzhiyun cmd, seq);
353*4882a593Smuzhiyun return -ETIMEDOUT;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun ret = mt7915_mcu_parse_response(dev, cmd, skb, seq);
357*4882a593Smuzhiyun if (ret != -EAGAIN)
358*4882a593Smuzhiyun break;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun return ret;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun static int
mt7915_mcu_send_message(struct mt76_dev * mdev,struct sk_buff * skb,int cmd,bool wait_resp)365*4882a593Smuzhiyun mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
366*4882a593Smuzhiyun int cmd, bool wait_resp)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
369*4882a593Smuzhiyun int ret, seq;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun mutex_lock(&mdev->mcu.mutex);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun ret = __mt7915_mcu_msg_send(dev, skb, cmd, &seq);
374*4882a593Smuzhiyun if (ret)
375*4882a593Smuzhiyun goto out;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun if (wait_resp)
378*4882a593Smuzhiyun ret = mt7915_mcu_wait_response(dev, cmd, seq);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun out:
381*4882a593Smuzhiyun mutex_unlock(&mdev->mcu.mutex);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun return ret;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun static int
mt7915_mcu_msg_send(struct mt76_dev * mdev,int cmd,const void * data,int len,bool wait_resp)387*4882a593Smuzhiyun mt7915_mcu_msg_send(struct mt76_dev *mdev, int cmd, const void *data,
388*4882a593Smuzhiyun int len, bool wait_resp)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun struct sk_buff *skb;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun skb = mt76_mcu_msg_alloc(mdev, data, len);
393*4882a593Smuzhiyun if (!skb)
394*4882a593Smuzhiyun return -ENOMEM;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(mdev, skb, cmd, wait_resp);
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun static void
mt7915_mcu_csa_finish(void * priv,u8 * mac,struct ieee80211_vif * vif)400*4882a593Smuzhiyun mt7915_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun if (vif->csa_active)
403*4882a593Smuzhiyun ieee80211_csa_finish(vif);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun static void
mt7915_mcu_rx_radar_detected(struct mt7915_dev * dev,struct sk_buff * skb)407*4882a593Smuzhiyun mt7915_mcu_rx_radar_detected(struct mt7915_dev *dev, struct sk_buff *skb)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun struct mt76_phy *mphy = &dev->mt76.phy;
410*4882a593Smuzhiyun struct mt7915_mcu_rdd_report *r;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun r = (struct mt7915_mcu_rdd_report *)skb->data;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun if (r->idx && dev->mt76.phy2)
415*4882a593Smuzhiyun mphy = dev->mt76.phy2;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun ieee80211_radar_detected(mphy->hw);
418*4882a593Smuzhiyun dev->hw_pattern++;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun static void
mt7915_mcu_tx_rate_cal(struct mt76_phy * mphy,struct mt7915_mcu_ra_info * ra,struct rate_info * rate,u16 r)422*4882a593Smuzhiyun mt7915_mcu_tx_rate_cal(struct mt76_phy *mphy, struct mt7915_mcu_ra_info *ra,
423*4882a593Smuzhiyun struct rate_info *rate, u16 r)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun struct ieee80211_supported_band *sband;
426*4882a593Smuzhiyun u16 ru_idx = le16_to_cpu(ra->ru_idx);
427*4882a593Smuzhiyun u16 flags = 0;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun rate->mcs = FIELD_GET(MT_RA_RATE_MCS, r);
430*4882a593Smuzhiyun rate->nss = FIELD_GET(MT_RA_RATE_NSS, r) + 1;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun switch (FIELD_GET(MT_RA_RATE_TX_MODE, r)) {
433*4882a593Smuzhiyun case MT_PHY_TYPE_CCK:
434*4882a593Smuzhiyun case MT_PHY_TYPE_OFDM:
435*4882a593Smuzhiyun if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
436*4882a593Smuzhiyun sband = &mphy->sband_5g.sband;
437*4882a593Smuzhiyun else
438*4882a593Smuzhiyun sband = &mphy->sband_2g.sband;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun rate->legacy = sband->bitrates[rate->mcs].bitrate;
441*4882a593Smuzhiyun break;
442*4882a593Smuzhiyun case MT_PHY_TYPE_HT:
443*4882a593Smuzhiyun case MT_PHY_TYPE_HT_GF:
444*4882a593Smuzhiyun rate->mcs += (rate->nss - 1) * 8;
445*4882a593Smuzhiyun flags |= RATE_INFO_FLAGS_MCS;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun if (ra->gi)
448*4882a593Smuzhiyun flags |= RATE_INFO_FLAGS_SHORT_GI;
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun case MT_PHY_TYPE_VHT:
451*4882a593Smuzhiyun flags |= RATE_INFO_FLAGS_VHT_MCS;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (ra->gi)
454*4882a593Smuzhiyun flags |= RATE_INFO_FLAGS_SHORT_GI;
455*4882a593Smuzhiyun break;
456*4882a593Smuzhiyun case MT_PHY_TYPE_HE_SU:
457*4882a593Smuzhiyun case MT_PHY_TYPE_HE_EXT_SU:
458*4882a593Smuzhiyun case MT_PHY_TYPE_HE_TB:
459*4882a593Smuzhiyun case MT_PHY_TYPE_HE_MU:
460*4882a593Smuzhiyun rate->he_gi = ra->gi;
461*4882a593Smuzhiyun rate->he_dcm = FIELD_GET(MT_RA_RATE_DCM_EN, r);
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun flags |= RATE_INFO_FLAGS_HE_MCS;
464*4882a593Smuzhiyun break;
465*4882a593Smuzhiyun default:
466*4882a593Smuzhiyun break;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun rate->flags = flags;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun if (ru_idx) {
471*4882a593Smuzhiyun switch (ru_idx) {
472*4882a593Smuzhiyun case 1 ... 2:
473*4882a593Smuzhiyun rate->he_ru_alloc = NL80211_RATE_INFO_HE_RU_ALLOC_996;
474*4882a593Smuzhiyun break;
475*4882a593Smuzhiyun case 3 ... 6:
476*4882a593Smuzhiyun rate->he_ru_alloc = NL80211_RATE_INFO_HE_RU_ALLOC_484;
477*4882a593Smuzhiyun break;
478*4882a593Smuzhiyun case 7 ... 14:
479*4882a593Smuzhiyun rate->he_ru_alloc = NL80211_RATE_INFO_HE_RU_ALLOC_242;
480*4882a593Smuzhiyun break;
481*4882a593Smuzhiyun default:
482*4882a593Smuzhiyun rate->he_ru_alloc = NL80211_RATE_INFO_HE_RU_ALLOC_106;
483*4882a593Smuzhiyun break;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun rate->bw = RATE_INFO_BW_HE_RU;
486*4882a593Smuzhiyun } else {
487*4882a593Smuzhiyun u8 bw = mt7915_mcu_chan_bw(&mphy->chandef) -
488*4882a593Smuzhiyun FIELD_GET(MT_RA_RATE_BW, r);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun switch (bw) {
491*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_160:
492*4882a593Smuzhiyun rate->bw = RATE_INFO_BW_160;
493*4882a593Smuzhiyun break;
494*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_80:
495*4882a593Smuzhiyun rate->bw = RATE_INFO_BW_80;
496*4882a593Smuzhiyun break;
497*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_40:
498*4882a593Smuzhiyun rate->bw = RATE_INFO_BW_40;
499*4882a593Smuzhiyun break;
500*4882a593Smuzhiyun default:
501*4882a593Smuzhiyun rate->bw = RATE_INFO_BW_20;
502*4882a593Smuzhiyun break;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun static void
mt7915_mcu_tx_rate_report(struct mt7915_dev * dev,struct sk_buff * skb)508*4882a593Smuzhiyun mt7915_mcu_tx_rate_report(struct mt7915_dev *dev, struct sk_buff *skb)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun struct mt7915_mcu_ra_info *ra = (struct mt7915_mcu_ra_info *)skb->data;
511*4882a593Smuzhiyun struct rate_info rate = {}, prob_rate = {};
512*4882a593Smuzhiyun u16 probe = le16_to_cpu(ra->prob_up_rate);
513*4882a593Smuzhiyun u16 attempts = le16_to_cpu(ra->attempts);
514*4882a593Smuzhiyun u16 curr = le16_to_cpu(ra->curr_rate);
515*4882a593Smuzhiyun u16 wcidx = le16_to_cpu(ra->wlan_idx);
516*4882a593Smuzhiyun struct mt76_phy *mphy = &dev->mphy;
517*4882a593Smuzhiyun struct mt7915_sta_stats *stats;
518*4882a593Smuzhiyun struct mt7915_sta *msta;
519*4882a593Smuzhiyun struct mt76_wcid *wcid;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (wcidx >= MT76_N_WCIDS)
522*4882a593Smuzhiyun return;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
525*4882a593Smuzhiyun if (!wcid)
526*4882a593Smuzhiyun return;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun msta = container_of(wcid, struct mt7915_sta, wcid);
529*4882a593Smuzhiyun stats = &msta->stats;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (msta->wcid.ext_phy && dev->mt76.phy2)
532*4882a593Smuzhiyun mphy = dev->mt76.phy2;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* current rate */
535*4882a593Smuzhiyun mt7915_mcu_tx_rate_cal(mphy, ra, &rate, curr);
536*4882a593Smuzhiyun stats->tx_rate = rate;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun /* probing rate */
539*4882a593Smuzhiyun mt7915_mcu_tx_rate_cal(mphy, ra, &prob_rate, probe);
540*4882a593Smuzhiyun stats->prob_rate = prob_rate;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun if (attempts) {
543*4882a593Smuzhiyun u16 success = le16_to_cpu(ra->success);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun stats->per = 1000 * (attempts - success) / attempts;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun static void
mt7915_mcu_rx_log_message(struct mt7915_dev * dev,struct sk_buff * skb)550*4882a593Smuzhiyun mt7915_mcu_rx_log_message(struct mt7915_dev *dev, struct sk_buff *skb)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
553*4882a593Smuzhiyun const char *data = (char *)&rxd[1];
554*4882a593Smuzhiyun const char *type;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun switch (rxd->s2d_index) {
557*4882a593Smuzhiyun case 0:
558*4882a593Smuzhiyun type = "WM";
559*4882a593Smuzhiyun break;
560*4882a593Smuzhiyun case 2:
561*4882a593Smuzhiyun type = "WA";
562*4882a593Smuzhiyun break;
563*4882a593Smuzhiyun default:
564*4882a593Smuzhiyun type = "unknown";
565*4882a593Smuzhiyun break;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun wiphy_info(mt76_hw(dev)->wiphy, "%s: %s", type, data);
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun static void
mt7915_mcu_rx_ext_event(struct mt7915_dev * dev,struct sk_buff * skb)572*4882a593Smuzhiyun mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun switch (rxd->ext_eid) {
577*4882a593Smuzhiyun case MCU_EXT_EVENT_RDD_REPORT:
578*4882a593Smuzhiyun mt7915_mcu_rx_radar_detected(dev, skb);
579*4882a593Smuzhiyun break;
580*4882a593Smuzhiyun case MCU_EXT_EVENT_CSA_NOTIFY:
581*4882a593Smuzhiyun ieee80211_iterate_active_interfaces_atomic(dev->mt76.hw,
582*4882a593Smuzhiyun IEEE80211_IFACE_ITER_RESUME_ALL,
583*4882a593Smuzhiyun mt7915_mcu_csa_finish, dev);
584*4882a593Smuzhiyun break;
585*4882a593Smuzhiyun case MCU_EXT_EVENT_RATE_REPORT:
586*4882a593Smuzhiyun mt7915_mcu_tx_rate_report(dev, skb);
587*4882a593Smuzhiyun break;
588*4882a593Smuzhiyun case MCU_EXT_EVENT_FW_LOG_2_HOST:
589*4882a593Smuzhiyun mt7915_mcu_rx_log_message(dev, skb);
590*4882a593Smuzhiyun break;
591*4882a593Smuzhiyun default:
592*4882a593Smuzhiyun break;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun static void
mt7915_mcu_rx_unsolicited_event(struct mt7915_dev * dev,struct sk_buff * skb)597*4882a593Smuzhiyun mt7915_mcu_rx_unsolicited_event(struct mt7915_dev *dev, struct sk_buff *skb)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun switch (rxd->eid) {
602*4882a593Smuzhiyun case MCU_EVENT_EXT:
603*4882a593Smuzhiyun mt7915_mcu_rx_ext_event(dev, skb);
604*4882a593Smuzhiyun break;
605*4882a593Smuzhiyun default:
606*4882a593Smuzhiyun break;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun dev_kfree_skb(skb);
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun
mt7915_mcu_rx_event(struct mt7915_dev * dev,struct sk_buff * skb)611*4882a593Smuzhiyun void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT ||
616*4882a593Smuzhiyun rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST ||
617*4882a593Smuzhiyun rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
618*4882a593Smuzhiyun rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
619*4882a593Smuzhiyun rxd->ext_eid == MCU_EXT_EVENT_RATE_REPORT ||
620*4882a593Smuzhiyun !rxd->seq)
621*4882a593Smuzhiyun mt7915_mcu_rx_unsolicited_event(dev, skb);
622*4882a593Smuzhiyun else
623*4882a593Smuzhiyun mt76_mcu_rx_event(&dev->mt76, skb);
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun static struct sk_buff *
mt7915_mcu_alloc_sta_req(struct mt7915_dev * dev,struct mt7915_vif * mvif,struct mt7915_sta * msta,int len)627*4882a593Smuzhiyun mt7915_mcu_alloc_sta_req(struct mt7915_dev *dev, struct mt7915_vif *mvif,
628*4882a593Smuzhiyun struct mt7915_sta *msta, int len)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun struct sta_req_hdr hdr = {
631*4882a593Smuzhiyun .bss_idx = mvif->idx,
632*4882a593Smuzhiyun .wlan_idx_lo = msta ? to_wcid_lo(msta->wcid.idx) : 0,
633*4882a593Smuzhiyun .wlan_idx_hi = msta ? to_wcid_hi(msta->wcid.idx) : 0,
634*4882a593Smuzhiyun .muar_idx = msta && msta->wcid.sta ? mvif->omac_idx : 0xe,
635*4882a593Smuzhiyun .is_tlv_append = 1,
636*4882a593Smuzhiyun };
637*4882a593Smuzhiyun struct sk_buff *skb;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, len);
640*4882a593Smuzhiyun if (!skb)
641*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun skb_put_data(skb, &hdr, sizeof(hdr));
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun return skb;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun static struct wtbl_req_hdr *
mt7915_mcu_alloc_wtbl_req(struct mt7915_dev * dev,struct mt7915_sta * msta,int cmd,void * sta_wtbl,struct sk_buff ** skb)649*4882a593Smuzhiyun mt7915_mcu_alloc_wtbl_req(struct mt7915_dev *dev, struct mt7915_sta *msta,
650*4882a593Smuzhiyun int cmd, void *sta_wtbl, struct sk_buff **skb)
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun struct tlv *sta_hdr = sta_wtbl;
653*4882a593Smuzhiyun struct wtbl_req_hdr hdr = {
654*4882a593Smuzhiyun .wlan_idx_lo = to_wcid_lo(msta->wcid.idx),
655*4882a593Smuzhiyun .wlan_idx_hi = to_wcid_hi(msta->wcid.idx),
656*4882a593Smuzhiyun .operation = cmd,
657*4882a593Smuzhiyun };
658*4882a593Smuzhiyun struct sk_buff *nskb = *skb;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun if (!nskb) {
661*4882a593Smuzhiyun nskb = mt76_mcu_msg_alloc(&dev->mt76, NULL,
662*4882a593Smuzhiyun MT7915_WTBL_UPDATE_BA_SIZE);
663*4882a593Smuzhiyun if (!nskb)
664*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun *skb = nskb;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun if (sta_hdr)
670*4882a593Smuzhiyun le16_add_cpu(&sta_hdr->len, sizeof(hdr));
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun return skb_put_data(nskb, &hdr, sizeof(hdr));
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun static struct tlv *
mt7915_mcu_add_nested_tlv(struct sk_buff * skb,int tag,int len,void * sta_ntlv,void * sta_wtbl)676*4882a593Smuzhiyun mt7915_mcu_add_nested_tlv(struct sk_buff *skb, int tag, int len,
677*4882a593Smuzhiyun void *sta_ntlv, void *sta_wtbl)
678*4882a593Smuzhiyun {
679*4882a593Smuzhiyun struct sta_ntlv_hdr *ntlv_hdr = sta_ntlv;
680*4882a593Smuzhiyun struct tlv *sta_hdr = sta_wtbl;
681*4882a593Smuzhiyun struct tlv *ptlv, tlv = {
682*4882a593Smuzhiyun .tag = cpu_to_le16(tag),
683*4882a593Smuzhiyun .len = cpu_to_le16(len),
684*4882a593Smuzhiyun };
685*4882a593Smuzhiyun u16 ntlv;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun ptlv = skb_put(skb, len);
688*4882a593Smuzhiyun memcpy(ptlv, &tlv, sizeof(tlv));
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun ntlv = le16_to_cpu(ntlv_hdr->tlv_num);
691*4882a593Smuzhiyun ntlv_hdr->tlv_num = cpu_to_le16(ntlv + 1);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun if (sta_hdr) {
694*4882a593Smuzhiyun u16 size = le16_to_cpu(sta_hdr->len);
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun sta_hdr->len = cpu_to_le16(size + len);
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun return ptlv;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun static struct tlv *
mt7915_mcu_add_tlv(struct sk_buff * skb,int tag,int len)703*4882a593Smuzhiyun mt7915_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun return mt7915_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun static struct tlv *
mt7915_mcu_add_nested_subtlv(struct sk_buff * skb,int sub_tag,int sub_len,__le16 * sub_ntlv,__le16 * len)709*4882a593Smuzhiyun mt7915_mcu_add_nested_subtlv(struct sk_buff *skb, int sub_tag, int sub_len,
710*4882a593Smuzhiyun __le16 *sub_ntlv, __le16 *len)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun struct tlv *ptlv, tlv = {
713*4882a593Smuzhiyun .tag = cpu_to_le16(sub_tag),
714*4882a593Smuzhiyun .len = cpu_to_le16(sub_len),
715*4882a593Smuzhiyun };
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun ptlv = skb_put(skb, sub_len);
718*4882a593Smuzhiyun memcpy(ptlv, &tlv, sizeof(tlv));
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun le16_add_cpu(sub_ntlv, 1);
721*4882a593Smuzhiyun le16_add_cpu(len, sub_len);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun return ptlv;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun /** bss info **/
727*4882a593Smuzhiyun static int
mt7915_mcu_bss_basic_tlv(struct sk_buff * skb,struct ieee80211_vif * vif,struct mt7915_phy * phy,bool enable)728*4882a593Smuzhiyun mt7915_mcu_bss_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif,
729*4882a593Smuzhiyun struct mt7915_phy *phy, bool enable)
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
732*4882a593Smuzhiyun struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
733*4882a593Smuzhiyun enum nl80211_band band = chandef->chan->band;
734*4882a593Smuzhiyun struct bss_info_basic *bss;
735*4882a593Smuzhiyun u16 wlan_idx = mvif->sta.wcid.idx;
736*4882a593Smuzhiyun u32 type = NETWORK_INFRA;
737*4882a593Smuzhiyun struct tlv *tlv;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_BASIC, sizeof(*bss));
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun switch (vif->type) {
742*4882a593Smuzhiyun case NL80211_IFTYPE_MESH_POINT:
743*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
744*4882a593Smuzhiyun break;
745*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
746*4882a593Smuzhiyun /* TODO: enable BSS_INFO_UAPSD & BSS_INFO_PM */
747*4882a593Smuzhiyun if (enable) {
748*4882a593Smuzhiyun struct ieee80211_sta *sta;
749*4882a593Smuzhiyun struct mt7915_sta *msta;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun rcu_read_lock();
752*4882a593Smuzhiyun sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
753*4882a593Smuzhiyun if (!sta) {
754*4882a593Smuzhiyun rcu_read_unlock();
755*4882a593Smuzhiyun return -EINVAL;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun msta = (struct mt7915_sta *)sta->drv_priv;
759*4882a593Smuzhiyun wlan_idx = msta->wcid.idx;
760*4882a593Smuzhiyun rcu_read_unlock();
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun break;
763*4882a593Smuzhiyun case NL80211_IFTYPE_ADHOC:
764*4882a593Smuzhiyun type = NETWORK_IBSS;
765*4882a593Smuzhiyun break;
766*4882a593Smuzhiyun default:
767*4882a593Smuzhiyun WARN_ON(1);
768*4882a593Smuzhiyun break;
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun bss = (struct bss_info_basic *)tlv;
772*4882a593Smuzhiyun memcpy(bss->bssid, vif->bss_conf.bssid, ETH_ALEN);
773*4882a593Smuzhiyun bss->bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int);
774*4882a593Smuzhiyun bss->network_type = cpu_to_le32(type);
775*4882a593Smuzhiyun bss->dtim_period = vif->bss_conf.dtim_period;
776*4882a593Smuzhiyun bss->bmc_wcid_lo = to_wcid_lo(wlan_idx);
777*4882a593Smuzhiyun bss->bmc_wcid_hi = to_wcid_hi(wlan_idx);
778*4882a593Smuzhiyun bss->phy_mode = mt7915_get_phy_mode(phy->dev, vif, band, NULL);
779*4882a593Smuzhiyun bss->wmm_idx = mvif->wmm_idx;
780*4882a593Smuzhiyun bss->active = enable;
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun return 0;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun static void
mt7915_mcu_bss_omac_tlv(struct sk_buff * skb,struct ieee80211_vif * vif)786*4882a593Smuzhiyun mt7915_mcu_bss_omac_tlv(struct sk_buff *skb, struct ieee80211_vif *vif)
787*4882a593Smuzhiyun {
788*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
789*4882a593Smuzhiyun struct bss_info_omac *omac;
790*4882a593Smuzhiyun struct tlv *tlv;
791*4882a593Smuzhiyun u32 type = 0;
792*4882a593Smuzhiyun u8 idx;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_OMAC, sizeof(*omac));
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun switch (vif->type) {
797*4882a593Smuzhiyun case NL80211_IFTYPE_MESH_POINT:
798*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
799*4882a593Smuzhiyun type = CONNECTION_INFRA_AP;
800*4882a593Smuzhiyun break;
801*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
802*4882a593Smuzhiyun type = CONNECTION_INFRA_STA;
803*4882a593Smuzhiyun break;
804*4882a593Smuzhiyun case NL80211_IFTYPE_ADHOC:
805*4882a593Smuzhiyun type = CONNECTION_IBSS_ADHOC;
806*4882a593Smuzhiyun break;
807*4882a593Smuzhiyun default:
808*4882a593Smuzhiyun WARN_ON(1);
809*4882a593Smuzhiyun break;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun omac = (struct bss_info_omac *)tlv;
813*4882a593Smuzhiyun idx = mvif->omac_idx > EXT_BSSID_START ? HW_BSSID_0 : mvif->omac_idx;
814*4882a593Smuzhiyun omac->conn_type = cpu_to_le32(type);
815*4882a593Smuzhiyun omac->omac_idx = mvif->omac_idx;
816*4882a593Smuzhiyun omac->band_idx = mvif->band_idx;
817*4882a593Smuzhiyun omac->hw_bss_idx = idx;
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun struct mt7915_he_obss_narrow_bw_ru_data {
821*4882a593Smuzhiyun bool tolerated;
822*4882a593Smuzhiyun };
823*4882a593Smuzhiyun
mt7915_check_he_obss_narrow_bw_ru_iter(struct wiphy * wiphy,struct cfg80211_bss * bss,void * _data)824*4882a593Smuzhiyun static void mt7915_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy,
825*4882a593Smuzhiyun struct cfg80211_bss *bss,
826*4882a593Smuzhiyun void *_data)
827*4882a593Smuzhiyun {
828*4882a593Smuzhiyun struct mt7915_he_obss_narrow_bw_ru_data *data = _data;
829*4882a593Smuzhiyun const struct element *elem;
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun elem = ieee80211_bss_get_elem(bss, WLAN_EID_EXT_CAPABILITY);
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (!elem || elem->datalen <= 10 ||
834*4882a593Smuzhiyun !(elem->data[10] &
835*4882a593Smuzhiyun WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT))
836*4882a593Smuzhiyun data->tolerated = false;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun
mt7915_check_he_obss_narrow_bw_ru(struct ieee80211_hw * hw,struct ieee80211_vif * vif)839*4882a593Smuzhiyun static bool mt7915_check_he_obss_narrow_bw_ru(struct ieee80211_hw *hw,
840*4882a593Smuzhiyun struct ieee80211_vif *vif)
841*4882a593Smuzhiyun {
842*4882a593Smuzhiyun struct mt7915_he_obss_narrow_bw_ru_data iter_data = {
843*4882a593Smuzhiyun .tolerated = true,
844*4882a593Smuzhiyun };
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR))
847*4882a593Smuzhiyun return false;
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef,
850*4882a593Smuzhiyun mt7915_check_he_obss_narrow_bw_ru_iter,
851*4882a593Smuzhiyun &iter_data);
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun /*
854*4882a593Smuzhiyun * If there is at least one AP on radar channel that cannot
855*4882a593Smuzhiyun * tolerate 26-tone RU UL OFDMA transmissions using HE TB PPDU.
856*4882a593Smuzhiyun */
857*4882a593Smuzhiyun return !iter_data.tolerated;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun static void
mt7915_mcu_bss_rfch_tlv(struct sk_buff * skb,struct ieee80211_vif * vif,struct mt7915_phy * phy)861*4882a593Smuzhiyun mt7915_mcu_bss_rfch_tlv(struct sk_buff *skb, struct ieee80211_vif *vif,
862*4882a593Smuzhiyun struct mt7915_phy *phy)
863*4882a593Smuzhiyun {
864*4882a593Smuzhiyun struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
865*4882a593Smuzhiyun struct bss_info_rf_ch *ch;
866*4882a593Smuzhiyun struct tlv *tlv;
867*4882a593Smuzhiyun int freq1 = chandef->center_freq1;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_RF_CH, sizeof(*ch));
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun ch = (struct bss_info_rf_ch *)tlv;
872*4882a593Smuzhiyun ch->pri_ch = chandef->chan->hw_value;
873*4882a593Smuzhiyun ch->center_ch0 = ieee80211_frequency_to_channel(freq1);
874*4882a593Smuzhiyun ch->bw = mt7915_mcu_chan_bw(chandef);
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun if (chandef->width == NL80211_CHAN_WIDTH_80P80) {
877*4882a593Smuzhiyun int freq2 = chandef->center_freq2;
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun ch->center_ch1 = ieee80211_frequency_to_channel(freq2);
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun if (vif->bss_conf.he_support && vif->type == NL80211_IFTYPE_STATION) {
883*4882a593Smuzhiyun struct mt7915_dev *dev = phy->dev;
884*4882a593Smuzhiyun struct mt76_phy *mphy = &dev->mt76.phy;
885*4882a593Smuzhiyun bool ext_phy = phy != &dev->phy;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun if (ext_phy && dev->mt76.phy2)
888*4882a593Smuzhiyun mphy = dev->mt76.phy2;
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun ch->he_ru26_block =
891*4882a593Smuzhiyun mt7915_check_he_obss_narrow_bw_ru(mphy->hw, vif);
892*4882a593Smuzhiyun ch->he_all_disable = false;
893*4882a593Smuzhiyun } else {
894*4882a593Smuzhiyun ch->he_all_disable = true;
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun static void
mt7915_mcu_bss_ra_tlv(struct sk_buff * skb,struct ieee80211_vif * vif,struct mt7915_phy * phy)899*4882a593Smuzhiyun mt7915_mcu_bss_ra_tlv(struct sk_buff *skb, struct ieee80211_vif *vif,
900*4882a593Smuzhiyun struct mt7915_phy *phy)
901*4882a593Smuzhiyun {
902*4882a593Smuzhiyun struct bss_info_ra *ra;
903*4882a593Smuzhiyun struct tlv *tlv;
904*4882a593Smuzhiyun int max_nss = hweight8(phy->chainmask);
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_RA, sizeof(*ra));
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun ra = (struct bss_info_ra *)tlv;
909*4882a593Smuzhiyun ra->op_mode = vif->type == NL80211_IFTYPE_AP;
910*4882a593Smuzhiyun ra->adhoc_en = vif->type == NL80211_IFTYPE_ADHOC;
911*4882a593Smuzhiyun ra->short_preamble = true;
912*4882a593Smuzhiyun ra->tx_streams = max_nss;
913*4882a593Smuzhiyun ra->rx_streams = max_nss;
914*4882a593Smuzhiyun ra->algo = 4;
915*4882a593Smuzhiyun ra->train_up_rule = 2;
916*4882a593Smuzhiyun ra->train_up_high_thres = 110;
917*4882a593Smuzhiyun ra->train_up_rule_rssi = -70;
918*4882a593Smuzhiyun ra->low_traffic_thres = 2;
919*4882a593Smuzhiyun ra->phy_cap = cpu_to_le32(0xfdf);
920*4882a593Smuzhiyun ra->interval = cpu_to_le32(500);
921*4882a593Smuzhiyun ra->fast_interval = cpu_to_le32(100);
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun static void
mt7915_mcu_bss_he_tlv(struct sk_buff * skb,struct ieee80211_vif * vif,struct mt7915_phy * phy)925*4882a593Smuzhiyun mt7915_mcu_bss_he_tlv(struct sk_buff *skb, struct ieee80211_vif *vif,
926*4882a593Smuzhiyun struct mt7915_phy *phy)
927*4882a593Smuzhiyun {
928*4882a593Smuzhiyun #define DEFAULT_HE_PE_DURATION 4
929*4882a593Smuzhiyun #define DEFAULT_HE_DURATION_RTS_THRES 1023
930*4882a593Smuzhiyun const struct ieee80211_sta_he_cap *cap;
931*4882a593Smuzhiyun struct bss_info_he *he;
932*4882a593Smuzhiyun struct tlv *tlv;
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun cap = mt7915_get_he_phy_cap(phy, vif);
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_HE_BASIC, sizeof(*he));
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun he = (struct bss_info_he *)tlv;
939*4882a593Smuzhiyun he->he_pe_duration = vif->bss_conf.htc_trig_based_pkt_ext;
940*4882a593Smuzhiyun if (!he->he_pe_duration)
941*4882a593Smuzhiyun he->he_pe_duration = DEFAULT_HE_PE_DURATION;
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun he->he_rts_thres = cpu_to_le16(vif->bss_conf.frame_time_rts_th);
944*4882a593Smuzhiyun if (!he->he_rts_thres)
945*4882a593Smuzhiyun he->he_rts_thres = cpu_to_le16(DEFAULT_HE_DURATION_RTS_THRES);
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun he->max_nss_mcs[CMD_HE_MCS_BW80] = cap->he_mcs_nss_supp.tx_mcs_80;
948*4882a593Smuzhiyun he->max_nss_mcs[CMD_HE_MCS_BW160] = cap->he_mcs_nss_supp.tx_mcs_160;
949*4882a593Smuzhiyun he->max_nss_mcs[CMD_HE_MCS_BW8080] = cap->he_mcs_nss_supp.tx_mcs_80p80;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun static void
mt7915_mcu_bss_hw_amsdu_tlv(struct sk_buff * skb)953*4882a593Smuzhiyun mt7915_mcu_bss_hw_amsdu_tlv(struct sk_buff *skb)
954*4882a593Smuzhiyun {
955*4882a593Smuzhiyun #define TXD_CMP_MAP1 GENMASK(15, 0)
956*4882a593Smuzhiyun #define TXD_CMP_MAP2 (GENMASK(31, 0) & ~BIT(23))
957*4882a593Smuzhiyun struct bss_info_hw_amsdu *amsdu;
958*4882a593Smuzhiyun struct tlv *tlv;
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_HW_AMSDU, sizeof(*amsdu));
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun amsdu = (struct bss_info_hw_amsdu *)tlv;
963*4882a593Smuzhiyun amsdu->cmp_bitmap_0 = cpu_to_le32(TXD_CMP_MAP1);
964*4882a593Smuzhiyun amsdu->cmp_bitmap_1 = cpu_to_le32(TXD_CMP_MAP2);
965*4882a593Smuzhiyun amsdu->trig_thres = cpu_to_le16(2);
966*4882a593Smuzhiyun amsdu->enable = true;
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun static void
mt7915_mcu_bss_ext_tlv(struct sk_buff * skb,struct mt7915_vif * mvif)970*4882a593Smuzhiyun mt7915_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt7915_vif *mvif)
971*4882a593Smuzhiyun {
972*4882a593Smuzhiyun /* SIFS 20us + 512 byte beacon tranmitted by 1Mbps (3906us) */
973*4882a593Smuzhiyun #define BCN_TX_ESTIMATE_TIME (4096 + 20)
974*4882a593Smuzhiyun struct bss_info_ext_bss *ext;
975*4882a593Smuzhiyun int ext_bss_idx, tsf_offset;
976*4882a593Smuzhiyun struct tlv *tlv;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun ext_bss_idx = mvif->omac_idx - EXT_BSSID_START;
979*4882a593Smuzhiyun if (ext_bss_idx < 0)
980*4882a593Smuzhiyun return;
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_EXT_BSS, sizeof(*ext));
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun ext = (struct bss_info_ext_bss *)tlv;
985*4882a593Smuzhiyun tsf_offset = ext_bss_idx * BCN_TX_ESTIMATE_TIME;
986*4882a593Smuzhiyun ext->mbss_tsf_offset = cpu_to_le32(tsf_offset);
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun static void
mt7915_mcu_bss_bmc_tlv(struct sk_buff * skb,struct mt7915_phy * phy)990*4882a593Smuzhiyun mt7915_mcu_bss_bmc_tlv(struct sk_buff *skb, struct mt7915_phy *phy)
991*4882a593Smuzhiyun {
992*4882a593Smuzhiyun struct bss_info_bmc_rate *bmc;
993*4882a593Smuzhiyun struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
994*4882a593Smuzhiyun enum nl80211_band band = chandef->chan->band;
995*4882a593Smuzhiyun struct tlv *tlv;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_BMC_RATE, sizeof(*bmc));
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun bmc = (struct bss_info_bmc_rate *)tlv;
1000*4882a593Smuzhiyun if (band == NL80211_BAND_2GHZ) {
1001*4882a593Smuzhiyun bmc->short_preamble = true;
1002*4882a593Smuzhiyun } else {
1003*4882a593Smuzhiyun bmc->bc_trans = cpu_to_le16(0x2000);
1004*4882a593Smuzhiyun bmc->mc_trans = cpu_to_le16(0x2080);
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun static void
mt7915_mcu_bss_sync_tlv(struct sk_buff * skb,struct ieee80211_vif * vif)1009*4882a593Smuzhiyun mt7915_mcu_bss_sync_tlv(struct sk_buff *skb, struct ieee80211_vif *vif)
1010*4882a593Smuzhiyun {
1011*4882a593Smuzhiyun struct bss_info_sync_mode *sync;
1012*4882a593Smuzhiyun struct tlv *tlv;
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, BSS_INFO_SYNC_MODE, sizeof(*sync));
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun sync = (struct bss_info_sync_mode *)tlv;
1017*4882a593Smuzhiyun sync->bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int);
1018*4882a593Smuzhiyun sync->dtim_period = vif->bss_conf.dtim_period;
1019*4882a593Smuzhiyun sync->enable = true;
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun
mt7915_mcu_add_bss_info(struct mt7915_phy * phy,struct ieee80211_vif * vif,int enable)1022*4882a593Smuzhiyun int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
1023*4882a593Smuzhiyun struct ieee80211_vif *vif, int enable)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1026*4882a593Smuzhiyun struct sk_buff *skb;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(phy->dev, mvif, NULL,
1029*4882a593Smuzhiyun MT7915_BSS_UPDATE_MAX_SIZE);
1030*4882a593Smuzhiyun if (IS_ERR(skb))
1031*4882a593Smuzhiyun return PTR_ERR(skb);
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun /* bss_omac must be first */
1034*4882a593Smuzhiyun if (enable)
1035*4882a593Smuzhiyun mt7915_mcu_bss_omac_tlv(skb, vif);
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun mt7915_mcu_bss_basic_tlv(skb, vif, phy, enable);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (enable) {
1040*4882a593Smuzhiyun mt7915_mcu_bss_rfch_tlv(skb, vif, phy);
1041*4882a593Smuzhiyun mt7915_mcu_bss_bmc_tlv(skb, phy);
1042*4882a593Smuzhiyun mt7915_mcu_bss_ra_tlv(skb, vif, phy);
1043*4882a593Smuzhiyun mt7915_mcu_bss_hw_amsdu_tlv(skb);
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun if (vif->bss_conf.he_support)
1046*4882a593Smuzhiyun mt7915_mcu_bss_he_tlv(skb, vif, phy);
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun if (mvif->omac_idx > HW_BSSID_MAX)
1049*4882a593Smuzhiyun mt7915_mcu_bss_ext_tlv(skb, mvif);
1050*4882a593Smuzhiyun else
1051*4882a593Smuzhiyun mt7915_mcu_bss_sync_tlv(skb, vif);
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&phy->dev->mt76, skb,
1055*4882a593Smuzhiyun MCU_EXT_CMD_BSS_INFO_UPDATE, true);
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun /** starec & wtbl **/
1059*4882a593Smuzhiyun static int
mt7915_mcu_sta_key_tlv(struct sk_buff * skb,struct ieee80211_key_conf * key,enum set_key_cmd cmd)1060*4882a593Smuzhiyun mt7915_mcu_sta_key_tlv(struct sk_buff *skb, struct ieee80211_key_conf *key,
1061*4882a593Smuzhiyun enum set_key_cmd cmd)
1062*4882a593Smuzhiyun {
1063*4882a593Smuzhiyun struct sta_rec_sec *sec;
1064*4882a593Smuzhiyun struct tlv *tlv;
1065*4882a593Smuzhiyun u32 len = sizeof(*sec);
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_KEY_V2, sizeof(*sec));
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun sec = (struct sta_rec_sec *)tlv;
1070*4882a593Smuzhiyun sec->add = cmd;
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun if (cmd == SET_KEY) {
1073*4882a593Smuzhiyun struct sec_key *sec_key;
1074*4882a593Smuzhiyun u8 cipher;
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun cipher = mt7915_mcu_get_cipher(key->cipher);
1077*4882a593Smuzhiyun if (cipher == MT_CIPHER_NONE)
1078*4882a593Smuzhiyun return -EOPNOTSUPP;
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun sec_key = &sec->key[0];
1081*4882a593Smuzhiyun sec_key->cipher_len = sizeof(*sec_key);
1082*4882a593Smuzhiyun sec_key->key_id = key->keyidx;
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun if (cipher == MT_CIPHER_BIP_CMAC_128) {
1085*4882a593Smuzhiyun sec_key->cipher_id = MT_CIPHER_AES_CCMP;
1086*4882a593Smuzhiyun sec_key->key_len = 16;
1087*4882a593Smuzhiyun memcpy(sec_key->key, key->key, 16);
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun sec_key = &sec->key[1];
1090*4882a593Smuzhiyun sec_key->cipher_id = MT_CIPHER_BIP_CMAC_128;
1091*4882a593Smuzhiyun sec_key->cipher_len = sizeof(*sec_key);
1092*4882a593Smuzhiyun sec_key->key_len = 16;
1093*4882a593Smuzhiyun memcpy(sec_key->key, key->key + 16, 16);
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun sec->n_cipher = 2;
1096*4882a593Smuzhiyun } else {
1097*4882a593Smuzhiyun sec_key->cipher_id = cipher;
1098*4882a593Smuzhiyun sec_key->key_len = key->keylen;
1099*4882a593Smuzhiyun memcpy(sec_key->key, key->key, key->keylen);
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun if (cipher == MT_CIPHER_TKIP) {
1102*4882a593Smuzhiyun /* Rx/Tx MIC keys are swapped */
1103*4882a593Smuzhiyun memcpy(sec_key->key + 16, key->key + 24, 8);
1104*4882a593Smuzhiyun memcpy(sec_key->key + 24, key->key + 16, 8);
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun len -= sizeof(*sec_key);
1108*4882a593Smuzhiyun sec->n_cipher = 1;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun } else {
1111*4882a593Smuzhiyun len -= sizeof(sec->key);
1112*4882a593Smuzhiyun sec->n_cipher = 0;
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun sec->len = cpu_to_le16(len);
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun return 0;
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun
mt7915_mcu_add_key(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct mt7915_sta * msta,struct ieee80211_key_conf * key,enum set_key_cmd cmd)1119*4882a593Smuzhiyun int mt7915_mcu_add_key(struct mt7915_dev *dev, struct ieee80211_vif *vif,
1120*4882a593Smuzhiyun struct mt7915_sta *msta, struct ieee80211_key_conf *key,
1121*4882a593Smuzhiyun enum set_key_cmd cmd)
1122*4882a593Smuzhiyun {
1123*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1124*4882a593Smuzhiyun struct sk_buff *skb;
1125*4882a593Smuzhiyun int len = sizeof(struct sta_req_hdr) + sizeof(struct sta_rec_sec);
1126*4882a593Smuzhiyun int ret;
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta, len);
1129*4882a593Smuzhiyun if (IS_ERR(skb))
1130*4882a593Smuzhiyun return PTR_ERR(skb);
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun ret = mt7915_mcu_sta_key_tlv(skb, key, cmd);
1133*4882a593Smuzhiyun if (ret)
1134*4882a593Smuzhiyun return ret;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
1137*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun static void
mt7915_mcu_sta_ba_tlv(struct sk_buff * skb,struct ieee80211_ampdu_params * params,bool enable,bool tx)1141*4882a593Smuzhiyun mt7915_mcu_sta_ba_tlv(struct sk_buff *skb,
1142*4882a593Smuzhiyun struct ieee80211_ampdu_params *params,
1143*4882a593Smuzhiyun bool enable, bool tx)
1144*4882a593Smuzhiyun {
1145*4882a593Smuzhiyun struct sta_rec_ba *ba;
1146*4882a593Smuzhiyun struct tlv *tlv;
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_BA, sizeof(*ba));
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun ba = (struct sta_rec_ba *)tlv;
1151*4882a593Smuzhiyun ba->ba_type = tx ? MT_BA_TYPE_ORIGINATOR : MT_BA_TYPE_RECIPIENT,
1152*4882a593Smuzhiyun ba->winsize = cpu_to_le16(params->buf_size);
1153*4882a593Smuzhiyun ba->ssn = cpu_to_le16(params->ssn);
1154*4882a593Smuzhiyun ba->ba_en = enable << params->tid;
1155*4882a593Smuzhiyun ba->amsdu = params->amsdu;
1156*4882a593Smuzhiyun ba->tid = params->tid;
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun static void
mt7915_mcu_wtbl_ba_tlv(struct sk_buff * skb,struct ieee80211_ampdu_params * params,bool enable,bool tx,void * sta_wtbl,void * wtbl_tlv)1160*4882a593Smuzhiyun mt7915_mcu_wtbl_ba_tlv(struct sk_buff *skb,
1161*4882a593Smuzhiyun struct ieee80211_ampdu_params *params,
1162*4882a593Smuzhiyun bool enable, bool tx, void *sta_wtbl,
1163*4882a593Smuzhiyun void *wtbl_tlv)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun struct wtbl_ba *ba;
1166*4882a593Smuzhiyun struct tlv *tlv;
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_tlv(skb, WTBL_BA, sizeof(*ba),
1169*4882a593Smuzhiyun wtbl_tlv, sta_wtbl);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun ba = (struct wtbl_ba *)tlv;
1172*4882a593Smuzhiyun ba->tid = params->tid;
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun if (tx) {
1175*4882a593Smuzhiyun ba->ba_type = MT_BA_TYPE_ORIGINATOR;
1176*4882a593Smuzhiyun ba->sn = enable ? cpu_to_le16(params->ssn) : 0;
1177*4882a593Smuzhiyun ba->ba_en = enable;
1178*4882a593Smuzhiyun } else {
1179*4882a593Smuzhiyun memcpy(ba->peer_addr, params->sta->addr, ETH_ALEN);
1180*4882a593Smuzhiyun ba->ba_type = MT_BA_TYPE_RECIPIENT;
1181*4882a593Smuzhiyun ba->rst_ba_tid = params->tid;
1182*4882a593Smuzhiyun ba->rst_ba_sel = RST_BA_MAC_TID_MATCH;
1183*4882a593Smuzhiyun ba->rst_ba_sb = 1;
1184*4882a593Smuzhiyun }
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun if (enable && tx)
1187*4882a593Smuzhiyun ba->ba_winsize = cpu_to_le16(params->buf_size);
1188*4882a593Smuzhiyun }
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun static int
mt7915_mcu_sta_ba(struct mt7915_dev * dev,struct ieee80211_ampdu_params * params,bool enable,bool tx)1191*4882a593Smuzhiyun mt7915_mcu_sta_ba(struct mt7915_dev *dev,
1192*4882a593Smuzhiyun struct ieee80211_ampdu_params *params,
1193*4882a593Smuzhiyun bool enable, bool tx)
1194*4882a593Smuzhiyun {
1195*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)params->sta->drv_priv;
1196*4882a593Smuzhiyun struct mt7915_vif *mvif = msta->vif;
1197*4882a593Smuzhiyun struct wtbl_req_hdr *wtbl_hdr;
1198*4882a593Smuzhiyun struct tlv *sta_wtbl;
1199*4882a593Smuzhiyun struct sk_buff *skb;
1200*4882a593Smuzhiyun int ret;
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun if (enable && tx && !params->amsdu)
1203*4882a593Smuzhiyun msta->wcid.amsdu = false;
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta,
1206*4882a593Smuzhiyun MT7915_STA_UPDATE_MAX_SIZE);
1207*4882a593Smuzhiyun if (IS_ERR(skb))
1208*4882a593Smuzhiyun return PTR_ERR(skb);
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun sta_wtbl = mt7915_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv));
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun wtbl_hdr = mt7915_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, sta_wtbl,
1213*4882a593Smuzhiyun &skb);
1214*4882a593Smuzhiyun mt7915_mcu_wtbl_ba_tlv(skb, params, enable, tx, sta_wtbl, wtbl_hdr);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun ret = __mt76_mcu_skb_send_msg(&dev->mt76, skb,
1217*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
1218*4882a593Smuzhiyun if (ret)
1219*4882a593Smuzhiyun return ret;
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta,
1222*4882a593Smuzhiyun MT7915_STA_UPDATE_MAX_SIZE);
1223*4882a593Smuzhiyun if (IS_ERR(skb))
1224*4882a593Smuzhiyun return PTR_ERR(skb);
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun mt7915_mcu_sta_ba_tlv(skb, params, enable, tx);
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
1229*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
1230*4882a593Smuzhiyun }
1231*4882a593Smuzhiyun
mt7915_mcu_add_tx_ba(struct mt7915_dev * dev,struct ieee80211_ampdu_params * params,bool enable)1232*4882a593Smuzhiyun int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,
1233*4882a593Smuzhiyun struct ieee80211_ampdu_params *params,
1234*4882a593Smuzhiyun bool enable)
1235*4882a593Smuzhiyun {
1236*4882a593Smuzhiyun return mt7915_mcu_sta_ba(dev, params, enable, true);
1237*4882a593Smuzhiyun }
1238*4882a593Smuzhiyun
mt7915_mcu_add_rx_ba(struct mt7915_dev * dev,struct ieee80211_ampdu_params * params,bool enable)1239*4882a593Smuzhiyun int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,
1240*4882a593Smuzhiyun struct ieee80211_ampdu_params *params,
1241*4882a593Smuzhiyun bool enable)
1242*4882a593Smuzhiyun {
1243*4882a593Smuzhiyun return mt7915_mcu_sta_ba(dev, params, enable, false);
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun static void
mt7915_mcu_wtbl_generic_tlv(struct sk_buff * skb,struct ieee80211_vif * vif,struct ieee80211_sta * sta,void * sta_wtbl,void * wtbl_tlv)1247*4882a593Smuzhiyun mt7915_mcu_wtbl_generic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif,
1248*4882a593Smuzhiyun struct ieee80211_sta *sta, void *sta_wtbl,
1249*4882a593Smuzhiyun void *wtbl_tlv)
1250*4882a593Smuzhiyun {
1251*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1252*4882a593Smuzhiyun struct wtbl_generic *generic;
1253*4882a593Smuzhiyun struct wtbl_rx *rx;
1254*4882a593Smuzhiyun struct tlv *tlv;
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_tlv(skb, WTBL_GENERIC, sizeof(*generic),
1257*4882a593Smuzhiyun wtbl_tlv, sta_wtbl);
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun generic = (struct wtbl_generic *)tlv;
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun if (sta) {
1262*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_STATION)
1263*4882a593Smuzhiyun generic->partial_aid = cpu_to_le16(vif->bss_conf.aid);
1264*4882a593Smuzhiyun else
1265*4882a593Smuzhiyun generic->partial_aid = cpu_to_le16(sta->aid);
1266*4882a593Smuzhiyun memcpy(generic->peer_addr, sta->addr, ETH_ALEN);
1267*4882a593Smuzhiyun generic->muar_idx = mvif->omac_idx;
1268*4882a593Smuzhiyun generic->qos = sta->wme;
1269*4882a593Smuzhiyun } else {
1270*4882a593Smuzhiyun /* use BSSID in station mode */
1271*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_STATION)
1272*4882a593Smuzhiyun memcpy(generic->peer_addr, vif->bss_conf.bssid,
1273*4882a593Smuzhiyun ETH_ALEN);
1274*4882a593Smuzhiyun else
1275*4882a593Smuzhiyun eth_broadcast_addr(generic->peer_addr);
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun generic->muar_idx = 0xe;
1278*4882a593Smuzhiyun }
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_tlv(skb, WTBL_RX, sizeof(*rx),
1281*4882a593Smuzhiyun wtbl_tlv, sta_wtbl);
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun rx = (struct wtbl_rx *)tlv;
1284*4882a593Smuzhiyun rx->rca1 = sta ? vif->type != NL80211_IFTYPE_AP : 1;
1285*4882a593Smuzhiyun rx->rca2 = 1;
1286*4882a593Smuzhiyun rx->rv = 1;
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun static void
mt7915_mcu_sta_basic_tlv(struct sk_buff * skb,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1290*4882a593Smuzhiyun mt7915_mcu_sta_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif,
1291*4882a593Smuzhiyun struct ieee80211_sta *sta, bool enable)
1292*4882a593Smuzhiyun {
1293*4882a593Smuzhiyun #define EXTRA_INFO_VER BIT(0)
1294*4882a593Smuzhiyun #define EXTRA_INFO_NEW BIT(1)
1295*4882a593Smuzhiyun struct sta_rec_basic *basic;
1296*4882a593Smuzhiyun struct tlv *tlv;
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_BASIC, sizeof(*basic));
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun basic = (struct sta_rec_basic *)tlv;
1301*4882a593Smuzhiyun basic->extra_info = cpu_to_le16(EXTRA_INFO_VER);
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun if (enable) {
1304*4882a593Smuzhiyun basic->extra_info |= cpu_to_le16(EXTRA_INFO_NEW);
1305*4882a593Smuzhiyun basic->conn_state = CONN_STATE_PORT_SECURE;
1306*4882a593Smuzhiyun } else {
1307*4882a593Smuzhiyun basic->conn_state = CONN_STATE_DISCONNECT;
1308*4882a593Smuzhiyun }
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun if (!sta) {
1311*4882a593Smuzhiyun basic->conn_type = cpu_to_le32(CONNECTION_INFRA_BC);
1312*4882a593Smuzhiyun eth_broadcast_addr(basic->peer_addr);
1313*4882a593Smuzhiyun return;
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun switch (vif->type) {
1317*4882a593Smuzhiyun case NL80211_IFTYPE_MESH_POINT:
1318*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
1319*4882a593Smuzhiyun basic->conn_type = cpu_to_le32(CONNECTION_INFRA_STA);
1320*4882a593Smuzhiyun basic->aid = cpu_to_le16(sta->aid);
1321*4882a593Smuzhiyun break;
1322*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
1323*4882a593Smuzhiyun basic->conn_type = cpu_to_le32(CONNECTION_INFRA_AP);
1324*4882a593Smuzhiyun basic->aid = cpu_to_le16(vif->bss_conf.aid);
1325*4882a593Smuzhiyun break;
1326*4882a593Smuzhiyun case NL80211_IFTYPE_ADHOC:
1327*4882a593Smuzhiyun basic->conn_type = cpu_to_le32(CONNECTION_IBSS_ADHOC);
1328*4882a593Smuzhiyun basic->aid = cpu_to_le16(sta->aid);
1329*4882a593Smuzhiyun break;
1330*4882a593Smuzhiyun default:
1331*4882a593Smuzhiyun WARN_ON(1);
1332*4882a593Smuzhiyun break;
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun memcpy(basic->peer_addr, sta->addr, ETH_ALEN);
1336*4882a593Smuzhiyun basic->qos = sta->wme;
1337*4882a593Smuzhiyun }
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun static void
mt7915_mcu_sta_he_tlv(struct sk_buff * skb,struct ieee80211_sta * sta)1340*4882a593Smuzhiyun mt7915_mcu_sta_he_tlv(struct sk_buff *skb, struct ieee80211_sta *sta)
1341*4882a593Smuzhiyun {
1342*4882a593Smuzhiyun struct ieee80211_sta_he_cap *he_cap = &sta->he_cap;
1343*4882a593Smuzhiyun struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
1344*4882a593Smuzhiyun struct sta_rec_he *he;
1345*4882a593Smuzhiyun struct tlv *tlv;
1346*4882a593Smuzhiyun u32 cap = 0;
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_HE, sizeof(*he));
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun he = (struct sta_rec_he *)tlv;
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun if (elem->mac_cap_info[0] & IEEE80211_HE_MAC_CAP0_HTC_HE)
1353*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_HTC;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun if (elem->mac_cap_info[2] & IEEE80211_HE_MAC_CAP2_BSR)
1356*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_BSR;
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun if (elem->mac_cap_info[3] & IEEE80211_HE_MAC_CAP3_OMI_CONTROL)
1359*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_OM;
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun if (elem->mac_cap_info[4] & IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU)
1362*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_AMSDU_IN_AMPDU;
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun if (elem->mac_cap_info[4] & IEEE80211_HE_MAC_CAP4_BQR)
1365*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_BQR;
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun if (elem->phy_cap_info[0] &
1368*4882a593Smuzhiyun (IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G |
1369*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G))
1370*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_BW20_RU242_SUPPORT;
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun if (elem->phy_cap_info[1] &
1373*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
1374*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_LDPC;
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun if (elem->phy_cap_info[1] &
1377*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US)
1378*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI;
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun if (elem->phy_cap_info[2] &
1381*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US)
1382*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI;
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun if (elem->phy_cap_info[2] &
1385*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ)
1386*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_LE_EQ_80M_TX_STBC;
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun if (elem->phy_cap_info[2] &
1389*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
1390*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_LE_EQ_80M_RX_STBC;
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun if (elem->phy_cap_info[6] &
1393*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE)
1394*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE;
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun if (elem->phy_cap_info[7] &
1397*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI)
1398*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI;
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun if (elem->phy_cap_info[7] &
1401*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ)
1402*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_GT_80M_TX_STBC;
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun if (elem->phy_cap_info[7] &
1405*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ)
1406*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_GT_80M_RX_STBC;
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun if (elem->phy_cap_info[8] &
1409*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI)
1410*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI;
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun if (elem->phy_cap_info[8] &
1413*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI)
1414*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI;
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun if (elem->phy_cap_info[9] &
1417*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK)
1418*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_TRIG_CQI_FK;
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun if (elem->phy_cap_info[9] &
1421*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU)
1422*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242;
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun if (elem->phy_cap_info[9] &
1425*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU)
1426*4882a593Smuzhiyun cap |= STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242;
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun he->he_cap = cpu_to_le32(cap);
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun switch (sta->bandwidth) {
1431*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_160:
1432*4882a593Smuzhiyun if (elem->phy_cap_info[0] &
1433*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
1434*4882a593Smuzhiyun he->max_nss_mcs[CMD_HE_MCS_BW8080] =
1435*4882a593Smuzhiyun he_cap->he_mcs_nss_supp.rx_mcs_80p80;
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun he->max_nss_mcs[CMD_HE_MCS_BW160] =
1438*4882a593Smuzhiyun he_cap->he_mcs_nss_supp.rx_mcs_160;
1439*4882a593Smuzhiyun fallthrough;
1440*4882a593Smuzhiyun default:
1441*4882a593Smuzhiyun he->max_nss_mcs[CMD_HE_MCS_BW80] =
1442*4882a593Smuzhiyun he_cap->he_mcs_nss_supp.rx_mcs_80;
1443*4882a593Smuzhiyun break;
1444*4882a593Smuzhiyun }
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun he->t_frame_dur =
1447*4882a593Smuzhiyun HE_MAC(CAP1_TF_MAC_PAD_DUR_MASK, elem->mac_cap_info[1]);
1448*4882a593Smuzhiyun he->max_ampdu_exp =
1449*4882a593Smuzhiyun HE_MAC(CAP3_MAX_AMPDU_LEN_EXP_MASK, elem->mac_cap_info[3]);
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun he->bw_set =
1452*4882a593Smuzhiyun HE_PHY(CAP0_CHANNEL_WIDTH_SET_MASK, elem->phy_cap_info[0]);
1453*4882a593Smuzhiyun he->device_class =
1454*4882a593Smuzhiyun HE_PHY(CAP1_DEVICE_CLASS_A, elem->phy_cap_info[1]);
1455*4882a593Smuzhiyun he->punc_pream_rx =
1456*4882a593Smuzhiyun HE_PHY(CAP1_PREAMBLE_PUNC_RX_MASK, elem->phy_cap_info[1]);
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun he->dcm_tx_mode =
1459*4882a593Smuzhiyun HE_PHY(CAP3_DCM_MAX_CONST_TX_MASK, elem->phy_cap_info[3]);
1460*4882a593Smuzhiyun he->dcm_tx_max_nss =
1461*4882a593Smuzhiyun HE_PHY(CAP3_DCM_MAX_TX_NSS_2, elem->phy_cap_info[3]);
1462*4882a593Smuzhiyun he->dcm_rx_mode =
1463*4882a593Smuzhiyun HE_PHY(CAP3_DCM_MAX_CONST_RX_MASK, elem->phy_cap_info[3]);
1464*4882a593Smuzhiyun he->dcm_rx_max_nss =
1465*4882a593Smuzhiyun HE_PHY(CAP3_DCM_MAX_RX_NSS_2, elem->phy_cap_info[3]);
1466*4882a593Smuzhiyun he->dcm_rx_max_nss =
1467*4882a593Smuzhiyun HE_PHY(CAP8_DCM_MAX_RU_MASK, elem->phy_cap_info[8]);
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun he->pkt_ext = 2;
1470*4882a593Smuzhiyun }
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun static void
mt7915_mcu_sta_uapsd_tlv(struct sk_buff * skb,struct ieee80211_sta * sta,struct ieee80211_vif * vif)1473*4882a593Smuzhiyun mt7915_mcu_sta_uapsd_tlv(struct sk_buff *skb, struct ieee80211_sta *sta,
1474*4882a593Smuzhiyun struct ieee80211_vif *vif)
1475*4882a593Smuzhiyun {
1476*4882a593Smuzhiyun struct sta_rec_uapsd *uapsd;
1477*4882a593Smuzhiyun struct tlv *tlv;
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun if (vif->type != NL80211_IFTYPE_AP || !sta->wme)
1480*4882a593Smuzhiyun return;
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_APPS, sizeof(*uapsd));
1483*4882a593Smuzhiyun uapsd = (struct sta_rec_uapsd *)tlv;
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_VO) {
1486*4882a593Smuzhiyun uapsd->dac_map |= BIT(3);
1487*4882a593Smuzhiyun uapsd->tac_map |= BIT(3);
1488*4882a593Smuzhiyun }
1489*4882a593Smuzhiyun if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_VI) {
1490*4882a593Smuzhiyun uapsd->dac_map |= BIT(2);
1491*4882a593Smuzhiyun uapsd->tac_map |= BIT(2);
1492*4882a593Smuzhiyun }
1493*4882a593Smuzhiyun if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_BE) {
1494*4882a593Smuzhiyun uapsd->dac_map |= BIT(1);
1495*4882a593Smuzhiyun uapsd->tac_map |= BIT(1);
1496*4882a593Smuzhiyun }
1497*4882a593Smuzhiyun if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_BK) {
1498*4882a593Smuzhiyun uapsd->dac_map |= BIT(0);
1499*4882a593Smuzhiyun uapsd->tac_map |= BIT(0);
1500*4882a593Smuzhiyun }
1501*4882a593Smuzhiyun uapsd->max_sp = sta->max_sp;
1502*4882a593Smuzhiyun }
1503*4882a593Smuzhiyun
1504*4882a593Smuzhiyun static void
mt7915_mcu_sta_muru_tlv(struct sk_buff * skb,struct ieee80211_sta * sta)1505*4882a593Smuzhiyun mt7915_mcu_sta_muru_tlv(struct sk_buff *skb, struct ieee80211_sta *sta)
1506*4882a593Smuzhiyun {
1507*4882a593Smuzhiyun struct ieee80211_sta_he_cap *he_cap = &sta->he_cap;
1508*4882a593Smuzhiyun struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
1509*4882a593Smuzhiyun struct sta_rec_muru *muru;
1510*4882a593Smuzhiyun struct tlv *tlv;
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_MURU, sizeof(*muru));
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun muru = (struct sta_rec_muru *)tlv;
1515*4882a593Smuzhiyun muru->cfg.ofdma_dl_en = true;
1516*4882a593Smuzhiyun muru->cfg.ofdma_ul_en = true;
1517*4882a593Smuzhiyun muru->cfg.mimo_dl_en = true;
1518*4882a593Smuzhiyun muru->cfg.mimo_ul_en = true;
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun muru->ofdma_dl.punc_pream_rx =
1521*4882a593Smuzhiyun HE_PHY(CAP1_PREAMBLE_PUNC_RX_MASK, elem->phy_cap_info[1]);
1522*4882a593Smuzhiyun muru->ofdma_dl.he_20m_in_40m_2g =
1523*4882a593Smuzhiyun HE_PHY(CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G, elem->phy_cap_info[8]);
1524*4882a593Smuzhiyun muru->ofdma_dl.he_20m_in_160m =
1525*4882a593Smuzhiyun HE_PHY(CAP8_20MHZ_IN_160MHZ_HE_PPDU, elem->phy_cap_info[8]);
1526*4882a593Smuzhiyun muru->ofdma_dl.he_80m_in_160m =
1527*4882a593Smuzhiyun HE_PHY(CAP8_80MHZ_IN_160MHZ_HE_PPDU, elem->phy_cap_info[8]);
1528*4882a593Smuzhiyun muru->ofdma_dl.lt16_sigb = 0;
1529*4882a593Smuzhiyun muru->ofdma_dl.rx_su_comp_sigb = 0;
1530*4882a593Smuzhiyun muru->ofdma_dl.rx_su_non_comp_sigb = 0;
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun muru->ofdma_ul.t_frame_dur =
1533*4882a593Smuzhiyun HE_MAC(CAP1_TF_MAC_PAD_DUR_MASK, elem->mac_cap_info[1]);
1534*4882a593Smuzhiyun muru->ofdma_ul.mu_cascading =
1535*4882a593Smuzhiyun HE_MAC(CAP2_MU_CASCADING, elem->mac_cap_info[2]);
1536*4882a593Smuzhiyun muru->ofdma_ul.uo_ra =
1537*4882a593Smuzhiyun HE_MAC(CAP3_OFDMA_RA, elem->mac_cap_info[3]);
1538*4882a593Smuzhiyun muru->ofdma_ul.he_2x996_tone = 0;
1539*4882a593Smuzhiyun muru->ofdma_ul.rx_t_frame_11ac = 0;
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun muru->mimo_dl.vht_mu_bfee =
1542*4882a593Smuzhiyun !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE);
1543*4882a593Smuzhiyun muru->mimo_dl.partial_bw_dl_mimo =
1544*4882a593Smuzhiyun HE_PHY(CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO, elem->phy_cap_info[6]);
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun muru->mimo_ul.full_ul_mimo =
1547*4882a593Smuzhiyun HE_PHY(CAP2_UL_MU_FULL_MU_MIMO, elem->phy_cap_info[2]);
1548*4882a593Smuzhiyun muru->mimo_ul.partial_ul_mimo =
1549*4882a593Smuzhiyun HE_PHY(CAP2_UL_MU_PARTIAL_MU_MIMO, elem->phy_cap_info[2]);
1550*4882a593Smuzhiyun }
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun static int
mt7915_mcu_add_mu(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1553*4882a593Smuzhiyun mt7915_mcu_add_mu(struct mt7915_dev *dev, struct ieee80211_vif *vif,
1554*4882a593Smuzhiyun struct ieee80211_sta *sta)
1555*4882a593Smuzhiyun {
1556*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1557*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
1558*4882a593Smuzhiyun struct sk_buff *skb;
1559*4882a593Smuzhiyun int len = sizeof(struct sta_req_hdr) + sizeof(struct sta_rec_muru);
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun if (!sta->vht_cap.vht_supported && !sta->he_cap.has_he)
1562*4882a593Smuzhiyun return 0;
1563*4882a593Smuzhiyun
1564*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta, len);
1565*4882a593Smuzhiyun if (IS_ERR(skb))
1566*4882a593Smuzhiyun return PTR_ERR(skb);
1567*4882a593Smuzhiyun
1568*4882a593Smuzhiyun /* starec muru */
1569*4882a593Smuzhiyun mt7915_mcu_sta_muru_tlv(skb, sta);
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
1572*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun
1575*4882a593Smuzhiyun static void
mt7915_mcu_sta_amsdu_tlv(struct sk_buff * skb,struct ieee80211_sta * sta)1576*4882a593Smuzhiyun mt7915_mcu_sta_amsdu_tlv(struct sk_buff *skb, struct ieee80211_sta *sta)
1577*4882a593Smuzhiyun {
1578*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
1579*4882a593Smuzhiyun struct sta_rec_amsdu *amsdu;
1580*4882a593Smuzhiyun struct tlv *tlv;
1581*4882a593Smuzhiyun
1582*4882a593Smuzhiyun if (!sta->max_amsdu_len)
1583*4882a593Smuzhiyun return;
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_HW_AMSDU, sizeof(*amsdu));
1586*4882a593Smuzhiyun amsdu = (struct sta_rec_amsdu *)tlv;
1587*4882a593Smuzhiyun amsdu->max_amsdu_num = 8;
1588*4882a593Smuzhiyun amsdu->amsdu_en = true;
1589*4882a593Smuzhiyun amsdu->max_mpdu_size = sta->max_amsdu_len >=
1590*4882a593Smuzhiyun IEEE80211_MAX_MPDU_LEN_VHT_7991;
1591*4882a593Smuzhiyun msta->wcid.amsdu = true;
1592*4882a593Smuzhiyun }
1593*4882a593Smuzhiyun
1594*4882a593Smuzhiyun static bool
mt7915_hw_amsdu_supported(struct ieee80211_vif * vif)1595*4882a593Smuzhiyun mt7915_hw_amsdu_supported(struct ieee80211_vif *vif)
1596*4882a593Smuzhiyun {
1597*4882a593Smuzhiyun switch (vif->type) {
1598*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
1599*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
1600*4882a593Smuzhiyun return true;
1601*4882a593Smuzhiyun default:
1602*4882a593Smuzhiyun return false;
1603*4882a593Smuzhiyun }
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun static void
mt7915_mcu_sta_tlv(struct mt7915_dev * dev,struct sk_buff * skb,struct ieee80211_sta * sta,struct ieee80211_vif * vif)1607*4882a593Smuzhiyun mt7915_mcu_sta_tlv(struct mt7915_dev *dev, struct sk_buff *skb,
1608*4882a593Smuzhiyun struct ieee80211_sta *sta, struct ieee80211_vif *vif)
1609*4882a593Smuzhiyun {
1610*4882a593Smuzhiyun struct tlv *tlv;
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun /* starec ht */
1613*4882a593Smuzhiyun if (sta->ht_cap.ht_supported) {
1614*4882a593Smuzhiyun struct sta_rec_ht *ht;
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_HT, sizeof(*ht));
1617*4882a593Smuzhiyun ht = (struct sta_rec_ht *)tlv;
1618*4882a593Smuzhiyun ht->ht_cap = cpu_to_le16(sta->ht_cap.cap);
1619*4882a593Smuzhiyun
1620*4882a593Smuzhiyun if (mt7915_hw_amsdu_supported(vif))
1621*4882a593Smuzhiyun mt7915_mcu_sta_amsdu_tlv(skb, sta);
1622*4882a593Smuzhiyun }
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun /* starec vht */
1625*4882a593Smuzhiyun if (sta->vht_cap.vht_supported) {
1626*4882a593Smuzhiyun struct sta_rec_vht *vht;
1627*4882a593Smuzhiyun
1628*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_VHT, sizeof(*vht));
1629*4882a593Smuzhiyun vht = (struct sta_rec_vht *)tlv;
1630*4882a593Smuzhiyun vht->vht_cap = cpu_to_le32(sta->vht_cap.cap);
1631*4882a593Smuzhiyun vht->vht_rx_mcs_map = sta->vht_cap.vht_mcs.rx_mcs_map;
1632*4882a593Smuzhiyun vht->vht_tx_mcs_map = sta->vht_cap.vht_mcs.tx_mcs_map;
1633*4882a593Smuzhiyun }
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun /* starec he */
1636*4882a593Smuzhiyun if (sta->he_cap.has_he)
1637*4882a593Smuzhiyun mt7915_mcu_sta_he_tlv(skb, sta);
1638*4882a593Smuzhiyun
1639*4882a593Smuzhiyun /* starec uapsd */
1640*4882a593Smuzhiyun mt7915_mcu_sta_uapsd_tlv(skb, sta, vif);
1641*4882a593Smuzhiyun }
1642*4882a593Smuzhiyun
1643*4882a593Smuzhiyun static void
mt7915_mcu_wtbl_smps_tlv(struct sk_buff * skb,struct ieee80211_sta * sta,void * sta_wtbl,void * wtbl_tlv)1644*4882a593Smuzhiyun mt7915_mcu_wtbl_smps_tlv(struct sk_buff *skb, struct ieee80211_sta *sta,
1645*4882a593Smuzhiyun void *sta_wtbl, void *wtbl_tlv)
1646*4882a593Smuzhiyun {
1647*4882a593Smuzhiyun struct wtbl_smps *smps;
1648*4882a593Smuzhiyun struct tlv *tlv;
1649*4882a593Smuzhiyun
1650*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_tlv(skb, WTBL_SMPS, sizeof(*smps),
1651*4882a593Smuzhiyun wtbl_tlv, sta_wtbl);
1652*4882a593Smuzhiyun smps = (struct wtbl_smps *)tlv;
1653*4882a593Smuzhiyun
1654*4882a593Smuzhiyun if (sta->smps_mode == IEEE80211_SMPS_DYNAMIC)
1655*4882a593Smuzhiyun smps->smps = true;
1656*4882a593Smuzhiyun }
1657*4882a593Smuzhiyun
1658*4882a593Smuzhiyun static void
mt7915_mcu_wtbl_ht_tlv(struct sk_buff * skb,struct ieee80211_sta * sta,void * sta_wtbl,void * wtbl_tlv)1659*4882a593Smuzhiyun mt7915_mcu_wtbl_ht_tlv(struct sk_buff *skb, struct ieee80211_sta *sta,
1660*4882a593Smuzhiyun void *sta_wtbl, void *wtbl_tlv)
1661*4882a593Smuzhiyun {
1662*4882a593Smuzhiyun struct wtbl_ht *ht = NULL;
1663*4882a593Smuzhiyun struct tlv *tlv;
1664*4882a593Smuzhiyun
1665*4882a593Smuzhiyun /* wtbl ht */
1666*4882a593Smuzhiyun if (sta->ht_cap.ht_supported) {
1667*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_tlv(skb, WTBL_HT, sizeof(*ht),
1668*4882a593Smuzhiyun wtbl_tlv, sta_wtbl);
1669*4882a593Smuzhiyun ht = (struct wtbl_ht *)tlv;
1670*4882a593Smuzhiyun ht->ldpc = sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING;
1671*4882a593Smuzhiyun ht->af = sta->ht_cap.ampdu_factor;
1672*4882a593Smuzhiyun ht->mm = sta->ht_cap.ampdu_density;
1673*4882a593Smuzhiyun ht->ht = true;
1674*4882a593Smuzhiyun }
1675*4882a593Smuzhiyun
1676*4882a593Smuzhiyun /* wtbl vht */
1677*4882a593Smuzhiyun if (sta->vht_cap.vht_supported) {
1678*4882a593Smuzhiyun struct wtbl_vht *vht;
1679*4882a593Smuzhiyun u8 af;
1680*4882a593Smuzhiyun
1681*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_tlv(skb, WTBL_VHT, sizeof(*vht),
1682*4882a593Smuzhiyun wtbl_tlv, sta_wtbl);
1683*4882a593Smuzhiyun vht = (struct wtbl_vht *)tlv;
1684*4882a593Smuzhiyun vht->ldpc = sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC,
1685*4882a593Smuzhiyun vht->vht = true;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun af = FIELD_GET(IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK,
1688*4882a593Smuzhiyun sta->vht_cap.cap);
1689*4882a593Smuzhiyun if (ht)
1690*4882a593Smuzhiyun ht->af = max_t(u8, ht->af, af);
1691*4882a593Smuzhiyun }
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun mt7915_mcu_wtbl_smps_tlv(skb, sta, sta_wtbl, wtbl_tlv);
1694*4882a593Smuzhiyun }
1695*4882a593Smuzhiyun
mt7915_mcu_add_smps(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1696*4882a593Smuzhiyun int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,
1697*4882a593Smuzhiyun struct ieee80211_sta *sta)
1698*4882a593Smuzhiyun {
1699*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1700*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
1701*4882a593Smuzhiyun struct wtbl_req_hdr *wtbl_hdr;
1702*4882a593Smuzhiyun struct tlv *sta_wtbl;
1703*4882a593Smuzhiyun struct sk_buff *skb;
1704*4882a593Smuzhiyun
1705*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta,
1706*4882a593Smuzhiyun MT7915_STA_UPDATE_MAX_SIZE);
1707*4882a593Smuzhiyun if (IS_ERR(skb))
1708*4882a593Smuzhiyun return PTR_ERR(skb);
1709*4882a593Smuzhiyun
1710*4882a593Smuzhiyun sta_wtbl = mt7915_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv));
1711*4882a593Smuzhiyun
1712*4882a593Smuzhiyun wtbl_hdr = mt7915_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, sta_wtbl,
1713*4882a593Smuzhiyun &skb);
1714*4882a593Smuzhiyun mt7915_mcu_wtbl_smps_tlv(skb, sta, sta_wtbl, wtbl_hdr);
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
1717*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
1718*4882a593Smuzhiyun }
1719*4882a593Smuzhiyun
1720*4882a593Smuzhiyun static void
mt7915_mcu_sta_sounding_rate(struct sta_rec_bf * bf)1721*4882a593Smuzhiyun mt7915_mcu_sta_sounding_rate(struct sta_rec_bf *bf)
1722*4882a593Smuzhiyun {
1723*4882a593Smuzhiyun bf->sounding_phy = MT_PHY_TYPE_OFDM;
1724*4882a593Smuzhiyun bf->ndp_rate = 0; /* mcs0 */
1725*4882a593Smuzhiyun bf->ndpa_rate = MT7915_CFEND_RATE_DEFAULT; /* ofdm 24m */
1726*4882a593Smuzhiyun bf->rept_poll_rate = MT7915_CFEND_RATE_DEFAULT; /* ofdm 24m */
1727*4882a593Smuzhiyun }
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun static void
mt7915_mcu_sta_bfer_ht(struct ieee80211_sta * sta,struct sta_rec_bf * bf)1730*4882a593Smuzhiyun mt7915_mcu_sta_bfer_ht(struct ieee80211_sta *sta, struct sta_rec_bf *bf)
1731*4882a593Smuzhiyun {
1732*4882a593Smuzhiyun struct ieee80211_mcs_info *mcs = &sta->ht_cap.mcs;
1733*4882a593Smuzhiyun u8 n = 0;
1734*4882a593Smuzhiyun
1735*4882a593Smuzhiyun bf->tx_mode = MT_PHY_TYPE_HT;
1736*4882a593Smuzhiyun bf->bf_cap |= MT_IBF;
1737*4882a593Smuzhiyun
1738*4882a593Smuzhiyun if (mcs->tx_params & IEEE80211_HT_MCS_TX_RX_DIFF &&
1739*4882a593Smuzhiyun (mcs->tx_params & IEEE80211_HT_MCS_TX_DEFINED))
1740*4882a593Smuzhiyun n = FIELD_GET(IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK,
1741*4882a593Smuzhiyun mcs->tx_params);
1742*4882a593Smuzhiyun else if (mcs->rx_mask[3])
1743*4882a593Smuzhiyun n = 3;
1744*4882a593Smuzhiyun else if (mcs->rx_mask[2])
1745*4882a593Smuzhiyun n = 2;
1746*4882a593Smuzhiyun else if (mcs->rx_mask[1])
1747*4882a593Smuzhiyun n = 1;
1748*4882a593Smuzhiyun
1749*4882a593Smuzhiyun bf->nc = min_t(u8, bf->nr, n);
1750*4882a593Smuzhiyun bf->ibf_ncol = bf->nc;
1751*4882a593Smuzhiyun
1752*4882a593Smuzhiyun if (sta->bandwidth <= IEEE80211_STA_RX_BW_40 && !bf->nc)
1753*4882a593Smuzhiyun bf->ibf_timeout = 0x48;
1754*4882a593Smuzhiyun }
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun static void
mt7915_mcu_sta_bfer_vht(struct ieee80211_sta * sta,struct mt7915_phy * phy,struct sta_rec_bf * bf)1757*4882a593Smuzhiyun mt7915_mcu_sta_bfer_vht(struct ieee80211_sta *sta, struct mt7915_phy *phy,
1758*4882a593Smuzhiyun struct sta_rec_bf *bf)
1759*4882a593Smuzhiyun {
1760*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *pc = &sta->vht_cap;
1761*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *vc = &phy->mt76->sband_5g.sband.vht_cap;
1762*4882a593Smuzhiyun u8 bfee_nr, bfer_nr, n, tx_ant = hweight8(phy->chainmask) - 1;
1763*4882a593Smuzhiyun u16 mcs_map;
1764*4882a593Smuzhiyun
1765*4882a593Smuzhiyun bf->tx_mode = MT_PHY_TYPE_VHT;
1766*4882a593Smuzhiyun bf->bf_cap |= MT_EBF;
1767*4882a593Smuzhiyun
1768*4882a593Smuzhiyun mt7915_mcu_sta_sounding_rate(bf);
1769*4882a593Smuzhiyun
1770*4882a593Smuzhiyun bfee_nr = FIELD_GET(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK,
1771*4882a593Smuzhiyun pc->cap);
1772*4882a593Smuzhiyun bfer_nr = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
1773*4882a593Smuzhiyun vc->cap);
1774*4882a593Smuzhiyun mcs_map = le16_to_cpu(pc->vht_mcs.rx_mcs_map);
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun n = min_t(u8, bfer_nr, bfee_nr);
1777*4882a593Smuzhiyun bf->nr = min_t(u8, n, tx_ant);
1778*4882a593Smuzhiyun n = mt7915_mcu_get_sta_nss(mcs_map);
1779*4882a593Smuzhiyun
1780*4882a593Smuzhiyun bf->nc = min_t(u8, n, bf->nr);
1781*4882a593Smuzhiyun bf->ibf_ncol = bf->nc;
1782*4882a593Smuzhiyun
1783*4882a593Smuzhiyun /* force nr from 4 to 2 */
1784*4882a593Smuzhiyun if (sta->bandwidth == IEEE80211_STA_RX_BW_160)
1785*4882a593Smuzhiyun bf->nr = 1;
1786*4882a593Smuzhiyun }
1787*4882a593Smuzhiyun
1788*4882a593Smuzhiyun static void
mt7915_mcu_sta_bfer_he(struct ieee80211_sta * sta,struct ieee80211_vif * vif,struct mt7915_phy * phy,struct sta_rec_bf * bf)1789*4882a593Smuzhiyun mt7915_mcu_sta_bfer_he(struct ieee80211_sta *sta, struct ieee80211_vif *vif,
1790*4882a593Smuzhiyun struct mt7915_phy *phy, struct sta_rec_bf *bf)
1791*4882a593Smuzhiyun {
1792*4882a593Smuzhiyun struct ieee80211_sta_he_cap *pc = &sta->he_cap;
1793*4882a593Smuzhiyun struct ieee80211_he_cap_elem *pe = &pc->he_cap_elem;
1794*4882a593Smuzhiyun const struct ieee80211_he_cap_elem *ve;
1795*4882a593Smuzhiyun const struct ieee80211_sta_he_cap *vc;
1796*4882a593Smuzhiyun u8 bfee_nr, bfer_nr, nss_mcs;
1797*4882a593Smuzhiyun u16 mcs_map;
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun vc = mt7915_get_he_phy_cap(phy, vif);
1800*4882a593Smuzhiyun ve = &vc->he_cap_elem;
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun bf->tx_mode = MT_PHY_TYPE_HE_SU;
1803*4882a593Smuzhiyun bf->bf_cap |= MT_EBF;
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun mt7915_mcu_sta_sounding_rate(bf);
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun bf->trigger_su = HE_PHY(CAP6_TRIG_SU_BEAMFORMER_FB,
1808*4882a593Smuzhiyun pe->phy_cap_info[6]);
1809*4882a593Smuzhiyun bf->trigger_mu = HE_PHY(CAP6_TRIG_MU_BEAMFORMER_FB,
1810*4882a593Smuzhiyun pe->phy_cap_info[6]);
1811*4882a593Smuzhiyun bfer_nr = HE_PHY(CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1812*4882a593Smuzhiyun ve->phy_cap_info[5]);
1813*4882a593Smuzhiyun bfee_nr = HE_PHY(CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_MASK,
1814*4882a593Smuzhiyun pe->phy_cap_info[4]);
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun mcs_map = le16_to_cpu(pc->he_mcs_nss_supp.tx_mcs_80);
1817*4882a593Smuzhiyun nss_mcs = mt7915_mcu_get_sta_nss(mcs_map);
1818*4882a593Smuzhiyun
1819*4882a593Smuzhiyun bf->nr = min_t(u8, bfer_nr, bfee_nr);
1820*4882a593Smuzhiyun bf->nc = min_t(u8, nss_mcs, bf->nr);
1821*4882a593Smuzhiyun bf->ibf_ncol = bf->nc;
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun if (sta->bandwidth != IEEE80211_STA_RX_BW_160)
1824*4882a593Smuzhiyun return;
1825*4882a593Smuzhiyun
1826*4882a593Smuzhiyun /* go over for 160MHz and 80p80 */
1827*4882a593Smuzhiyun if (pe->phy_cap_info[0] &
1828*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) {
1829*4882a593Smuzhiyun mcs_map = le16_to_cpu(pc->he_mcs_nss_supp.rx_mcs_160);
1830*4882a593Smuzhiyun nss_mcs = mt7915_mcu_get_sta_nss(mcs_map);
1831*4882a593Smuzhiyun
1832*4882a593Smuzhiyun bf->nc_bw160 = nss_mcs;
1833*4882a593Smuzhiyun }
1834*4882a593Smuzhiyun
1835*4882a593Smuzhiyun if (pe->phy_cap_info[0] &
1836*4882a593Smuzhiyun IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) {
1837*4882a593Smuzhiyun mcs_map = le16_to_cpu(pc->he_mcs_nss_supp.rx_mcs_80p80);
1838*4882a593Smuzhiyun nss_mcs = mt7915_mcu_get_sta_nss(mcs_map);
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun if (bf->nc_bw160)
1841*4882a593Smuzhiyun bf->nc_bw160 = min_t(u8, bf->nc_bw160, nss_mcs);
1842*4882a593Smuzhiyun else
1843*4882a593Smuzhiyun bf->nc_bw160 = nss_mcs;
1844*4882a593Smuzhiyun }
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun bfer_nr = HE_PHY(CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1847*4882a593Smuzhiyun ve->phy_cap_info[5]);
1848*4882a593Smuzhiyun bfee_nr = HE_PHY(CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_MASK,
1849*4882a593Smuzhiyun pe->phy_cap_info[4]);
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun bf->nr_bw160 = min_t(int, bfer_nr, bfee_nr);
1852*4882a593Smuzhiyun }
1853*4882a593Smuzhiyun
1854*4882a593Smuzhiyun static void
mt7915_mcu_sta_bfer_tlv(struct sk_buff * skb,struct ieee80211_sta * sta,struct ieee80211_vif * vif,struct mt7915_phy * phy,bool enable)1855*4882a593Smuzhiyun mt7915_mcu_sta_bfer_tlv(struct sk_buff *skb, struct ieee80211_sta *sta,
1856*4882a593Smuzhiyun struct ieee80211_vif *vif, struct mt7915_phy *phy,
1857*4882a593Smuzhiyun bool enable)
1858*4882a593Smuzhiyun {
1859*4882a593Smuzhiyun struct sta_rec_bf *bf;
1860*4882a593Smuzhiyun struct tlv *tlv;
1861*4882a593Smuzhiyun int tx_ant = hweight8(phy->chainmask) - 1;
1862*4882a593Smuzhiyun const u8 matrix[4][4] = {
1863*4882a593Smuzhiyun {0, 0, 0, 0},
1864*4882a593Smuzhiyun {1, 1, 0, 0}, /* 2x1, 2x2, 2x3, 2x4 */
1865*4882a593Smuzhiyun {2, 4, 4, 0}, /* 3x1, 3x2, 3x3, 3x4 */
1866*4882a593Smuzhiyun {3, 5, 6, 0} /* 4x1, 4x2, 4x3, 4x4 */
1867*4882a593Smuzhiyun };
1868*4882a593Smuzhiyun
1869*4882a593Smuzhiyun #define MT_BFER_FREE cpu_to_le16(GENMASK(15, 0))
1870*4882a593Smuzhiyun
1871*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_BF, sizeof(*bf));
1872*4882a593Smuzhiyun bf = (struct sta_rec_bf *)tlv;
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun if (!enable) {
1875*4882a593Smuzhiyun bf->pfmu = MT_BFER_FREE;
1876*4882a593Smuzhiyun return;
1877*4882a593Smuzhiyun }
1878*4882a593Smuzhiyun
1879*4882a593Smuzhiyun bf->bw = sta->bandwidth;
1880*4882a593Smuzhiyun bf->ibf_dbw = sta->bandwidth;
1881*4882a593Smuzhiyun bf->ibf_nrow = tx_ant;
1882*4882a593Smuzhiyun bf->ibf_timeout = 0x18;
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun if (sta->he_cap.has_he)
1885*4882a593Smuzhiyun mt7915_mcu_sta_bfer_he(sta, vif, phy, bf);
1886*4882a593Smuzhiyun else if (sta->vht_cap.vht_supported)
1887*4882a593Smuzhiyun mt7915_mcu_sta_bfer_vht(sta, phy, bf);
1888*4882a593Smuzhiyun else if (sta->ht_cap.ht_supported)
1889*4882a593Smuzhiyun mt7915_mcu_sta_bfer_ht(sta, bf);
1890*4882a593Smuzhiyun
1891*4882a593Smuzhiyun if (bf->bf_cap & MT_EBF && bf->nr != tx_ant)
1892*4882a593Smuzhiyun bf->mem_20m = matrix[tx_ant][bf->nc];
1893*4882a593Smuzhiyun else
1894*4882a593Smuzhiyun bf->mem_20m = matrix[bf->nr][bf->nc];
1895*4882a593Smuzhiyun
1896*4882a593Smuzhiyun switch (sta->bandwidth) {
1897*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_160:
1898*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_80:
1899*4882a593Smuzhiyun bf->mem_total = bf->mem_20m * 2;
1900*4882a593Smuzhiyun break;
1901*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_40:
1902*4882a593Smuzhiyun bf->mem_total = bf->mem_20m;
1903*4882a593Smuzhiyun break;
1904*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_20:
1905*4882a593Smuzhiyun default:
1906*4882a593Smuzhiyun break;
1907*4882a593Smuzhiyun }
1908*4882a593Smuzhiyun }
1909*4882a593Smuzhiyun
1910*4882a593Smuzhiyun static void
mt7915_mcu_sta_bfee_tlv(struct sk_buff * skb,struct ieee80211_sta * sta,struct mt7915_phy * phy)1911*4882a593Smuzhiyun mt7915_mcu_sta_bfee_tlv(struct sk_buff *skb, struct ieee80211_sta *sta,
1912*4882a593Smuzhiyun struct mt7915_phy *phy)
1913*4882a593Smuzhiyun {
1914*4882a593Smuzhiyun struct sta_rec_bfee *bfee;
1915*4882a593Smuzhiyun struct tlv *tlv;
1916*4882a593Smuzhiyun int tx_ant = hweight8(phy->chainmask) - 1;
1917*4882a593Smuzhiyun u8 nr = 0;
1918*4882a593Smuzhiyun
1919*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_BFEE, sizeof(*bfee));
1920*4882a593Smuzhiyun bfee = (struct sta_rec_bfee *)tlv;
1921*4882a593Smuzhiyun
1922*4882a593Smuzhiyun if (sta->he_cap.has_he) {
1923*4882a593Smuzhiyun struct ieee80211_he_cap_elem *pe = &sta->he_cap.he_cap_elem;
1924*4882a593Smuzhiyun
1925*4882a593Smuzhiyun nr = HE_PHY(CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1926*4882a593Smuzhiyun pe->phy_cap_info[5]);
1927*4882a593Smuzhiyun } else if (sta->vht_cap.vht_supported) {
1928*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *pc = &sta->vht_cap;
1929*4882a593Smuzhiyun
1930*4882a593Smuzhiyun nr = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
1931*4882a593Smuzhiyun pc->cap);
1932*4882a593Smuzhiyun }
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun /* reply with identity matrix to avoid 2x2 BF negative gain */
1935*4882a593Smuzhiyun if (nr == 1 && tx_ant == 2)
1936*4882a593Smuzhiyun bfee->fb_identity_matrix = true;
1937*4882a593Smuzhiyun }
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun static u8
mt7915_mcu_sta_txbf_type(struct mt7915_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1940*4882a593Smuzhiyun mt7915_mcu_sta_txbf_type(struct mt7915_phy *phy, struct ieee80211_vif *vif,
1941*4882a593Smuzhiyun struct ieee80211_sta *sta)
1942*4882a593Smuzhiyun {
1943*4882a593Smuzhiyun u8 type = 0;
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun if (vif->type != NL80211_IFTYPE_STATION &&
1946*4882a593Smuzhiyun vif->type != NL80211_IFTYPE_AP)
1947*4882a593Smuzhiyun return 0;
1948*4882a593Smuzhiyun
1949*4882a593Smuzhiyun if (sta->he_cap.has_he) {
1950*4882a593Smuzhiyun struct ieee80211_he_cap_elem *pe;
1951*4882a593Smuzhiyun const struct ieee80211_he_cap_elem *ve;
1952*4882a593Smuzhiyun const struct ieee80211_sta_he_cap *vc;
1953*4882a593Smuzhiyun
1954*4882a593Smuzhiyun pe = &sta->he_cap.he_cap_elem;
1955*4882a593Smuzhiyun vc = mt7915_get_he_phy_cap(phy, vif);
1956*4882a593Smuzhiyun ve = &vc->he_cap_elem;
1957*4882a593Smuzhiyun
1958*4882a593Smuzhiyun if ((HE_PHY(CAP3_SU_BEAMFORMER, pe->phy_cap_info[3]) ||
1959*4882a593Smuzhiyun HE_PHY(CAP4_MU_BEAMFORMER, pe->phy_cap_info[4])) &&
1960*4882a593Smuzhiyun HE_PHY(CAP4_SU_BEAMFORMEE, ve->phy_cap_info[4]))
1961*4882a593Smuzhiyun type |= MT_STA_BFEE;
1962*4882a593Smuzhiyun
1963*4882a593Smuzhiyun if ((HE_PHY(CAP3_SU_BEAMFORMER, ve->phy_cap_info[3]) ||
1964*4882a593Smuzhiyun HE_PHY(CAP4_MU_BEAMFORMER, ve->phy_cap_info[4])) &&
1965*4882a593Smuzhiyun HE_PHY(CAP4_SU_BEAMFORMEE, pe->phy_cap_info[4]))
1966*4882a593Smuzhiyun type |= MT_STA_BFER;
1967*4882a593Smuzhiyun } else if (sta->vht_cap.vht_supported) {
1968*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *pc;
1969*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *vc;
1970*4882a593Smuzhiyun u32 cr, ce;
1971*4882a593Smuzhiyun
1972*4882a593Smuzhiyun pc = &sta->vht_cap;
1973*4882a593Smuzhiyun vc = &phy->mt76->sband_5g.sband.vht_cap;
1974*4882a593Smuzhiyun cr = IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1975*4882a593Smuzhiyun IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE;
1976*4882a593Smuzhiyun ce = IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
1977*4882a593Smuzhiyun IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
1978*4882a593Smuzhiyun
1979*4882a593Smuzhiyun if ((pc->cap & cr) && (vc->cap & ce))
1980*4882a593Smuzhiyun type |= MT_STA_BFEE;
1981*4882a593Smuzhiyun
1982*4882a593Smuzhiyun if ((vc->cap & cr) && (pc->cap & ce))
1983*4882a593Smuzhiyun type |= MT_STA_BFER;
1984*4882a593Smuzhiyun } else if (sta->ht_cap.ht_supported) {
1985*4882a593Smuzhiyun /* TODO: iBF */
1986*4882a593Smuzhiyun }
1987*4882a593Smuzhiyun
1988*4882a593Smuzhiyun return type;
1989*4882a593Smuzhiyun }
1990*4882a593Smuzhiyun
1991*4882a593Smuzhiyun static int
mt7915_mcu_add_txbf(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1992*4882a593Smuzhiyun mt7915_mcu_add_txbf(struct mt7915_dev *dev, struct ieee80211_vif *vif,
1993*4882a593Smuzhiyun struct ieee80211_sta *sta, bool enable)
1994*4882a593Smuzhiyun {
1995*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1996*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
1997*4882a593Smuzhiyun struct mt7915_phy *phy;
1998*4882a593Smuzhiyun struct sk_buff *skb;
1999*4882a593Smuzhiyun int r, len;
2000*4882a593Smuzhiyun u8 type;
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun phy = mvif->band_idx ? mt7915_ext_phy(dev) : &dev->phy;
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun type = mt7915_mcu_sta_txbf_type(phy, vif, sta);
2005*4882a593Smuzhiyun
2006*4882a593Smuzhiyun /* must keep each tag independent */
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun /* starec bf */
2009*4882a593Smuzhiyun if (type & MT_STA_BFER) {
2010*4882a593Smuzhiyun len = sizeof(struct sta_req_hdr) + sizeof(struct sta_rec_bf);
2011*4882a593Smuzhiyun
2012*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta, len);
2013*4882a593Smuzhiyun if (IS_ERR(skb))
2014*4882a593Smuzhiyun return PTR_ERR(skb);
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun mt7915_mcu_sta_bfer_tlv(skb, sta, vif, phy, enable);
2017*4882a593Smuzhiyun
2018*4882a593Smuzhiyun r = __mt76_mcu_skb_send_msg(&dev->mt76, skb,
2019*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
2020*4882a593Smuzhiyun if (r)
2021*4882a593Smuzhiyun return r;
2022*4882a593Smuzhiyun }
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun /* starec bfee */
2025*4882a593Smuzhiyun if (type & MT_STA_BFEE) {
2026*4882a593Smuzhiyun len = sizeof(struct sta_req_hdr) + sizeof(struct sta_rec_bfee);
2027*4882a593Smuzhiyun
2028*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta, len);
2029*4882a593Smuzhiyun if (IS_ERR(skb))
2030*4882a593Smuzhiyun return PTR_ERR(skb);
2031*4882a593Smuzhiyun
2032*4882a593Smuzhiyun mt7915_mcu_sta_bfee_tlv(skb, sta, phy);
2033*4882a593Smuzhiyun
2034*4882a593Smuzhiyun r = __mt76_mcu_skb_send_msg(&dev->mt76, skb,
2035*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
2036*4882a593Smuzhiyun if (r)
2037*4882a593Smuzhiyun return r;
2038*4882a593Smuzhiyun }
2039*4882a593Smuzhiyun
2040*4882a593Smuzhiyun return 0;
2041*4882a593Smuzhiyun }
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun static void
mt7915_mcu_sta_rate_ctrl_tlv(struct sk_buff * skb,struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2044*4882a593Smuzhiyun mt7915_mcu_sta_rate_ctrl_tlv(struct sk_buff *skb, struct mt7915_dev *dev,
2045*4882a593Smuzhiyun struct ieee80211_vif *vif,
2046*4882a593Smuzhiyun struct ieee80211_sta *sta)
2047*4882a593Smuzhiyun {
2048*4882a593Smuzhiyun struct cfg80211_chan_def *chandef = &dev->mphy.chandef;
2049*4882a593Smuzhiyun struct sta_rec_ra *ra;
2050*4882a593Smuzhiyun struct tlv *tlv;
2051*4882a593Smuzhiyun enum nl80211_band band = chandef->chan->band;
2052*4882a593Smuzhiyun u32 supp_rate = sta->supp_rates[band];
2053*4882a593Smuzhiyun int n_rates = hweight32(supp_rate);
2054*4882a593Smuzhiyun u32 cap = sta->wme ? STA_CAP_WMM : 0;
2055*4882a593Smuzhiyun u8 i, nss = sta->rx_nss, mcs = 0;
2056*4882a593Smuzhiyun
2057*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_RA, sizeof(*ra));
2058*4882a593Smuzhiyun
2059*4882a593Smuzhiyun ra = (struct sta_rec_ra *)tlv;
2060*4882a593Smuzhiyun ra->valid = true;
2061*4882a593Smuzhiyun ra->auto_rate = true;
2062*4882a593Smuzhiyun ra->phy_mode = mt7915_get_phy_mode(dev, vif, band, sta);
2063*4882a593Smuzhiyun ra->channel = chandef->chan->hw_value;
2064*4882a593Smuzhiyun ra->bw = sta->bandwidth;
2065*4882a593Smuzhiyun ra->rate_len = n_rates;
2066*4882a593Smuzhiyun ra->phy.bw = sta->bandwidth;
2067*4882a593Smuzhiyun
2068*4882a593Smuzhiyun if (n_rates) {
2069*4882a593Smuzhiyun if (band == NL80211_BAND_2GHZ) {
2070*4882a593Smuzhiyun ra->supp_mode = MODE_CCK;
2071*4882a593Smuzhiyun ra->supp_cck_rate = supp_rate & GENMASK(3, 0);
2072*4882a593Smuzhiyun ra->phy.type = MT_PHY_TYPE_CCK;
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun if (n_rates > 4) {
2075*4882a593Smuzhiyun ra->supp_mode |= MODE_OFDM;
2076*4882a593Smuzhiyun ra->supp_ofdm_rate = supp_rate >> 4;
2077*4882a593Smuzhiyun ra->phy.type = MT_PHY_TYPE_OFDM;
2078*4882a593Smuzhiyun }
2079*4882a593Smuzhiyun } else {
2080*4882a593Smuzhiyun ra->supp_mode = MODE_OFDM;
2081*4882a593Smuzhiyun ra->supp_ofdm_rate = supp_rate;
2082*4882a593Smuzhiyun ra->phy.type = MT_PHY_TYPE_OFDM;
2083*4882a593Smuzhiyun }
2084*4882a593Smuzhiyun }
2085*4882a593Smuzhiyun
2086*4882a593Smuzhiyun if (sta->ht_cap.ht_supported) {
2087*4882a593Smuzhiyun for (i = 0; i < nss; i++)
2088*4882a593Smuzhiyun ra->ht_mcs[i] = sta->ht_cap.mcs.rx_mask[i];
2089*4882a593Smuzhiyun
2090*4882a593Smuzhiyun ra->supp_ht_mcs = *(__le32 *)ra->ht_mcs;
2091*4882a593Smuzhiyun ra->supp_mode |= MODE_HT;
2092*4882a593Smuzhiyun mcs = hweight32(le32_to_cpu(ra->supp_ht_mcs)) - 1;
2093*4882a593Smuzhiyun ra->af = sta->ht_cap.ampdu_factor;
2094*4882a593Smuzhiyun ra->ht_gf = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD);
2095*4882a593Smuzhiyun
2096*4882a593Smuzhiyun cap |= STA_CAP_HT;
2097*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
2098*4882a593Smuzhiyun cap |= STA_CAP_SGI_20;
2099*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
2100*4882a593Smuzhiyun cap |= STA_CAP_SGI_40;
2101*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_TX_STBC)
2102*4882a593Smuzhiyun cap |= STA_CAP_TX_STBC;
2103*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
2104*4882a593Smuzhiyun cap |= STA_CAP_RX_STBC;
2105*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
2106*4882a593Smuzhiyun cap |= STA_CAP_LDPC;
2107*4882a593Smuzhiyun }
2108*4882a593Smuzhiyun
2109*4882a593Smuzhiyun if (sta->vht_cap.vht_supported) {
2110*4882a593Smuzhiyun u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
2111*4882a593Smuzhiyun u16 vht_mcs;
2112*4882a593Smuzhiyun u8 af, mcs_prev;
2113*4882a593Smuzhiyun
2114*4882a593Smuzhiyun af = FIELD_GET(IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK,
2115*4882a593Smuzhiyun sta->vht_cap.cap);
2116*4882a593Smuzhiyun ra->af = max_t(u8, ra->af, af);
2117*4882a593Smuzhiyun
2118*4882a593Smuzhiyun cap |= STA_CAP_VHT;
2119*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80)
2120*4882a593Smuzhiyun cap |= STA_CAP_VHT_SGI_80;
2121*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160)
2122*4882a593Smuzhiyun cap |= STA_CAP_VHT_SGI_160;
2123*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_TXSTBC)
2124*4882a593Smuzhiyun cap |= STA_CAP_VHT_TX_STBC;
2125*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_1)
2126*4882a593Smuzhiyun cap |= STA_CAP_VHT_RX_STBC;
2127*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
2128*4882a593Smuzhiyun cap |= STA_CAP_VHT_LDPC;
2129*4882a593Smuzhiyun
2130*4882a593Smuzhiyun ra->supp_mode |= MODE_VHT;
2131*4882a593Smuzhiyun for (mcs = 0, i = 0; i < nss; i++, mcs_map >>= 2) {
2132*4882a593Smuzhiyun switch (mcs_map & 0x3) {
2133*4882a593Smuzhiyun case IEEE80211_VHT_MCS_SUPPORT_0_9:
2134*4882a593Smuzhiyun vht_mcs = GENMASK(9, 0);
2135*4882a593Smuzhiyun break;
2136*4882a593Smuzhiyun case IEEE80211_VHT_MCS_SUPPORT_0_8:
2137*4882a593Smuzhiyun vht_mcs = GENMASK(8, 0);
2138*4882a593Smuzhiyun break;
2139*4882a593Smuzhiyun case IEEE80211_VHT_MCS_SUPPORT_0_7:
2140*4882a593Smuzhiyun vht_mcs = GENMASK(7, 0);
2141*4882a593Smuzhiyun break;
2142*4882a593Smuzhiyun default:
2143*4882a593Smuzhiyun vht_mcs = 0;
2144*4882a593Smuzhiyun }
2145*4882a593Smuzhiyun
2146*4882a593Smuzhiyun ra->supp_vht_mcs[i] = cpu_to_le16(vht_mcs);
2147*4882a593Smuzhiyun
2148*4882a593Smuzhiyun mcs_prev = hweight16(vht_mcs) - 1;
2149*4882a593Smuzhiyun if (mcs_prev > mcs)
2150*4882a593Smuzhiyun mcs = mcs_prev;
2151*4882a593Smuzhiyun
2152*4882a593Smuzhiyun /* only support 2ss on 160MHz */
2153*4882a593Smuzhiyun if (i > 1 && (ra->bw == CMD_CBW_160MHZ ||
2154*4882a593Smuzhiyun ra->bw == CMD_CBW_8080MHZ))
2155*4882a593Smuzhiyun break;
2156*4882a593Smuzhiyun }
2157*4882a593Smuzhiyun }
2158*4882a593Smuzhiyun
2159*4882a593Smuzhiyun if (sta->he_cap.has_he) {
2160*4882a593Smuzhiyun ra->supp_mode |= MODE_HE;
2161*4882a593Smuzhiyun cap |= STA_CAP_HE;
2162*4882a593Smuzhiyun }
2163*4882a593Smuzhiyun
2164*4882a593Smuzhiyun ra->sta_status = cpu_to_le32(cap);
2165*4882a593Smuzhiyun
2166*4882a593Smuzhiyun switch (BIT(fls(ra->supp_mode) - 1)) {
2167*4882a593Smuzhiyun case MODE_VHT:
2168*4882a593Smuzhiyun ra->phy.type = MT_PHY_TYPE_VHT;
2169*4882a593Smuzhiyun ra->phy.mcs = mcs;
2170*4882a593Smuzhiyun ra->phy.nss = nss;
2171*4882a593Smuzhiyun ra->phy.stbc = !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_TXSTBC);
2172*4882a593Smuzhiyun ra->phy.ldpc = !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
2173*4882a593Smuzhiyun ra->phy.sgi =
2174*4882a593Smuzhiyun !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
2175*4882a593Smuzhiyun break;
2176*4882a593Smuzhiyun case MODE_HT:
2177*4882a593Smuzhiyun ra->phy.type = MT_PHY_TYPE_HT;
2178*4882a593Smuzhiyun ra->phy.mcs = mcs;
2179*4882a593Smuzhiyun ra->phy.ldpc = sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING;
2180*4882a593Smuzhiyun ra->phy.stbc = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_TX_STBC);
2181*4882a593Smuzhiyun ra->phy.sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
2182*4882a593Smuzhiyun break;
2183*4882a593Smuzhiyun default:
2184*4882a593Smuzhiyun break;
2185*4882a593Smuzhiyun }
2186*4882a593Smuzhiyun }
2187*4882a593Smuzhiyun
mt7915_mcu_add_rate_ctrl(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2188*4882a593Smuzhiyun int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,
2189*4882a593Smuzhiyun struct ieee80211_sta *sta)
2190*4882a593Smuzhiyun {
2191*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
2192*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
2193*4882a593Smuzhiyun struct sk_buff *skb;
2194*4882a593Smuzhiyun int len = sizeof(struct sta_req_hdr) + sizeof(struct sta_rec_ra);
2195*4882a593Smuzhiyun
2196*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta, len);
2197*4882a593Smuzhiyun if (IS_ERR(skb))
2198*4882a593Smuzhiyun return PTR_ERR(skb);
2199*4882a593Smuzhiyun
2200*4882a593Smuzhiyun mt7915_mcu_sta_rate_ctrl_tlv(skb, dev, vif, sta);
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
2203*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
2204*4882a593Smuzhiyun }
2205*4882a593Smuzhiyun
2206*4882a593Smuzhiyun static int
mt7915_mcu_add_group(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2207*4882a593Smuzhiyun mt7915_mcu_add_group(struct mt7915_dev *dev, struct ieee80211_vif *vif,
2208*4882a593Smuzhiyun struct ieee80211_sta *sta)
2209*4882a593Smuzhiyun {
2210*4882a593Smuzhiyun #define MT_STA_BSS_GROUP 1
2211*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
2212*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
2213*4882a593Smuzhiyun struct {
2214*4882a593Smuzhiyun __le32 action;
2215*4882a593Smuzhiyun u8 wlan_idx_lo;
2216*4882a593Smuzhiyun u8 status;
2217*4882a593Smuzhiyun u8 wlan_idx_hi;
2218*4882a593Smuzhiyun u8 rsv0[5];
2219*4882a593Smuzhiyun __le32 val;
2220*4882a593Smuzhiyun u8 rsv1[8];
2221*4882a593Smuzhiyun } __packed req = {
2222*4882a593Smuzhiyun .action = cpu_to_le32(MT_STA_BSS_GROUP),
2223*4882a593Smuzhiyun .wlan_idx_lo = to_wcid_lo(msta->wcid.idx),
2224*4882a593Smuzhiyun .wlan_idx_hi = to_wcid_hi(msta->wcid.idx),
2225*4882a593Smuzhiyun .val = cpu_to_le32(mvif->idx),
2226*4882a593Smuzhiyun };
2227*4882a593Smuzhiyun
2228*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_DRR_CTRL,
2229*4882a593Smuzhiyun &req, sizeof(req), true);
2230*4882a593Smuzhiyun }
2231*4882a593Smuzhiyun
mt7915_mcu_add_sta_adv(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)2232*4882a593Smuzhiyun int mt7915_mcu_add_sta_adv(struct mt7915_dev *dev, struct ieee80211_vif *vif,
2233*4882a593Smuzhiyun struct ieee80211_sta *sta, bool enable)
2234*4882a593Smuzhiyun {
2235*4882a593Smuzhiyun int ret;
2236*4882a593Smuzhiyun
2237*4882a593Smuzhiyun if (!sta)
2238*4882a593Smuzhiyun return 0;
2239*4882a593Smuzhiyun
2240*4882a593Smuzhiyun /* must keep the order */
2241*4882a593Smuzhiyun ret = mt7915_mcu_add_group(dev, vif, sta);
2242*4882a593Smuzhiyun if (ret)
2243*4882a593Smuzhiyun return ret;
2244*4882a593Smuzhiyun
2245*4882a593Smuzhiyun ret = mt7915_mcu_add_txbf(dev, vif, sta, enable);
2246*4882a593Smuzhiyun if (ret)
2247*4882a593Smuzhiyun return ret;
2248*4882a593Smuzhiyun
2249*4882a593Smuzhiyun ret = mt7915_mcu_add_mu(dev, vif, sta);
2250*4882a593Smuzhiyun if (ret)
2251*4882a593Smuzhiyun return ret;
2252*4882a593Smuzhiyun
2253*4882a593Smuzhiyun if (enable)
2254*4882a593Smuzhiyun return mt7915_mcu_add_rate_ctrl(dev, vif, sta);
2255*4882a593Smuzhiyun
2256*4882a593Smuzhiyun return 0;
2257*4882a593Smuzhiyun }
2258*4882a593Smuzhiyun
mt7915_mcu_add_sta(struct mt7915_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)2259*4882a593Smuzhiyun int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
2260*4882a593Smuzhiyun struct ieee80211_sta *sta, bool enable)
2261*4882a593Smuzhiyun {
2262*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
2263*4882a593Smuzhiyun struct wtbl_req_hdr *wtbl_hdr;
2264*4882a593Smuzhiyun struct mt7915_sta *msta;
2265*4882a593Smuzhiyun struct tlv *sta_wtbl;
2266*4882a593Smuzhiyun struct sk_buff *skb;
2267*4882a593Smuzhiyun
2268*4882a593Smuzhiyun msta = sta ? (struct mt7915_sta *)sta->drv_priv : &mvif->sta;
2269*4882a593Smuzhiyun
2270*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta,
2271*4882a593Smuzhiyun MT7915_STA_UPDATE_MAX_SIZE);
2272*4882a593Smuzhiyun if (IS_ERR(skb))
2273*4882a593Smuzhiyun return PTR_ERR(skb);
2274*4882a593Smuzhiyun
2275*4882a593Smuzhiyun mt7915_mcu_sta_basic_tlv(skb, vif, sta, enable);
2276*4882a593Smuzhiyun if (enable && sta)
2277*4882a593Smuzhiyun mt7915_mcu_sta_tlv(dev, skb, sta, vif);
2278*4882a593Smuzhiyun
2279*4882a593Smuzhiyun sta_wtbl = mt7915_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv));
2280*4882a593Smuzhiyun
2281*4882a593Smuzhiyun wtbl_hdr = mt7915_mcu_alloc_wtbl_req(dev, msta, WTBL_RESET_AND_SET,
2282*4882a593Smuzhiyun sta_wtbl, &skb);
2283*4882a593Smuzhiyun if (enable) {
2284*4882a593Smuzhiyun mt7915_mcu_wtbl_generic_tlv(skb, vif, sta, sta_wtbl, wtbl_hdr);
2285*4882a593Smuzhiyun if (sta)
2286*4882a593Smuzhiyun mt7915_mcu_wtbl_ht_tlv(skb, sta, sta_wtbl, wtbl_hdr);
2287*4882a593Smuzhiyun }
2288*4882a593Smuzhiyun
2289*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
2290*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
2291*4882a593Smuzhiyun }
2292*4882a593Smuzhiyun
mt7915_mcu_set_fixed_rate(struct mt7915_dev * dev,struct ieee80211_sta * sta,u32 rate)2293*4882a593Smuzhiyun int mt7915_mcu_set_fixed_rate(struct mt7915_dev *dev,
2294*4882a593Smuzhiyun struct ieee80211_sta *sta, u32 rate)
2295*4882a593Smuzhiyun {
2296*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
2297*4882a593Smuzhiyun struct mt7915_vif *mvif = msta->vif;
2298*4882a593Smuzhiyun struct sta_rec_ra_fixed *ra;
2299*4882a593Smuzhiyun struct sk_buff *skb;
2300*4882a593Smuzhiyun struct tlv *tlv;
2301*4882a593Smuzhiyun int len = sizeof(struct sta_req_hdr) + sizeof(*ra);
2302*4882a593Smuzhiyun
2303*4882a593Smuzhiyun skb = mt7915_mcu_alloc_sta_req(dev, mvif, msta, len);
2304*4882a593Smuzhiyun if (IS_ERR(skb))
2305*4882a593Smuzhiyun return PTR_ERR(skb);
2306*4882a593Smuzhiyun
2307*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(skb, STA_REC_RA_UPDATE, sizeof(*ra));
2308*4882a593Smuzhiyun ra = (struct sta_rec_ra_fixed *)tlv;
2309*4882a593Smuzhiyun
2310*4882a593Smuzhiyun if (!rate) {
2311*4882a593Smuzhiyun ra->field = cpu_to_le32(RATE_PARAM_AUTO);
2312*4882a593Smuzhiyun goto out;
2313*4882a593Smuzhiyun } else {
2314*4882a593Smuzhiyun ra->field = cpu_to_le32(RATE_PARAM_FIXED);
2315*4882a593Smuzhiyun }
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun ra->phy.type = FIELD_GET(RATE_CFG_PHY_TYPE, rate);
2318*4882a593Smuzhiyun ra->phy.bw = FIELD_GET(RATE_CFG_BW, rate);
2319*4882a593Smuzhiyun ra->phy.nss = FIELD_GET(RATE_CFG_NSS, rate);
2320*4882a593Smuzhiyun ra->phy.mcs = FIELD_GET(RATE_CFG_MCS, rate);
2321*4882a593Smuzhiyun ra->phy.stbc = FIELD_GET(RATE_CFG_STBC, rate);
2322*4882a593Smuzhiyun
2323*4882a593Smuzhiyun if (ra->phy.bw)
2324*4882a593Smuzhiyun ra->phy.ldpc = 7;
2325*4882a593Smuzhiyun else
2326*4882a593Smuzhiyun ra->phy.ldpc = FIELD_GET(RATE_CFG_LDPC, rate) * 7;
2327*4882a593Smuzhiyun
2328*4882a593Smuzhiyun /* HT/VHT - SGI: 1, LGI: 0; HE - SGI: 0, MGI: 1, LGI: 2 */
2329*4882a593Smuzhiyun if (ra->phy.type > MT_PHY_TYPE_VHT)
2330*4882a593Smuzhiyun ra->phy.sgi = ra->phy.mcs * 85;
2331*4882a593Smuzhiyun else
2332*4882a593Smuzhiyun ra->phy.sgi = ra->phy.mcs * 15;
2333*4882a593Smuzhiyun
2334*4882a593Smuzhiyun out:
2335*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
2336*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE, true);
2337*4882a593Smuzhiyun }
2338*4882a593Smuzhiyun
mt7915_mcu_add_dev_info(struct mt7915_dev * dev,struct ieee80211_vif * vif,bool enable)2339*4882a593Smuzhiyun int mt7915_mcu_add_dev_info(struct mt7915_dev *dev,
2340*4882a593Smuzhiyun struct ieee80211_vif *vif, bool enable)
2341*4882a593Smuzhiyun {
2342*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
2343*4882a593Smuzhiyun struct {
2344*4882a593Smuzhiyun struct req_hdr {
2345*4882a593Smuzhiyun u8 omac_idx;
2346*4882a593Smuzhiyun u8 dbdc_idx;
2347*4882a593Smuzhiyun __le16 tlv_num;
2348*4882a593Smuzhiyun u8 is_tlv_append;
2349*4882a593Smuzhiyun u8 rsv[3];
2350*4882a593Smuzhiyun } __packed hdr;
2351*4882a593Smuzhiyun struct req_tlv {
2352*4882a593Smuzhiyun __le16 tag;
2353*4882a593Smuzhiyun __le16 len;
2354*4882a593Smuzhiyun u8 active;
2355*4882a593Smuzhiyun u8 dbdc_idx;
2356*4882a593Smuzhiyun u8 omac_addr[ETH_ALEN];
2357*4882a593Smuzhiyun } __packed tlv;
2358*4882a593Smuzhiyun } data = {
2359*4882a593Smuzhiyun .hdr = {
2360*4882a593Smuzhiyun .omac_idx = mvif->omac_idx,
2361*4882a593Smuzhiyun .dbdc_idx = mvif->band_idx,
2362*4882a593Smuzhiyun .tlv_num = cpu_to_le16(1),
2363*4882a593Smuzhiyun .is_tlv_append = 1,
2364*4882a593Smuzhiyun },
2365*4882a593Smuzhiyun .tlv = {
2366*4882a593Smuzhiyun .tag = cpu_to_le16(DEV_INFO_ACTIVE),
2367*4882a593Smuzhiyun .len = cpu_to_le16(sizeof(struct req_tlv)),
2368*4882a593Smuzhiyun .active = enable,
2369*4882a593Smuzhiyun .dbdc_idx = mvif->band_idx,
2370*4882a593Smuzhiyun },
2371*4882a593Smuzhiyun };
2372*4882a593Smuzhiyun
2373*4882a593Smuzhiyun memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN);
2374*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DEV_INFO_UPDATE,
2375*4882a593Smuzhiyun &data, sizeof(data), true);
2376*4882a593Smuzhiyun }
2377*4882a593Smuzhiyun
2378*4882a593Smuzhiyun static void
mt7915_mcu_beacon_csa(struct sk_buff * rskb,struct sk_buff * skb,struct bss_info_bcn * bcn,struct ieee80211_mutable_offsets * offs)2379*4882a593Smuzhiyun mt7915_mcu_beacon_csa(struct sk_buff *rskb, struct sk_buff *skb,
2380*4882a593Smuzhiyun struct bss_info_bcn *bcn,
2381*4882a593Smuzhiyun struct ieee80211_mutable_offsets *offs)
2382*4882a593Smuzhiyun {
2383*4882a593Smuzhiyun if (offs->cntdwn_counter_offs[0]) {
2384*4882a593Smuzhiyun struct tlv *tlv;
2385*4882a593Smuzhiyun struct bss_info_bcn_csa *csa;
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_subtlv(rskb, BSS_INFO_BCN_CSA,
2388*4882a593Smuzhiyun sizeof(*csa), &bcn->sub_ntlv,
2389*4882a593Smuzhiyun &bcn->len);
2390*4882a593Smuzhiyun csa = (struct bss_info_bcn_csa *)tlv;
2391*4882a593Smuzhiyun csa->cnt = skb->data[offs->cntdwn_counter_offs[0]];
2392*4882a593Smuzhiyun }
2393*4882a593Smuzhiyun }
2394*4882a593Smuzhiyun
2395*4882a593Smuzhiyun static void
mt7915_mcu_beacon_cont(struct mt7915_dev * dev,struct sk_buff * rskb,struct sk_buff * skb,struct bss_info_bcn * bcn,struct ieee80211_mutable_offsets * offs)2396*4882a593Smuzhiyun mt7915_mcu_beacon_cont(struct mt7915_dev *dev, struct sk_buff *rskb,
2397*4882a593Smuzhiyun struct sk_buff *skb, struct bss_info_bcn *bcn,
2398*4882a593Smuzhiyun struct ieee80211_mutable_offsets *offs)
2399*4882a593Smuzhiyun {
2400*4882a593Smuzhiyun struct mt76_wcid *wcid = &dev->mt76.global_wcid;
2401*4882a593Smuzhiyun struct bss_info_bcn_cont *cont;
2402*4882a593Smuzhiyun struct tlv *tlv;
2403*4882a593Smuzhiyun u8 *buf;
2404*4882a593Smuzhiyun int len = sizeof(*cont) + MT_TXD_SIZE + skb->len;
2405*4882a593Smuzhiyun
2406*4882a593Smuzhiyun tlv = mt7915_mcu_add_nested_subtlv(rskb, BSS_INFO_BCN_CONTENT,
2407*4882a593Smuzhiyun len, &bcn->sub_ntlv, &bcn->len);
2408*4882a593Smuzhiyun
2409*4882a593Smuzhiyun cont = (struct bss_info_bcn_cont *)tlv;
2410*4882a593Smuzhiyun cont->pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
2411*4882a593Smuzhiyun cont->tim_ofs = cpu_to_le16(offs->tim_offset);
2412*4882a593Smuzhiyun
2413*4882a593Smuzhiyun if (offs->cntdwn_counter_offs[0])
2414*4882a593Smuzhiyun cont->csa_ofs = cpu_to_le16(offs->cntdwn_counter_offs[0] - 4);
2415*4882a593Smuzhiyun
2416*4882a593Smuzhiyun buf = (u8 *)tlv + sizeof(*cont);
2417*4882a593Smuzhiyun mt7915_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
2418*4882a593Smuzhiyun true);
2419*4882a593Smuzhiyun memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
2420*4882a593Smuzhiyun }
2421*4882a593Smuzhiyun
mt7915_mcu_add_beacon(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int en)2422*4882a593Smuzhiyun int mt7915_mcu_add_beacon(struct ieee80211_hw *hw,
2423*4882a593Smuzhiyun struct ieee80211_vif *vif, int en)
2424*4882a593Smuzhiyun {
2425*4882a593Smuzhiyun #define MAX_BEACON_SIZE 512
2426*4882a593Smuzhiyun struct mt7915_dev *dev = mt7915_hw_dev(hw);
2427*4882a593Smuzhiyun struct mt7915_phy *phy = mt7915_hw_phy(hw);
2428*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
2429*4882a593Smuzhiyun struct ieee80211_mutable_offsets offs;
2430*4882a593Smuzhiyun struct ieee80211_tx_info *info;
2431*4882a593Smuzhiyun struct sk_buff *skb, *rskb;
2432*4882a593Smuzhiyun struct tlv *tlv;
2433*4882a593Smuzhiyun struct bss_info_bcn *bcn;
2434*4882a593Smuzhiyun int len = MT7915_BEACON_UPDATE_SIZE + MAX_BEACON_SIZE;
2435*4882a593Smuzhiyun
2436*4882a593Smuzhiyun skb = ieee80211_beacon_get_template(hw, vif, &offs);
2437*4882a593Smuzhiyun if (!skb)
2438*4882a593Smuzhiyun return -EINVAL;
2439*4882a593Smuzhiyun
2440*4882a593Smuzhiyun if (skb->len > MAX_BEACON_SIZE - MT_TXD_SIZE) {
2441*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Bcn size limit exceed\n");
2442*4882a593Smuzhiyun dev_kfree_skb(skb);
2443*4882a593Smuzhiyun return -EINVAL;
2444*4882a593Smuzhiyun }
2445*4882a593Smuzhiyun
2446*4882a593Smuzhiyun rskb = mt7915_mcu_alloc_sta_req(dev, mvif, NULL, len);
2447*4882a593Smuzhiyun if (IS_ERR(rskb)) {
2448*4882a593Smuzhiyun dev_kfree_skb(skb);
2449*4882a593Smuzhiyun return PTR_ERR(rskb);
2450*4882a593Smuzhiyun }
2451*4882a593Smuzhiyun
2452*4882a593Smuzhiyun tlv = mt7915_mcu_add_tlv(rskb, BSS_INFO_OFFLOAD, sizeof(*bcn));
2453*4882a593Smuzhiyun bcn = (struct bss_info_bcn *)tlv;
2454*4882a593Smuzhiyun bcn->enable = en;
2455*4882a593Smuzhiyun
2456*4882a593Smuzhiyun if (mvif->band_idx) {
2457*4882a593Smuzhiyun info = IEEE80211_SKB_CB(skb);
2458*4882a593Smuzhiyun info->hw_queue |= MT_TX_HW_QUEUE_EXT_PHY;
2459*4882a593Smuzhiyun }
2460*4882a593Smuzhiyun
2461*4882a593Smuzhiyun /* TODO: subtag - bss color count & 11v MBSSID */
2462*4882a593Smuzhiyun mt7915_mcu_beacon_csa(rskb, skb, bcn, &offs);
2463*4882a593Smuzhiyun mt7915_mcu_beacon_cont(dev, rskb, skb, bcn, &offs);
2464*4882a593Smuzhiyun dev_kfree_skb(skb);
2465*4882a593Smuzhiyun
2466*4882a593Smuzhiyun return __mt76_mcu_skb_send_msg(&phy->dev->mt76, rskb,
2467*4882a593Smuzhiyun MCU_EXT_CMD_BSS_INFO_UPDATE, true);
2468*4882a593Smuzhiyun }
2469*4882a593Smuzhiyun
mt7915_mcu_send_firmware(struct mt7915_dev * dev,const void * data,int len)2470*4882a593Smuzhiyun static int mt7915_mcu_send_firmware(struct mt7915_dev *dev, const void *data,
2471*4882a593Smuzhiyun int len)
2472*4882a593Smuzhiyun {
2473*4882a593Smuzhiyun int ret = 0, cur_len;
2474*4882a593Smuzhiyun
2475*4882a593Smuzhiyun while (len > 0) {
2476*4882a593Smuzhiyun cur_len = min_t(int, 4096 - sizeof(struct mt7915_mcu_txd),
2477*4882a593Smuzhiyun len);
2478*4882a593Smuzhiyun
2479*4882a593Smuzhiyun ret = __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_FW_SCATTER,
2480*4882a593Smuzhiyun data, cur_len, false);
2481*4882a593Smuzhiyun if (ret)
2482*4882a593Smuzhiyun break;
2483*4882a593Smuzhiyun
2484*4882a593Smuzhiyun data += cur_len;
2485*4882a593Smuzhiyun len -= cur_len;
2486*4882a593Smuzhiyun mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false);
2487*4882a593Smuzhiyun }
2488*4882a593Smuzhiyun
2489*4882a593Smuzhiyun return ret;
2490*4882a593Smuzhiyun }
2491*4882a593Smuzhiyun
mt7915_mcu_start_firmware(struct mt7915_dev * dev,u32 addr,u32 option)2492*4882a593Smuzhiyun static int mt7915_mcu_start_firmware(struct mt7915_dev *dev, u32 addr,
2493*4882a593Smuzhiyun u32 option)
2494*4882a593Smuzhiyun {
2495*4882a593Smuzhiyun struct {
2496*4882a593Smuzhiyun __le32 option;
2497*4882a593Smuzhiyun __le32 addr;
2498*4882a593Smuzhiyun } req = {
2499*4882a593Smuzhiyun .option = cpu_to_le32(option),
2500*4882a593Smuzhiyun .addr = cpu_to_le32(addr),
2501*4882a593Smuzhiyun };
2502*4882a593Smuzhiyun
2503*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_FW_START_REQ,
2504*4882a593Smuzhiyun &req, sizeof(req), true);
2505*4882a593Smuzhiyun }
2506*4882a593Smuzhiyun
mt7915_mcu_restart(struct mt76_dev * dev)2507*4882a593Smuzhiyun static int mt7915_mcu_restart(struct mt76_dev *dev)
2508*4882a593Smuzhiyun {
2509*4882a593Smuzhiyun struct {
2510*4882a593Smuzhiyun u8 power_mode;
2511*4882a593Smuzhiyun u8 rsv[3];
2512*4882a593Smuzhiyun } req = {
2513*4882a593Smuzhiyun .power_mode = 1,
2514*4882a593Smuzhiyun };
2515*4882a593Smuzhiyun
2516*4882a593Smuzhiyun return __mt76_mcu_send_msg(dev, -MCU_CMD_NIC_POWER_CTRL, &req,
2517*4882a593Smuzhiyun sizeof(req), false);
2518*4882a593Smuzhiyun }
2519*4882a593Smuzhiyun
mt7915_mcu_patch_sem_ctrl(struct mt7915_dev * dev,bool get)2520*4882a593Smuzhiyun static int mt7915_mcu_patch_sem_ctrl(struct mt7915_dev *dev, bool get)
2521*4882a593Smuzhiyun {
2522*4882a593Smuzhiyun struct {
2523*4882a593Smuzhiyun __le32 op;
2524*4882a593Smuzhiyun } req = {
2525*4882a593Smuzhiyun .op = cpu_to_le32(get ? PATCH_SEM_GET : PATCH_SEM_RELEASE),
2526*4882a593Smuzhiyun };
2527*4882a593Smuzhiyun
2528*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_PATCH_SEM_CONTROL,
2529*4882a593Smuzhiyun &req, sizeof(req), true);
2530*4882a593Smuzhiyun }
2531*4882a593Smuzhiyun
mt7915_mcu_start_patch(struct mt7915_dev * dev)2532*4882a593Smuzhiyun static int mt7915_mcu_start_patch(struct mt7915_dev *dev)
2533*4882a593Smuzhiyun {
2534*4882a593Smuzhiyun struct {
2535*4882a593Smuzhiyun u8 check_crc;
2536*4882a593Smuzhiyun u8 reserved[3];
2537*4882a593Smuzhiyun } req = {
2538*4882a593Smuzhiyun .check_crc = 0,
2539*4882a593Smuzhiyun };
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_PATCH_FINISH_REQ,
2542*4882a593Smuzhiyun &req, sizeof(req), true);
2543*4882a593Smuzhiyun }
2544*4882a593Smuzhiyun
mt7915_driver_own(struct mt7915_dev * dev)2545*4882a593Smuzhiyun static int mt7915_driver_own(struct mt7915_dev *dev)
2546*4882a593Smuzhiyun {
2547*4882a593Smuzhiyun u32 reg = mt7915_reg_map_l1(dev, MT_TOP_LPCR_HOST_BAND0);
2548*4882a593Smuzhiyun
2549*4882a593Smuzhiyun mt76_wr(dev, reg, MT_TOP_LPCR_HOST_DRV_OWN);
2550*4882a593Smuzhiyun if (!mt76_poll_msec(dev, reg, MT_TOP_LPCR_HOST_FW_OWN,
2551*4882a593Smuzhiyun 0, 500)) {
2552*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Timeout for driver own\n");
2553*4882a593Smuzhiyun return -EIO;
2554*4882a593Smuzhiyun }
2555*4882a593Smuzhiyun
2556*4882a593Smuzhiyun return 0;
2557*4882a593Smuzhiyun }
2558*4882a593Smuzhiyun
mt7915_mcu_init_download(struct mt7915_dev * dev,u32 addr,u32 len,u32 mode)2559*4882a593Smuzhiyun static int mt7915_mcu_init_download(struct mt7915_dev *dev, u32 addr,
2560*4882a593Smuzhiyun u32 len, u32 mode)
2561*4882a593Smuzhiyun {
2562*4882a593Smuzhiyun struct {
2563*4882a593Smuzhiyun __le32 addr;
2564*4882a593Smuzhiyun __le32 len;
2565*4882a593Smuzhiyun __le32 mode;
2566*4882a593Smuzhiyun } req = {
2567*4882a593Smuzhiyun .addr = cpu_to_le32(addr),
2568*4882a593Smuzhiyun .len = cpu_to_le32(len),
2569*4882a593Smuzhiyun .mode = cpu_to_le32(mode),
2570*4882a593Smuzhiyun };
2571*4882a593Smuzhiyun int attr;
2572*4882a593Smuzhiyun
2573*4882a593Smuzhiyun if (req.addr == cpu_to_le32(MCU_PATCH_ADDRESS))
2574*4882a593Smuzhiyun attr = -MCU_CMD_PATCH_START_REQ;
2575*4882a593Smuzhiyun else
2576*4882a593Smuzhiyun attr = -MCU_CMD_TARGET_ADDRESS_LEN_REQ;
2577*4882a593Smuzhiyun
2578*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, attr, &req, sizeof(req), true);
2579*4882a593Smuzhiyun }
2580*4882a593Smuzhiyun
mt7915_load_patch(struct mt7915_dev * dev)2581*4882a593Smuzhiyun static int mt7915_load_patch(struct mt7915_dev *dev)
2582*4882a593Smuzhiyun {
2583*4882a593Smuzhiyun const struct mt7915_patch_hdr *hdr;
2584*4882a593Smuzhiyun const struct firmware *fw = NULL;
2585*4882a593Smuzhiyun int i, ret, sem;
2586*4882a593Smuzhiyun
2587*4882a593Smuzhiyun sem = mt7915_mcu_patch_sem_ctrl(dev, 1);
2588*4882a593Smuzhiyun switch (sem) {
2589*4882a593Smuzhiyun case PATCH_IS_DL:
2590*4882a593Smuzhiyun return 0;
2591*4882a593Smuzhiyun case PATCH_NOT_DL_SEM_SUCCESS:
2592*4882a593Smuzhiyun break;
2593*4882a593Smuzhiyun default:
2594*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to get patch semaphore\n");
2595*4882a593Smuzhiyun return -EAGAIN;
2596*4882a593Smuzhiyun }
2597*4882a593Smuzhiyun
2598*4882a593Smuzhiyun ret = request_firmware(&fw, MT7915_ROM_PATCH, dev->mt76.dev);
2599*4882a593Smuzhiyun if (ret)
2600*4882a593Smuzhiyun goto out;
2601*4882a593Smuzhiyun
2602*4882a593Smuzhiyun if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
2603*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Invalid firmware\n");
2604*4882a593Smuzhiyun ret = -EINVAL;
2605*4882a593Smuzhiyun goto out;
2606*4882a593Smuzhiyun }
2607*4882a593Smuzhiyun
2608*4882a593Smuzhiyun hdr = (const struct mt7915_patch_hdr *)(fw->data);
2609*4882a593Smuzhiyun
2610*4882a593Smuzhiyun dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n",
2611*4882a593Smuzhiyun be32_to_cpu(hdr->hw_sw_ver), hdr->build_date);
2612*4882a593Smuzhiyun
2613*4882a593Smuzhiyun for (i = 0; i < be32_to_cpu(hdr->desc.n_region); i++) {
2614*4882a593Smuzhiyun struct mt7915_patch_sec *sec;
2615*4882a593Smuzhiyun const u8 *dl;
2616*4882a593Smuzhiyun u32 len, addr;
2617*4882a593Smuzhiyun
2618*4882a593Smuzhiyun sec = (struct mt7915_patch_sec *)(fw->data + sizeof(*hdr) +
2619*4882a593Smuzhiyun i * sizeof(*sec));
2620*4882a593Smuzhiyun if ((be32_to_cpu(sec->type) & PATCH_SEC_TYPE_MASK) !=
2621*4882a593Smuzhiyun PATCH_SEC_TYPE_INFO) {
2622*4882a593Smuzhiyun ret = -EINVAL;
2623*4882a593Smuzhiyun goto out;
2624*4882a593Smuzhiyun }
2625*4882a593Smuzhiyun
2626*4882a593Smuzhiyun addr = be32_to_cpu(sec->info.addr);
2627*4882a593Smuzhiyun len = be32_to_cpu(sec->info.len);
2628*4882a593Smuzhiyun dl = fw->data + be32_to_cpu(sec->offs);
2629*4882a593Smuzhiyun
2630*4882a593Smuzhiyun ret = mt7915_mcu_init_download(dev, addr, len,
2631*4882a593Smuzhiyun DL_MODE_NEED_RSP);
2632*4882a593Smuzhiyun if (ret) {
2633*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Download request failed\n");
2634*4882a593Smuzhiyun goto out;
2635*4882a593Smuzhiyun }
2636*4882a593Smuzhiyun
2637*4882a593Smuzhiyun ret = mt7915_mcu_send_firmware(dev, dl, len);
2638*4882a593Smuzhiyun if (ret) {
2639*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to send patch\n");
2640*4882a593Smuzhiyun goto out;
2641*4882a593Smuzhiyun }
2642*4882a593Smuzhiyun }
2643*4882a593Smuzhiyun
2644*4882a593Smuzhiyun ret = mt7915_mcu_start_patch(dev);
2645*4882a593Smuzhiyun if (ret)
2646*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to start patch\n");
2647*4882a593Smuzhiyun
2648*4882a593Smuzhiyun out:
2649*4882a593Smuzhiyun sem = mt7915_mcu_patch_sem_ctrl(dev, 0);
2650*4882a593Smuzhiyun switch (sem) {
2651*4882a593Smuzhiyun case PATCH_REL_SEM_SUCCESS:
2652*4882a593Smuzhiyun break;
2653*4882a593Smuzhiyun default:
2654*4882a593Smuzhiyun ret = -EAGAIN;
2655*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to release patch semaphore\n");
2656*4882a593Smuzhiyun break;
2657*4882a593Smuzhiyun }
2658*4882a593Smuzhiyun release_firmware(fw);
2659*4882a593Smuzhiyun
2660*4882a593Smuzhiyun return ret;
2661*4882a593Smuzhiyun }
2662*4882a593Smuzhiyun
mt7915_mcu_gen_dl_mode(u8 feature_set,bool is_wa)2663*4882a593Smuzhiyun static u32 mt7915_mcu_gen_dl_mode(u8 feature_set, bool is_wa)
2664*4882a593Smuzhiyun {
2665*4882a593Smuzhiyun u32 ret = 0;
2666*4882a593Smuzhiyun
2667*4882a593Smuzhiyun ret |= (feature_set & FW_FEATURE_SET_ENCRYPT) ?
2668*4882a593Smuzhiyun (DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV) : 0;
2669*4882a593Smuzhiyun ret |= FIELD_PREP(DL_MODE_KEY_IDX,
2670*4882a593Smuzhiyun FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
2671*4882a593Smuzhiyun ret |= DL_MODE_NEED_RSP;
2672*4882a593Smuzhiyun ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
2673*4882a593Smuzhiyun
2674*4882a593Smuzhiyun return ret;
2675*4882a593Smuzhiyun }
2676*4882a593Smuzhiyun
2677*4882a593Smuzhiyun static int
mt7915_mcu_send_ram_firmware(struct mt7915_dev * dev,const struct mt7915_fw_trailer * hdr,const u8 * data,bool is_wa)2678*4882a593Smuzhiyun mt7915_mcu_send_ram_firmware(struct mt7915_dev *dev,
2679*4882a593Smuzhiyun const struct mt7915_fw_trailer *hdr,
2680*4882a593Smuzhiyun const u8 *data, bool is_wa)
2681*4882a593Smuzhiyun {
2682*4882a593Smuzhiyun int i, offset = 0;
2683*4882a593Smuzhiyun u32 override = 0, option = 0;
2684*4882a593Smuzhiyun
2685*4882a593Smuzhiyun for (i = 0; i < hdr->n_region; i++) {
2686*4882a593Smuzhiyun const struct mt7915_fw_region *region;
2687*4882a593Smuzhiyun int err;
2688*4882a593Smuzhiyun u32 len, addr, mode;
2689*4882a593Smuzhiyun
2690*4882a593Smuzhiyun region = (const struct mt7915_fw_region *)((const u8 *)hdr -
2691*4882a593Smuzhiyun (hdr->n_region - i) * sizeof(*region));
2692*4882a593Smuzhiyun mode = mt7915_mcu_gen_dl_mode(region->feature_set, is_wa);
2693*4882a593Smuzhiyun len = le32_to_cpu(region->len);
2694*4882a593Smuzhiyun addr = le32_to_cpu(region->addr);
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun if (region->feature_set & FW_FEATURE_OVERRIDE_ADDR)
2697*4882a593Smuzhiyun override = addr;
2698*4882a593Smuzhiyun
2699*4882a593Smuzhiyun err = mt7915_mcu_init_download(dev, addr, len, mode);
2700*4882a593Smuzhiyun if (err) {
2701*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Download request failed\n");
2702*4882a593Smuzhiyun return err;
2703*4882a593Smuzhiyun }
2704*4882a593Smuzhiyun
2705*4882a593Smuzhiyun err = mt7915_mcu_send_firmware(dev, data + offset, len);
2706*4882a593Smuzhiyun if (err) {
2707*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to send firmware.\n");
2708*4882a593Smuzhiyun return err;
2709*4882a593Smuzhiyun }
2710*4882a593Smuzhiyun
2711*4882a593Smuzhiyun offset += len;
2712*4882a593Smuzhiyun }
2713*4882a593Smuzhiyun
2714*4882a593Smuzhiyun if (override)
2715*4882a593Smuzhiyun option |= FW_START_OVERRIDE;
2716*4882a593Smuzhiyun
2717*4882a593Smuzhiyun if (is_wa)
2718*4882a593Smuzhiyun option |= FW_START_WORKING_PDA_CR4;
2719*4882a593Smuzhiyun
2720*4882a593Smuzhiyun return mt7915_mcu_start_firmware(dev, override, option);
2721*4882a593Smuzhiyun }
2722*4882a593Smuzhiyun
mt7915_load_ram(struct mt7915_dev * dev)2723*4882a593Smuzhiyun static int mt7915_load_ram(struct mt7915_dev *dev)
2724*4882a593Smuzhiyun {
2725*4882a593Smuzhiyun const struct mt7915_fw_trailer *hdr;
2726*4882a593Smuzhiyun const struct firmware *fw;
2727*4882a593Smuzhiyun int ret;
2728*4882a593Smuzhiyun
2729*4882a593Smuzhiyun ret = request_firmware(&fw, MT7915_FIRMWARE_WM, dev->mt76.dev);
2730*4882a593Smuzhiyun if (ret)
2731*4882a593Smuzhiyun return ret;
2732*4882a593Smuzhiyun
2733*4882a593Smuzhiyun if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
2734*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Invalid firmware\n");
2735*4882a593Smuzhiyun ret = -EINVAL;
2736*4882a593Smuzhiyun goto out;
2737*4882a593Smuzhiyun }
2738*4882a593Smuzhiyun
2739*4882a593Smuzhiyun hdr = (const struct mt7915_fw_trailer *)(fw->data + fw->size -
2740*4882a593Smuzhiyun sizeof(*hdr));
2741*4882a593Smuzhiyun
2742*4882a593Smuzhiyun dev_info(dev->mt76.dev, "WM Firmware Version: %.10s, Build Time: %.15s\n",
2743*4882a593Smuzhiyun hdr->fw_ver, hdr->build_date);
2744*4882a593Smuzhiyun
2745*4882a593Smuzhiyun ret = mt7915_mcu_send_ram_firmware(dev, hdr, fw->data, false);
2746*4882a593Smuzhiyun if (ret) {
2747*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to start WM firmware\n");
2748*4882a593Smuzhiyun goto out;
2749*4882a593Smuzhiyun }
2750*4882a593Smuzhiyun
2751*4882a593Smuzhiyun release_firmware(fw);
2752*4882a593Smuzhiyun
2753*4882a593Smuzhiyun ret = request_firmware(&fw, MT7915_FIRMWARE_WA, dev->mt76.dev);
2754*4882a593Smuzhiyun if (ret)
2755*4882a593Smuzhiyun return ret;
2756*4882a593Smuzhiyun
2757*4882a593Smuzhiyun if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
2758*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Invalid firmware\n");
2759*4882a593Smuzhiyun ret = -EINVAL;
2760*4882a593Smuzhiyun goto out;
2761*4882a593Smuzhiyun }
2762*4882a593Smuzhiyun
2763*4882a593Smuzhiyun hdr = (const struct mt7915_fw_trailer *)(fw->data + fw->size -
2764*4882a593Smuzhiyun sizeof(*hdr));
2765*4882a593Smuzhiyun
2766*4882a593Smuzhiyun dev_info(dev->mt76.dev, "WA Firmware Version: %.10s, Build Time: %.15s\n",
2767*4882a593Smuzhiyun hdr->fw_ver, hdr->build_date);
2768*4882a593Smuzhiyun
2769*4882a593Smuzhiyun ret = mt7915_mcu_send_ram_firmware(dev, hdr, fw->data, true);
2770*4882a593Smuzhiyun if (ret) {
2771*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to start WA firmware\n");
2772*4882a593Smuzhiyun goto out;
2773*4882a593Smuzhiyun }
2774*4882a593Smuzhiyun
2775*4882a593Smuzhiyun snprintf(dev->mt76.hw->wiphy->fw_version,
2776*4882a593Smuzhiyun sizeof(dev->mt76.hw->wiphy->fw_version),
2777*4882a593Smuzhiyun "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
2778*4882a593Smuzhiyun
2779*4882a593Smuzhiyun out:
2780*4882a593Smuzhiyun release_firmware(fw);
2781*4882a593Smuzhiyun
2782*4882a593Smuzhiyun return ret;
2783*4882a593Smuzhiyun }
2784*4882a593Smuzhiyun
mt7915_load_firmware(struct mt7915_dev * dev)2785*4882a593Smuzhiyun static int mt7915_load_firmware(struct mt7915_dev *dev)
2786*4882a593Smuzhiyun {
2787*4882a593Smuzhiyun int ret;
2788*4882a593Smuzhiyun u32 val, reg = mt7915_reg_map_l1(dev, MT_TOP_MISC);
2789*4882a593Smuzhiyun
2790*4882a593Smuzhiyun val = FIELD_PREP(MT_TOP_MISC_FW_STATE, FW_STATE_FW_DOWNLOAD);
2791*4882a593Smuzhiyun
2792*4882a593Smuzhiyun if (!mt76_poll_msec(dev, reg, MT_TOP_MISC_FW_STATE, val, 1000)) {
2793*4882a593Smuzhiyun /* restart firmware once */
2794*4882a593Smuzhiyun __mt76_mcu_restart(&dev->mt76);
2795*4882a593Smuzhiyun if (!mt76_poll_msec(dev, reg, MT_TOP_MISC_FW_STATE,
2796*4882a593Smuzhiyun val, 1000)) {
2797*4882a593Smuzhiyun dev_err(dev->mt76.dev,
2798*4882a593Smuzhiyun "Firmware is not ready for download\n");
2799*4882a593Smuzhiyun return -EIO;
2800*4882a593Smuzhiyun }
2801*4882a593Smuzhiyun }
2802*4882a593Smuzhiyun
2803*4882a593Smuzhiyun ret = mt7915_load_patch(dev);
2804*4882a593Smuzhiyun if (ret)
2805*4882a593Smuzhiyun return ret;
2806*4882a593Smuzhiyun
2807*4882a593Smuzhiyun ret = mt7915_load_ram(dev);
2808*4882a593Smuzhiyun if (ret)
2809*4882a593Smuzhiyun return ret;
2810*4882a593Smuzhiyun
2811*4882a593Smuzhiyun if (!mt76_poll_msec(dev, reg, MT_TOP_MISC_FW_STATE,
2812*4882a593Smuzhiyun FIELD_PREP(MT_TOP_MISC_FW_STATE,
2813*4882a593Smuzhiyun FW_STATE_WACPU_RDY), 1000)) {
2814*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
2815*4882a593Smuzhiyun return -EIO;
2816*4882a593Smuzhiyun }
2817*4882a593Smuzhiyun
2818*4882a593Smuzhiyun mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false);
2819*4882a593Smuzhiyun
2820*4882a593Smuzhiyun dev_dbg(dev->mt76.dev, "Firmware init done\n");
2821*4882a593Smuzhiyun
2822*4882a593Smuzhiyun return 0;
2823*4882a593Smuzhiyun }
2824*4882a593Smuzhiyun
mt7915_mcu_fw_log_2_host(struct mt7915_dev * dev,u8 ctrl)2825*4882a593Smuzhiyun int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 ctrl)
2826*4882a593Smuzhiyun {
2827*4882a593Smuzhiyun struct {
2828*4882a593Smuzhiyun u8 ctrl_val;
2829*4882a593Smuzhiyun u8 pad[3];
2830*4882a593Smuzhiyun } data = {
2831*4882a593Smuzhiyun .ctrl_val = ctrl
2832*4882a593Smuzhiyun };
2833*4882a593Smuzhiyun
2834*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_FW_LOG_2_HOST,
2835*4882a593Smuzhiyun &data, sizeof(data), true);
2836*4882a593Smuzhiyun }
2837*4882a593Smuzhiyun
mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev * dev,u32 module,u8 level)2838*4882a593Smuzhiyun int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level)
2839*4882a593Smuzhiyun {
2840*4882a593Smuzhiyun struct {
2841*4882a593Smuzhiyun u8 ver;
2842*4882a593Smuzhiyun u8 pad;
2843*4882a593Smuzhiyun __le16 len;
2844*4882a593Smuzhiyun u8 level;
2845*4882a593Smuzhiyun u8 rsv[3];
2846*4882a593Smuzhiyun __le32 module_idx;
2847*4882a593Smuzhiyun } data = {
2848*4882a593Smuzhiyun .module_idx = cpu_to_le32(module),
2849*4882a593Smuzhiyun .level = level,
2850*4882a593Smuzhiyun };
2851*4882a593Smuzhiyun
2852*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_FW_DBG_CTRL,
2853*4882a593Smuzhiyun &data, sizeof(data), false);
2854*4882a593Smuzhiyun }
2855*4882a593Smuzhiyun
mt7915_mcu_init(struct mt7915_dev * dev)2856*4882a593Smuzhiyun int mt7915_mcu_init(struct mt7915_dev *dev)
2857*4882a593Smuzhiyun {
2858*4882a593Smuzhiyun static const struct mt76_mcu_ops mt7915_mcu_ops = {
2859*4882a593Smuzhiyun .headroom = sizeof(struct mt7915_mcu_txd),
2860*4882a593Smuzhiyun .mcu_skb_send_msg = mt7915_mcu_send_message,
2861*4882a593Smuzhiyun .mcu_send_msg = mt7915_mcu_msg_send,
2862*4882a593Smuzhiyun .mcu_restart = mt7915_mcu_restart,
2863*4882a593Smuzhiyun };
2864*4882a593Smuzhiyun int ret;
2865*4882a593Smuzhiyun
2866*4882a593Smuzhiyun dev->mt76.mcu_ops = &mt7915_mcu_ops,
2867*4882a593Smuzhiyun
2868*4882a593Smuzhiyun ret = mt7915_driver_own(dev);
2869*4882a593Smuzhiyun if (ret)
2870*4882a593Smuzhiyun return ret;
2871*4882a593Smuzhiyun
2872*4882a593Smuzhiyun ret = mt7915_load_firmware(dev);
2873*4882a593Smuzhiyun if (ret)
2874*4882a593Smuzhiyun return ret;
2875*4882a593Smuzhiyun
2876*4882a593Smuzhiyun set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
2877*4882a593Smuzhiyun mt7915_mcu_fw_log_2_host(dev, 0);
2878*4882a593Smuzhiyun
2879*4882a593Smuzhiyun return 0;
2880*4882a593Smuzhiyun }
2881*4882a593Smuzhiyun
mt7915_mcu_exit(struct mt7915_dev * dev)2882*4882a593Smuzhiyun void mt7915_mcu_exit(struct mt7915_dev *dev)
2883*4882a593Smuzhiyun {
2884*4882a593Smuzhiyun u32 reg = mt7915_reg_map_l1(dev, MT_TOP_MISC);
2885*4882a593Smuzhiyun
2886*4882a593Smuzhiyun __mt76_mcu_restart(&dev->mt76);
2887*4882a593Smuzhiyun if (!mt76_poll_msec(dev, reg, MT_TOP_MISC_FW_STATE,
2888*4882a593Smuzhiyun FIELD_PREP(MT_TOP_MISC_FW_STATE,
2889*4882a593Smuzhiyun FW_STATE_FW_DOWNLOAD), 1000)) {
2890*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Failed to exit mcu\n");
2891*4882a593Smuzhiyun return;
2892*4882a593Smuzhiyun }
2893*4882a593Smuzhiyun
2894*4882a593Smuzhiyun reg = mt7915_reg_map_l1(dev, MT_TOP_LPCR_HOST_BAND0);
2895*4882a593Smuzhiyun mt76_wr(dev, reg, MT_TOP_LPCR_HOST_FW_OWN);
2896*4882a593Smuzhiyun skb_queue_purge(&dev->mt76.mcu.res_q);
2897*4882a593Smuzhiyun }
2898*4882a593Smuzhiyun
mt7915_mcu_set_mac(struct mt7915_dev * dev,int band,bool enable,bool hdr_trans)2899*4882a593Smuzhiyun int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band,
2900*4882a593Smuzhiyun bool enable, bool hdr_trans)
2901*4882a593Smuzhiyun {
2902*4882a593Smuzhiyun struct {
2903*4882a593Smuzhiyun u8 operation;
2904*4882a593Smuzhiyun u8 enable;
2905*4882a593Smuzhiyun u8 check_bssid;
2906*4882a593Smuzhiyun u8 insert_vlan;
2907*4882a593Smuzhiyun u8 remove_vlan;
2908*4882a593Smuzhiyun u8 tid;
2909*4882a593Smuzhiyun u8 mode;
2910*4882a593Smuzhiyun u8 rsv;
2911*4882a593Smuzhiyun } __packed req_trans = {
2912*4882a593Smuzhiyun .enable = hdr_trans,
2913*4882a593Smuzhiyun };
2914*4882a593Smuzhiyun struct {
2915*4882a593Smuzhiyun u8 enable;
2916*4882a593Smuzhiyun u8 band;
2917*4882a593Smuzhiyun u8 rsv[2];
2918*4882a593Smuzhiyun } __packed req_mac = {
2919*4882a593Smuzhiyun .enable = enable,
2920*4882a593Smuzhiyun .band = band,
2921*4882a593Smuzhiyun };
2922*4882a593Smuzhiyun int ret;
2923*4882a593Smuzhiyun
2924*4882a593Smuzhiyun ret = __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RX_HDR_TRANS,
2925*4882a593Smuzhiyun &req_trans, sizeof(req_trans), false);
2926*4882a593Smuzhiyun if (ret)
2927*4882a593Smuzhiyun return ret;
2928*4882a593Smuzhiyun
2929*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_MAC_INIT_CTRL,
2930*4882a593Smuzhiyun &req_mac, sizeof(req_mac), true);
2931*4882a593Smuzhiyun }
2932*4882a593Smuzhiyun
mt7915_mcu_set_scs(struct mt7915_dev * dev,u8 band,bool enable)2933*4882a593Smuzhiyun int mt7915_mcu_set_scs(struct mt7915_dev *dev, u8 band, bool enable)
2934*4882a593Smuzhiyun {
2935*4882a593Smuzhiyun struct {
2936*4882a593Smuzhiyun __le32 cmd;
2937*4882a593Smuzhiyun u8 band;
2938*4882a593Smuzhiyun u8 enable;
2939*4882a593Smuzhiyun } __packed req = {
2940*4882a593Smuzhiyun .cmd = cpu_to_le32(SCS_ENABLE),
2941*4882a593Smuzhiyun .band = band,
2942*4882a593Smuzhiyun .enable = enable + 1,
2943*4882a593Smuzhiyun };
2944*4882a593Smuzhiyun
2945*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SCS_CTRL, &req,
2946*4882a593Smuzhiyun sizeof(req), false);
2947*4882a593Smuzhiyun }
2948*4882a593Smuzhiyun
mt7915_mcu_set_rts_thresh(struct mt7915_phy * phy,u32 val)2949*4882a593Smuzhiyun int mt7915_mcu_set_rts_thresh(struct mt7915_phy *phy, u32 val)
2950*4882a593Smuzhiyun {
2951*4882a593Smuzhiyun struct mt7915_dev *dev = phy->dev;
2952*4882a593Smuzhiyun struct {
2953*4882a593Smuzhiyun u8 prot_idx;
2954*4882a593Smuzhiyun u8 band;
2955*4882a593Smuzhiyun u8 rsv[2];
2956*4882a593Smuzhiyun __le32 len_thresh;
2957*4882a593Smuzhiyun __le32 pkt_thresh;
2958*4882a593Smuzhiyun } __packed req = {
2959*4882a593Smuzhiyun .prot_idx = 1,
2960*4882a593Smuzhiyun .band = phy != &dev->phy,
2961*4882a593Smuzhiyun .len_thresh = cpu_to_le32(val),
2962*4882a593Smuzhiyun .pkt_thresh = cpu_to_le32(0x2),
2963*4882a593Smuzhiyun };
2964*4882a593Smuzhiyun
2965*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PROTECT_CTRL,
2966*4882a593Smuzhiyun &req, sizeof(req), true);
2967*4882a593Smuzhiyun }
2968*4882a593Smuzhiyun
mt7915_mcu_set_tx(struct mt7915_dev * dev,struct ieee80211_vif * vif)2969*4882a593Smuzhiyun int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif)
2970*4882a593Smuzhiyun {
2971*4882a593Smuzhiyun #define WMM_AIFS_SET BIT(0)
2972*4882a593Smuzhiyun #define WMM_CW_MIN_SET BIT(1)
2973*4882a593Smuzhiyun #define WMM_CW_MAX_SET BIT(2)
2974*4882a593Smuzhiyun #define WMM_TXOP_SET BIT(3)
2975*4882a593Smuzhiyun #define WMM_PARAM_SET GENMASK(3, 0)
2976*4882a593Smuzhiyun #define TX_CMD_MODE 1
2977*4882a593Smuzhiyun struct edca {
2978*4882a593Smuzhiyun u8 queue;
2979*4882a593Smuzhiyun u8 set;
2980*4882a593Smuzhiyun u8 aifs;
2981*4882a593Smuzhiyun u8 cw_min;
2982*4882a593Smuzhiyun __le16 cw_max;
2983*4882a593Smuzhiyun __le16 txop;
2984*4882a593Smuzhiyun };
2985*4882a593Smuzhiyun struct mt7915_mcu_tx {
2986*4882a593Smuzhiyun u8 total;
2987*4882a593Smuzhiyun u8 action;
2988*4882a593Smuzhiyun u8 valid;
2989*4882a593Smuzhiyun u8 mode;
2990*4882a593Smuzhiyun
2991*4882a593Smuzhiyun struct edca edca[IEEE80211_NUM_ACS];
2992*4882a593Smuzhiyun } __packed req = {
2993*4882a593Smuzhiyun .valid = true,
2994*4882a593Smuzhiyun .mode = TX_CMD_MODE,
2995*4882a593Smuzhiyun .total = IEEE80211_NUM_ACS,
2996*4882a593Smuzhiyun };
2997*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
2998*4882a593Smuzhiyun int ac;
2999*4882a593Smuzhiyun
3000*4882a593Smuzhiyun for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
3001*4882a593Smuzhiyun struct ieee80211_tx_queue_params *q = &mvif->queue_params[ac];
3002*4882a593Smuzhiyun struct edca *e = &req.edca[ac];
3003*4882a593Smuzhiyun
3004*4882a593Smuzhiyun e->set = WMM_PARAM_SET;
3005*4882a593Smuzhiyun e->queue = ac + mvif->wmm_idx * MT7915_MAX_WMM_SETS;
3006*4882a593Smuzhiyun e->aifs = q->aifs;
3007*4882a593Smuzhiyun e->txop = cpu_to_le16(q->txop);
3008*4882a593Smuzhiyun
3009*4882a593Smuzhiyun if (q->cw_min)
3010*4882a593Smuzhiyun e->cw_min = fls(q->cw_min);
3011*4882a593Smuzhiyun else
3012*4882a593Smuzhiyun e->cw_min = 5;
3013*4882a593Smuzhiyun
3014*4882a593Smuzhiyun if (q->cw_max)
3015*4882a593Smuzhiyun e->cw_max = cpu_to_le16(fls(q->cw_max));
3016*4882a593Smuzhiyun else
3017*4882a593Smuzhiyun e->cw_max = cpu_to_le16(10);
3018*4882a593Smuzhiyun }
3019*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EDCA_UPDATE,
3020*4882a593Smuzhiyun &req, sizeof(req), true);
3021*4882a593Smuzhiyun }
3022*4882a593Smuzhiyun
mt7915_mcu_set_pm(struct mt7915_dev * dev,int band,int enter)3023*4882a593Smuzhiyun int mt7915_mcu_set_pm(struct mt7915_dev *dev, int band, int enter)
3024*4882a593Smuzhiyun {
3025*4882a593Smuzhiyun #define ENTER_PM_STATE 1
3026*4882a593Smuzhiyun #define EXIT_PM_STATE 2
3027*4882a593Smuzhiyun struct {
3028*4882a593Smuzhiyun u8 pm_number;
3029*4882a593Smuzhiyun u8 pm_state;
3030*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
3031*4882a593Smuzhiyun u8 dtim_period;
3032*4882a593Smuzhiyun u8 wlan_idx_lo;
3033*4882a593Smuzhiyun __le16 bcn_interval;
3034*4882a593Smuzhiyun __le32 aid;
3035*4882a593Smuzhiyun __le32 rx_filter;
3036*4882a593Smuzhiyun u8 band_idx;
3037*4882a593Smuzhiyun u8 wlan_idx_hi;
3038*4882a593Smuzhiyun u8 rsv[2];
3039*4882a593Smuzhiyun __le32 feature;
3040*4882a593Smuzhiyun u8 omac_idx;
3041*4882a593Smuzhiyun u8 wmm_idx;
3042*4882a593Smuzhiyun u8 bcn_loss_cnt;
3043*4882a593Smuzhiyun u8 bcn_sp_duration;
3044*4882a593Smuzhiyun } __packed req = {
3045*4882a593Smuzhiyun .pm_number = 5,
3046*4882a593Smuzhiyun .pm_state = (enter) ? ENTER_PM_STATE : EXIT_PM_STATE,
3047*4882a593Smuzhiyun .band_idx = band,
3048*4882a593Smuzhiyun };
3049*4882a593Smuzhiyun
3050*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PM_STATE_CTRL,
3051*4882a593Smuzhiyun &req, sizeof(req), true);
3052*4882a593Smuzhiyun }
3053*4882a593Smuzhiyun
mt7915_mcu_rdd_cmd(struct mt7915_dev * dev,enum mt7915_rdd_cmd cmd,u8 index,u8 rx_sel,u8 val)3054*4882a593Smuzhiyun int mt7915_mcu_rdd_cmd(struct mt7915_dev *dev,
3055*4882a593Smuzhiyun enum mt7915_rdd_cmd cmd, u8 index,
3056*4882a593Smuzhiyun u8 rx_sel, u8 val)
3057*4882a593Smuzhiyun {
3058*4882a593Smuzhiyun struct {
3059*4882a593Smuzhiyun u8 ctrl;
3060*4882a593Smuzhiyun u8 rdd_idx;
3061*4882a593Smuzhiyun u8 rdd_rx_sel;
3062*4882a593Smuzhiyun u8 val;
3063*4882a593Smuzhiyun u8 rsv[4];
3064*4882a593Smuzhiyun } __packed req = {
3065*4882a593Smuzhiyun .ctrl = cmd,
3066*4882a593Smuzhiyun .rdd_idx = index,
3067*4882a593Smuzhiyun .rdd_rx_sel = rx_sel,
3068*4882a593Smuzhiyun .val = val,
3069*4882a593Smuzhiyun };
3070*4882a593Smuzhiyun
3071*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_CTRL,
3072*4882a593Smuzhiyun &req, sizeof(req), true);
3073*4882a593Smuzhiyun }
3074*4882a593Smuzhiyun
mt7915_mcu_set_fcc5_lpn(struct mt7915_dev * dev,int val)3075*4882a593Smuzhiyun int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val)
3076*4882a593Smuzhiyun {
3077*4882a593Smuzhiyun struct {
3078*4882a593Smuzhiyun __le32 tag;
3079*4882a593Smuzhiyun __le16 min_lpn;
3080*4882a593Smuzhiyun u8 rsv[2];
3081*4882a593Smuzhiyun } __packed req = {
3082*4882a593Smuzhiyun .tag = cpu_to_le32(0x1),
3083*4882a593Smuzhiyun .min_lpn = cpu_to_le16(val),
3084*4882a593Smuzhiyun };
3085*4882a593Smuzhiyun
3086*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH,
3087*4882a593Smuzhiyun &req, sizeof(req), true);
3088*4882a593Smuzhiyun }
3089*4882a593Smuzhiyun
mt7915_mcu_set_pulse_th(struct mt7915_dev * dev,const struct mt7915_dfs_pulse * pulse)3090*4882a593Smuzhiyun int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,
3091*4882a593Smuzhiyun const struct mt7915_dfs_pulse *pulse)
3092*4882a593Smuzhiyun {
3093*4882a593Smuzhiyun struct {
3094*4882a593Smuzhiyun __le32 tag;
3095*4882a593Smuzhiyun
3096*4882a593Smuzhiyun __le32 max_width; /* us */
3097*4882a593Smuzhiyun __le32 max_pwr; /* dbm */
3098*4882a593Smuzhiyun __le32 min_pwr; /* dbm */
3099*4882a593Smuzhiyun __le32 min_stgr_pri; /* us */
3100*4882a593Smuzhiyun __le32 max_stgr_pri; /* us */
3101*4882a593Smuzhiyun __le32 min_cr_pri; /* us */
3102*4882a593Smuzhiyun __le32 max_cr_pri; /* us */
3103*4882a593Smuzhiyun } __packed req = {
3104*4882a593Smuzhiyun .tag = cpu_to_le32(0x3),
3105*4882a593Smuzhiyun
3106*4882a593Smuzhiyun #define __req_field(field) .field = cpu_to_le32(pulse->field)
3107*4882a593Smuzhiyun __req_field(max_width),
3108*4882a593Smuzhiyun __req_field(max_pwr),
3109*4882a593Smuzhiyun __req_field(min_pwr),
3110*4882a593Smuzhiyun __req_field(min_stgr_pri),
3111*4882a593Smuzhiyun __req_field(max_stgr_pri),
3112*4882a593Smuzhiyun __req_field(min_cr_pri),
3113*4882a593Smuzhiyun __req_field(max_cr_pri),
3114*4882a593Smuzhiyun #undef __req_field
3115*4882a593Smuzhiyun };
3116*4882a593Smuzhiyun
3117*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH,
3118*4882a593Smuzhiyun &req, sizeof(req), true);
3119*4882a593Smuzhiyun }
3120*4882a593Smuzhiyun
mt7915_mcu_set_radar_th(struct mt7915_dev * dev,int index,const struct mt7915_dfs_pattern * pattern)3121*4882a593Smuzhiyun int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,
3122*4882a593Smuzhiyun const struct mt7915_dfs_pattern *pattern)
3123*4882a593Smuzhiyun {
3124*4882a593Smuzhiyun struct {
3125*4882a593Smuzhiyun __le32 tag;
3126*4882a593Smuzhiyun __le16 radar_type;
3127*4882a593Smuzhiyun
3128*4882a593Smuzhiyun u8 enb;
3129*4882a593Smuzhiyun u8 stgr;
3130*4882a593Smuzhiyun u8 min_crpn;
3131*4882a593Smuzhiyun u8 max_crpn;
3132*4882a593Smuzhiyun u8 min_crpr;
3133*4882a593Smuzhiyun u8 min_pw;
3134*4882a593Smuzhiyun u32 min_pri;
3135*4882a593Smuzhiyun u32 max_pri;
3136*4882a593Smuzhiyun u8 max_pw;
3137*4882a593Smuzhiyun u8 min_crbn;
3138*4882a593Smuzhiyun u8 max_crbn;
3139*4882a593Smuzhiyun u8 min_stgpn;
3140*4882a593Smuzhiyun u8 max_stgpn;
3141*4882a593Smuzhiyun u8 min_stgpr;
3142*4882a593Smuzhiyun u8 rsv[2];
3143*4882a593Smuzhiyun u32 min_stgpr_diff;
3144*4882a593Smuzhiyun } __packed req = {
3145*4882a593Smuzhiyun .tag = cpu_to_le32(0x2),
3146*4882a593Smuzhiyun .radar_type = cpu_to_le16(index),
3147*4882a593Smuzhiyun
3148*4882a593Smuzhiyun #define __req_field_u8(field) .field = pattern->field
3149*4882a593Smuzhiyun #define __req_field_u32(field) .field = cpu_to_le32(pattern->field)
3150*4882a593Smuzhiyun __req_field_u8(enb),
3151*4882a593Smuzhiyun __req_field_u8(stgr),
3152*4882a593Smuzhiyun __req_field_u8(min_crpn),
3153*4882a593Smuzhiyun __req_field_u8(max_crpn),
3154*4882a593Smuzhiyun __req_field_u8(min_crpr),
3155*4882a593Smuzhiyun __req_field_u8(min_pw),
3156*4882a593Smuzhiyun __req_field_u32(min_pri),
3157*4882a593Smuzhiyun __req_field_u32(max_pri),
3158*4882a593Smuzhiyun __req_field_u8(max_pw),
3159*4882a593Smuzhiyun __req_field_u8(min_crbn),
3160*4882a593Smuzhiyun __req_field_u8(max_crbn),
3161*4882a593Smuzhiyun __req_field_u8(min_stgpn),
3162*4882a593Smuzhiyun __req_field_u8(max_stgpn),
3163*4882a593Smuzhiyun __req_field_u8(min_stgpr),
3164*4882a593Smuzhiyun __req_field_u32(min_stgpr_diff),
3165*4882a593Smuzhiyun #undef __req_field_u8
3166*4882a593Smuzhiyun #undef __req_field_u32
3167*4882a593Smuzhiyun };
3168*4882a593Smuzhiyun
3169*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH,
3170*4882a593Smuzhiyun &req, sizeof(req), true);
3171*4882a593Smuzhiyun }
3172*4882a593Smuzhiyun
mt7915_mcu_set_chan_info(struct mt7915_phy * phy,int cmd)3173*4882a593Smuzhiyun int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd)
3174*4882a593Smuzhiyun {
3175*4882a593Smuzhiyun struct mt7915_dev *dev = phy->dev;
3176*4882a593Smuzhiyun struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
3177*4882a593Smuzhiyun int freq1 = chandef->center_freq1;
3178*4882a593Smuzhiyun struct {
3179*4882a593Smuzhiyun u8 control_ch;
3180*4882a593Smuzhiyun u8 center_ch;
3181*4882a593Smuzhiyun u8 bw;
3182*4882a593Smuzhiyun u8 tx_streams_num;
3183*4882a593Smuzhiyun u8 rx_streams; /* mask or num */
3184*4882a593Smuzhiyun u8 switch_reason;
3185*4882a593Smuzhiyun u8 band_idx;
3186*4882a593Smuzhiyun u8 center_ch2; /* for 80+80 only */
3187*4882a593Smuzhiyun __le16 cac_case;
3188*4882a593Smuzhiyun u8 channel_band;
3189*4882a593Smuzhiyun u8 rsv0;
3190*4882a593Smuzhiyun __le32 outband_freq;
3191*4882a593Smuzhiyun u8 txpower_drop;
3192*4882a593Smuzhiyun u8 ap_bw;
3193*4882a593Smuzhiyun u8 ap_center_ch;
3194*4882a593Smuzhiyun u8 rsv1[57];
3195*4882a593Smuzhiyun } __packed req = {
3196*4882a593Smuzhiyun .control_ch = chandef->chan->hw_value,
3197*4882a593Smuzhiyun .center_ch = ieee80211_frequency_to_channel(freq1),
3198*4882a593Smuzhiyun .bw = mt7915_mcu_chan_bw(chandef),
3199*4882a593Smuzhiyun .tx_streams_num = hweight8(phy->mt76->antenna_mask),
3200*4882a593Smuzhiyun .rx_streams = phy->chainmask,
3201*4882a593Smuzhiyun .band_idx = phy != &dev->phy,
3202*4882a593Smuzhiyun .channel_band = chandef->chan->band,
3203*4882a593Smuzhiyun };
3204*4882a593Smuzhiyun
3205*4882a593Smuzhiyun if (dev->mt76.hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
3206*4882a593Smuzhiyun req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD;
3207*4882a593Smuzhiyun else if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) &&
3208*4882a593Smuzhiyun chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
3209*4882a593Smuzhiyun req.switch_reason = CH_SWITCH_DFS;
3210*4882a593Smuzhiyun else
3211*4882a593Smuzhiyun req.switch_reason = CH_SWITCH_NORMAL;
3212*4882a593Smuzhiyun
3213*4882a593Smuzhiyun if (cmd == MCU_EXT_CMD_CHANNEL_SWITCH)
3214*4882a593Smuzhiyun req.rx_streams = hweight8(req.rx_streams);
3215*4882a593Smuzhiyun
3216*4882a593Smuzhiyun if (chandef->width == NL80211_CHAN_WIDTH_80P80) {
3217*4882a593Smuzhiyun int freq2 = chandef->center_freq2;
3218*4882a593Smuzhiyun
3219*4882a593Smuzhiyun req.center_ch2 = ieee80211_frequency_to_channel(freq2);
3220*4882a593Smuzhiyun }
3221*4882a593Smuzhiyun
3222*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true);
3223*4882a593Smuzhiyun }
3224*4882a593Smuzhiyun
mt7915_mcu_set_eeprom(struct mt7915_dev * dev)3225*4882a593Smuzhiyun int mt7915_mcu_set_eeprom(struct mt7915_dev *dev)
3226*4882a593Smuzhiyun {
3227*4882a593Smuzhiyun struct req_hdr {
3228*4882a593Smuzhiyun u8 buffer_mode;
3229*4882a593Smuzhiyun u8 format;
3230*4882a593Smuzhiyun __le16 len;
3231*4882a593Smuzhiyun } __packed req = {
3232*4882a593Smuzhiyun .buffer_mode = EE_MODE_EFUSE,
3233*4882a593Smuzhiyun .format = EE_FORMAT_WHOLE,
3234*4882a593Smuzhiyun };
3235*4882a593Smuzhiyun
3236*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EFUSE_BUFFER_MODE,
3237*4882a593Smuzhiyun &req, sizeof(req), true);
3238*4882a593Smuzhiyun }
3239*4882a593Smuzhiyun
mt7915_mcu_get_eeprom(struct mt7915_dev * dev,u32 offset)3240*4882a593Smuzhiyun int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset)
3241*4882a593Smuzhiyun {
3242*4882a593Smuzhiyun struct mt7915_mcu_eeprom_info req = {
3243*4882a593Smuzhiyun .addr = cpu_to_le32(round_down(offset, 16)),
3244*4882a593Smuzhiyun };
3245*4882a593Smuzhiyun
3246*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EFUSE_ACCESS, &req,
3247*4882a593Smuzhiyun sizeof(req), true);
3248*4882a593Smuzhiyun }
3249*4882a593Smuzhiyun
mt7915_mcu_get_temperature(struct mt7915_dev * dev,int index)3250*4882a593Smuzhiyun int mt7915_mcu_get_temperature(struct mt7915_dev *dev, int index)
3251*4882a593Smuzhiyun {
3252*4882a593Smuzhiyun struct {
3253*4882a593Smuzhiyun u8 ctrl_id;
3254*4882a593Smuzhiyun u8 action;
3255*4882a593Smuzhiyun u8 band;
3256*4882a593Smuzhiyun u8 rsv[5];
3257*4882a593Smuzhiyun } req = {
3258*4882a593Smuzhiyun .ctrl_id = THERMAL_SENSOR_TEMP_QUERY,
3259*4882a593Smuzhiyun .action = index,
3260*4882a593Smuzhiyun };
3261*4882a593Smuzhiyun
3262*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_THERMAL_CTRL, &req,
3263*4882a593Smuzhiyun sizeof(req), true);
3264*4882a593Smuzhiyun }
3265*4882a593Smuzhiyun
mt7915_mcu_get_rate_info(struct mt7915_dev * dev,u32 cmd,u16 wlan_idx)3266*4882a593Smuzhiyun int mt7915_mcu_get_rate_info(struct mt7915_dev *dev, u32 cmd, u16 wlan_idx)
3267*4882a593Smuzhiyun {
3268*4882a593Smuzhiyun struct {
3269*4882a593Smuzhiyun __le32 cmd;
3270*4882a593Smuzhiyun __le16 wlan_idx;
3271*4882a593Smuzhiyun __le16 ru_idx;
3272*4882a593Smuzhiyun __le16 direction;
3273*4882a593Smuzhiyun __le16 dump_group;
3274*4882a593Smuzhiyun } req = {
3275*4882a593Smuzhiyun .cmd = cpu_to_le32(cmd),
3276*4882a593Smuzhiyun .wlan_idx = cpu_to_le16(wlan_idx),
3277*4882a593Smuzhiyun .dump_group = cpu_to_le16(1),
3278*4882a593Smuzhiyun };
3279*4882a593Smuzhiyun
3280*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RATE_CTRL, &req,
3281*4882a593Smuzhiyun sizeof(req), false);
3282*4882a593Smuzhiyun }
3283*4882a593Smuzhiyun
mt7915_mcu_set_sku(struct mt7915_phy * phy)3284*4882a593Smuzhiyun int mt7915_mcu_set_sku(struct mt7915_phy *phy)
3285*4882a593Smuzhiyun {
3286*4882a593Smuzhiyun struct mt7915_dev *dev = phy->dev;
3287*4882a593Smuzhiyun struct mt76_phy *mphy = phy->mt76;
3288*4882a593Smuzhiyun struct ieee80211_hw *hw = mphy->hw;
3289*4882a593Smuzhiyun struct mt7915_sku_val {
3290*4882a593Smuzhiyun u8 format_id;
3291*4882a593Smuzhiyun u8 limit_type;
3292*4882a593Smuzhiyun u8 dbdc_idx;
3293*4882a593Smuzhiyun s8 val[MT7915_SKU_RATE_NUM];
3294*4882a593Smuzhiyun } __packed req = {
3295*4882a593Smuzhiyun .format_id = 4,
3296*4882a593Smuzhiyun .dbdc_idx = phy != &dev->phy,
3297*4882a593Smuzhiyun };
3298*4882a593Smuzhiyun int i;
3299*4882a593Smuzhiyun s8 *delta;
3300*4882a593Smuzhiyun
3301*4882a593Smuzhiyun delta = dev->rate_power[mphy->chandef.chan->band];
3302*4882a593Smuzhiyun mphy->txpower_cur = hw->conf.power_level * 2 +
3303*4882a593Smuzhiyun delta[MT7915_SKU_MAX_DELTA_IDX];
3304*4882a593Smuzhiyun
3305*4882a593Smuzhiyun for (i = 0; i < MT7915_SKU_RATE_NUM; i++)
3306*4882a593Smuzhiyun req.val[i] = hw->conf.power_level * 2 + delta[i];
3307*4882a593Smuzhiyun
3308*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76,
3309*4882a593Smuzhiyun MCU_EXT_CMD_TX_POWER_FEATURE_CTRL,
3310*4882a593Smuzhiyun &req, sizeof(req), true);
3311*4882a593Smuzhiyun }
3312*4882a593Smuzhiyun
mt7915_mcu_set_sku_en(struct mt7915_phy * phy,bool enable)3313*4882a593Smuzhiyun int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
3314*4882a593Smuzhiyun {
3315*4882a593Smuzhiyun struct mt7915_dev *dev = phy->dev;
3316*4882a593Smuzhiyun struct mt7915_sku {
3317*4882a593Smuzhiyun u8 format_id;
3318*4882a593Smuzhiyun u8 sku_enable;
3319*4882a593Smuzhiyun u8 dbdc_idx;
3320*4882a593Smuzhiyun u8 rsv;
3321*4882a593Smuzhiyun } __packed req = {
3322*4882a593Smuzhiyun .format_id = 0,
3323*4882a593Smuzhiyun .dbdc_idx = phy != &dev->phy,
3324*4882a593Smuzhiyun .sku_enable = enable,
3325*4882a593Smuzhiyun };
3326*4882a593Smuzhiyun
3327*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76,
3328*4882a593Smuzhiyun MCU_EXT_CMD_TX_POWER_FEATURE_CTRL,
3329*4882a593Smuzhiyun &req, sizeof(req), true);
3330*4882a593Smuzhiyun }
3331*4882a593Smuzhiyun
mt7915_mcu_set_ser(struct mt7915_dev * dev,u8 action,u8 set,u8 band)3332*4882a593Smuzhiyun int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band)
3333*4882a593Smuzhiyun {
3334*4882a593Smuzhiyun struct {
3335*4882a593Smuzhiyun u8 action;
3336*4882a593Smuzhiyun u8 set;
3337*4882a593Smuzhiyun u8 band;
3338*4882a593Smuzhiyun u8 rsv;
3339*4882a593Smuzhiyun } req = {
3340*4882a593Smuzhiyun .action = action,
3341*4882a593Smuzhiyun .set = set,
3342*4882a593Smuzhiyun .band = band,
3343*4882a593Smuzhiyun };
3344*4882a593Smuzhiyun
3345*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_SER_TRIGGER,
3346*4882a593Smuzhiyun &req, sizeof(req), false);
3347*4882a593Smuzhiyun }
3348*4882a593Smuzhiyun
mt7915_mcu_set_txbf_type(struct mt7915_dev * dev)3349*4882a593Smuzhiyun int mt7915_mcu_set_txbf_type(struct mt7915_dev *dev)
3350*4882a593Smuzhiyun {
3351*4882a593Smuzhiyun #define MT_BF_TYPE_UPDATE 20
3352*4882a593Smuzhiyun struct {
3353*4882a593Smuzhiyun u8 action;
3354*4882a593Smuzhiyun bool ebf;
3355*4882a593Smuzhiyun bool ibf;
3356*4882a593Smuzhiyun u8 rsv;
3357*4882a593Smuzhiyun } __packed req = {
3358*4882a593Smuzhiyun .action = MT_BF_TYPE_UPDATE,
3359*4882a593Smuzhiyun .ebf = true,
3360*4882a593Smuzhiyun .ibf = false,
3361*4882a593Smuzhiyun };
3362*4882a593Smuzhiyun
3363*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_TXBF_ACTION,
3364*4882a593Smuzhiyun &req, sizeof(req), true);
3365*4882a593Smuzhiyun }
3366*4882a593Smuzhiyun
mt7915_mcu_set_txbf_sounding(struct mt7915_dev * dev)3367*4882a593Smuzhiyun int mt7915_mcu_set_txbf_sounding(struct mt7915_dev *dev)
3368*4882a593Smuzhiyun {
3369*4882a593Smuzhiyun #define MT_BF_PROCESSING 4
3370*4882a593Smuzhiyun struct {
3371*4882a593Smuzhiyun u8 action;
3372*4882a593Smuzhiyun u8 snd_mode;
3373*4882a593Smuzhiyun u8 sta_num;
3374*4882a593Smuzhiyun u8 rsv;
3375*4882a593Smuzhiyun u8 wlan_idx[4];
3376*4882a593Smuzhiyun __le32 snd_period; /* ms */
3377*4882a593Smuzhiyun } __packed req = {
3378*4882a593Smuzhiyun .action = true,
3379*4882a593Smuzhiyun .snd_mode = MT_BF_PROCESSING,
3380*4882a593Smuzhiyun };
3381*4882a593Smuzhiyun
3382*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_TXBF_ACTION,
3383*4882a593Smuzhiyun &req, sizeof(req), true);
3384*4882a593Smuzhiyun }
3385*4882a593Smuzhiyun
mt7915_mcu_add_obss_spr(struct mt7915_dev * dev,struct ieee80211_vif * vif,bool enable)3386*4882a593Smuzhiyun int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif,
3387*4882a593Smuzhiyun bool enable)
3388*4882a593Smuzhiyun {
3389*4882a593Smuzhiyun #define MT_SPR_ENABLE 1
3390*4882a593Smuzhiyun struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
3391*4882a593Smuzhiyun struct {
3392*4882a593Smuzhiyun u8 action;
3393*4882a593Smuzhiyun u8 arg_num;
3394*4882a593Smuzhiyun u8 band_idx;
3395*4882a593Smuzhiyun u8 status;
3396*4882a593Smuzhiyun u8 drop_tx_idx;
3397*4882a593Smuzhiyun u8 sta_idx; /* 256 sta */
3398*4882a593Smuzhiyun u8 rsv[2];
3399*4882a593Smuzhiyun __le32 val;
3400*4882a593Smuzhiyun } __packed req = {
3401*4882a593Smuzhiyun .action = MT_SPR_ENABLE,
3402*4882a593Smuzhiyun .arg_num = 1,
3403*4882a593Smuzhiyun .band_idx = mvif->band_idx,
3404*4882a593Smuzhiyun .val = cpu_to_le32(enable),
3405*4882a593Smuzhiyun };
3406*4882a593Smuzhiyun
3407*4882a593Smuzhiyun return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_SPR,
3408*4882a593Smuzhiyun &req, sizeof(req), true);
3409*4882a593Smuzhiyun }
3410