1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /* Copyright (C) 2020 MediaTek Inc. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include "mt7915.h"
5*4882a593Smuzhiyun #include "eeprom.h"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /** global debugfs **/
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* test knob of system layer 1/2 error recovery */
mt7915_ser_trigger_set(void * data,u64 val)10*4882a593Smuzhiyun static int mt7915_ser_trigger_set(void *data, u64 val)
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun enum {
13*4882a593Smuzhiyun SER_SET_RECOVER_L1 = 1,
14*4882a593Smuzhiyun SER_SET_RECOVER_L2,
15*4882a593Smuzhiyun SER_ENABLE = 2,
16*4882a593Smuzhiyun SER_RECOVER
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun struct mt7915_dev *dev = data;
19*4882a593Smuzhiyun int ret = 0;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun switch (val) {
22*4882a593Smuzhiyun case SER_SET_RECOVER_L1:
23*4882a593Smuzhiyun case SER_SET_RECOVER_L2:
24*4882a593Smuzhiyun ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0);
25*4882a593Smuzhiyun if (ret)
26*4882a593Smuzhiyun return ret;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return mt7915_mcu_set_ser(dev, SER_RECOVER, val, 0);
29*4882a593Smuzhiyun default:
30*4882a593Smuzhiyun break;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return ret;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL,
37*4882a593Smuzhiyun mt7915_ser_trigger_set, "%lld\n");
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static int
mt7915_radar_trigger(void * data,u64 val)40*4882a593Smuzhiyun mt7915_radar_trigger(void *data, u64 val)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct mt7915_dev *dev = data;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return mt7915_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 1, 0, 0);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL,
48*4882a593Smuzhiyun mt7915_radar_trigger, "%lld\n");
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static int
mt7915_dbdc_set(void * data,u64 val)51*4882a593Smuzhiyun mt7915_dbdc_set(void *data, u64 val)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct mt7915_dev *dev = data;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (val)
56*4882a593Smuzhiyun mt7915_register_ext_phy(dev);
57*4882a593Smuzhiyun else
58*4882a593Smuzhiyun mt7915_unregister_ext_phy(dev);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static int
mt7915_dbdc_get(void * data,u64 * val)64*4882a593Smuzhiyun mt7915_dbdc_get(void *data, u64 *val)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct mt7915_dev *dev = data;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun *val = !!mt7915_ext_phy(dev);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(fops_dbdc, mt7915_dbdc_get,
74*4882a593Smuzhiyun mt7915_dbdc_set, "%lld\n");
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static int
mt7915_fw_debug_set(void * data,u64 val)77*4882a593Smuzhiyun mt7915_fw_debug_set(void *data, u64 val)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct mt7915_dev *dev = data;
80*4882a593Smuzhiyun enum {
81*4882a593Smuzhiyun DEBUG_TXCMD = 62,
82*4882a593Smuzhiyun DEBUG_CMD_RPT_TX,
83*4882a593Smuzhiyun DEBUG_CMD_RPT_TRIG,
84*4882a593Smuzhiyun DEBUG_SPL,
85*4882a593Smuzhiyun DEBUG_RPT_RX,
86*4882a593Smuzhiyun } debug;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun dev->fw_debug = !!val;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun mt7915_mcu_fw_log_2_host(dev, dev->fw_debug ? 2 : 0);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++)
93*4882a593Smuzhiyun mt7915_mcu_fw_dbg_ctrl(dev, debug, dev->fw_debug);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static int
mt7915_fw_debug_get(void * data,u64 * val)99*4882a593Smuzhiyun mt7915_fw_debug_get(void *data, u64 *val)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct mt7915_dev *dev = data;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun *val = dev->fw_debug;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug, mt7915_fw_debug_get,
109*4882a593Smuzhiyun mt7915_fw_debug_set, "%lld\n");
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static void
mt7915_ampdu_stat_read_phy(struct mt7915_phy * phy,struct seq_file * file)112*4882a593Smuzhiyun mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy,
113*4882a593Smuzhiyun struct seq_file *file)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct mt7915_dev *dev = file->private;
116*4882a593Smuzhiyun bool ext_phy = phy != &dev->phy;
117*4882a593Smuzhiyun int bound[15], range[4], i, n;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (!phy)
120*4882a593Smuzhiyun return;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* Tx ampdu stat */
123*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(range); i++)
124*4882a593Smuzhiyun range[i] = mt76_rr(dev, MT_MIB_ARNG(ext_phy, i));
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bound); i++)
127*4882a593Smuzhiyun bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun seq_printf(file, "\nPhy %d\n", ext_phy);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun seq_printf(file, "Length: %8d | ", bound[0]);
132*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bound) - 1; i++)
133*4882a593Smuzhiyun seq_printf(file, "%3d -%3d | ",
134*4882a593Smuzhiyun bound[i] + 1, bound[i + 1]);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun seq_puts(file, "\nCount: ");
137*4882a593Smuzhiyun n = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
138*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bound); i++)
139*4882a593Smuzhiyun seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + n]);
140*4882a593Smuzhiyun seq_puts(file, "\n");
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static void
mt7915_txbf_stat_read_phy(struct mt7915_phy * phy,struct seq_file * s)146*4882a593Smuzhiyun mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun struct mt7915_dev *dev = s->private;
149*4882a593Smuzhiyun bool ext_phy = phy != &dev->phy;
150*4882a593Smuzhiyun int cnt;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun if (!phy)
153*4882a593Smuzhiyun return;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* Tx Beamformer monitor */
156*4882a593Smuzhiyun seq_puts(s, "\nTx Beamformer applied PPDU counts: ");
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(ext_phy));
159*4882a593Smuzhiyun seq_printf(s, "iBF: %ld, eBF: %ld\n",
160*4882a593Smuzhiyun FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt),
161*4882a593Smuzhiyun FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt));
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /* Tx Beamformer Rx feedback monitor */
164*4882a593Smuzhiyun seq_puts(s, "Tx Beamformer Rx feedback statistics: ");
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(ext_phy));
167*4882a593Smuzhiyun seq_printf(s, "All: %ld, HE: %ld, VHT: %ld, HT: %ld\n",
168*4882a593Smuzhiyun FIELD_GET(MT_ETBF_RX_FB_ALL, cnt),
169*4882a593Smuzhiyun FIELD_GET(MT_ETBF_RX_FB_HE, cnt),
170*4882a593Smuzhiyun FIELD_GET(MT_ETBF_RX_FB_VHT, cnt),
171*4882a593Smuzhiyun FIELD_GET(MT_ETBF_RX_FB_HT, cnt));
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /* Tx Beamformee Rx NDPA & Tx feedback report */
174*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(ext_phy));
175*4882a593Smuzhiyun seq_printf(s, "Tx Beamformee successful feedback frames: %ld\n",
176*4882a593Smuzhiyun FIELD_GET(MT_ETBF_TX_FB_CPL, cnt));
177*4882a593Smuzhiyun seq_printf(s, "Tx Beamformee feedback triggered counts: %ld\n",
178*4882a593Smuzhiyun FIELD_GET(MT_ETBF_TX_FB_TRI, cnt));
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* Tx SU & MU counters */
181*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_MIB_SDR34(ext_phy));
182*4882a593Smuzhiyun seq_printf(s, "Tx multi-user Beamforming counts: %ld\n",
183*4882a593Smuzhiyun FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt));
184*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_MIB_DR8(ext_phy));
185*4882a593Smuzhiyun seq_printf(s, "Tx multi-user MPDU counts: %d\n", cnt);
186*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_MIB_DR9(ext_phy));
187*4882a593Smuzhiyun seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", cnt);
188*4882a593Smuzhiyun cnt = mt76_rr(dev, MT_MIB_DR11(ext_phy));
189*4882a593Smuzhiyun seq_printf(s, "Tx single-user successful MPDU counts: %d\n", cnt);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun seq_puts(s, "\n");
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static int
mt7915_tx_stats_read(struct seq_file * file,void * data)195*4882a593Smuzhiyun mt7915_tx_stats_read(struct seq_file *file, void *data)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun struct mt7915_dev *dev = file->private;
198*4882a593Smuzhiyun int stat[8], i, n;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun mt7915_ampdu_stat_read_phy(&dev->phy, file);
201*4882a593Smuzhiyun mt7915_txbf_stat_read_phy(&dev->phy, file);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun mt7915_ampdu_stat_read_phy(mt7915_ext_phy(dev), file);
204*4882a593Smuzhiyun mt7915_txbf_stat_read_phy(mt7915_ext_phy(dev), file);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* Tx amsdu info */
207*4882a593Smuzhiyun seq_puts(file, "Tx MSDU stat:\n");
208*4882a593Smuzhiyun for (i = 0, n = 0; i < ARRAY_SIZE(stat); i++) {
209*4882a593Smuzhiyun stat[i] = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
210*4882a593Smuzhiyun n += stat[i];
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(stat); i++) {
214*4882a593Smuzhiyun seq_printf(file, "AMSDU pack count of %d MSDU in TXD: 0x%x ",
215*4882a593Smuzhiyun i + 1, stat[i]);
216*4882a593Smuzhiyun if (n != 0)
217*4882a593Smuzhiyun seq_printf(file, "(%d%%)\n", stat[i] * 100 / n);
218*4882a593Smuzhiyun else
219*4882a593Smuzhiyun seq_puts(file, "\n");
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static int
mt7915_tx_stats_open(struct inode * inode,struct file * f)226*4882a593Smuzhiyun mt7915_tx_stats_open(struct inode *inode, struct file *f)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun return single_open(f, mt7915_tx_stats_read, inode->i_private);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const struct file_operations fops_tx_stats = {
232*4882a593Smuzhiyun .open = mt7915_tx_stats_open,
233*4882a593Smuzhiyun .read = seq_read,
234*4882a593Smuzhiyun .llseek = seq_lseek,
235*4882a593Smuzhiyun .release = single_release,
236*4882a593Smuzhiyun .owner = THIS_MODULE,
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
mt7915_read_temperature(struct seq_file * s,void * data)239*4882a593Smuzhiyun static int mt7915_read_temperature(struct seq_file *s, void *data)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun struct mt7915_dev *dev = dev_get_drvdata(s->private);
242*4882a593Smuzhiyun int temp;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* cpu */
245*4882a593Smuzhiyun temp = mt7915_mcu_get_temperature(dev, 0);
246*4882a593Smuzhiyun seq_printf(s, "Temperature: %d\n", temp);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun return 0;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun static int
mt7915_queues_acq(struct seq_file * s,void * data)252*4882a593Smuzhiyun mt7915_queues_acq(struct seq_file *s, void *data)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct mt7915_dev *dev = dev_get_drvdata(s->private);
255*4882a593Smuzhiyun int i;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun for (i = 0; i < 16; i++) {
258*4882a593Smuzhiyun int j, acs = i / 4, index = i % 4;
259*4882a593Smuzhiyun u32 ctrl, val, qlen = 0;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, index));
262*4882a593Smuzhiyun ctrl = BIT(31) | BIT(15) | (acs << 8);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun for (j = 0; j < 32; j++) {
265*4882a593Smuzhiyun if (val & BIT(j))
266*4882a593Smuzhiyun continue;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun mt76_wr(dev, MT_PLE_FL_Q0_CTRL,
269*4882a593Smuzhiyun ctrl | (j + (index << 5)));
270*4882a593Smuzhiyun qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL,
271*4882a593Smuzhiyun GENMASK(11, 0));
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun seq_printf(s, "AC%d%d: queued=%d\n", acs, index, qlen);
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun return 0;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static int
mt7915_queues_read(struct seq_file * s,void * data)280*4882a593Smuzhiyun mt7915_queues_read(struct seq_file *s, void *data)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun struct mt7915_dev *dev = dev_get_drvdata(s->private);
283*4882a593Smuzhiyun static const struct {
284*4882a593Smuzhiyun char *queue;
285*4882a593Smuzhiyun int id;
286*4882a593Smuzhiyun } queue_map[] = {
287*4882a593Smuzhiyun { "WFDMA0", MT_TXQ_BE },
288*4882a593Smuzhiyun { "MCUWM", MT_TXQ_MCU },
289*4882a593Smuzhiyun { "MCUWA", MT_TXQ_MCU_WA },
290*4882a593Smuzhiyun { "MCUFWQ", MT_TXQ_FWDL },
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun int i;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(queue_map); i++) {
295*4882a593Smuzhiyun struct mt76_queue *q = dev->mt76.q_tx[queue_map[i].id];
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (!q)
298*4882a593Smuzhiyun continue;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun seq_printf(s,
301*4882a593Smuzhiyun "%s: queued=%d head=%d tail=%d\n",
302*4882a593Smuzhiyun queue_map[i].queue, q->queued, q->head,
303*4882a593Smuzhiyun q->tail);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun return 0;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun static void
mt7915_puts_rate_txpower(struct seq_file * s,s8 * delta,s8 txpower_cur,int band)310*4882a593Smuzhiyun mt7915_puts_rate_txpower(struct seq_file *s, s8 *delta,
311*4882a593Smuzhiyun s8 txpower_cur, int band)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun static const char * const sku_group_name[] = {
314*4882a593Smuzhiyun "CCK", "OFDM", "HT20", "HT40",
315*4882a593Smuzhiyun "VHT20", "VHT40", "VHT80", "VHT160",
316*4882a593Smuzhiyun "RU26", "RU52", "RU106", "RU242/SU20",
317*4882a593Smuzhiyun "RU484/SU40", "RU996/SU80", "RU2x996/SU160"
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun s8 txpower[MT7915_SKU_RATE_NUM];
320*4882a593Smuzhiyun int i, idx = 0;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun for (i = 0; i < MT7915_SKU_RATE_NUM; i++)
323*4882a593Smuzhiyun txpower[i] = DIV_ROUND_UP(txpower_cur + delta[i], 2);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun for (i = 0; i < MAX_SKU_RATE_GROUP_NUM; i++) {
326*4882a593Smuzhiyun const struct sku_group *sku = &mt7915_sku_groups[i];
327*4882a593Smuzhiyun u32 offset = sku->offset[band];
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if (!offset) {
330*4882a593Smuzhiyun idx += sku->len;
331*4882a593Smuzhiyun continue;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun mt76_seq_puts_array(s, sku_group_name[i],
335*4882a593Smuzhiyun txpower + idx, sku->len);
336*4882a593Smuzhiyun idx += sku->len;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static int
mt7915_read_rate_txpower(struct seq_file * s,void * data)341*4882a593Smuzhiyun mt7915_read_rate_txpower(struct seq_file *s, void *data)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun struct mt7915_dev *dev = dev_get_drvdata(s->private);
344*4882a593Smuzhiyun struct mt76_phy *mphy = &dev->mphy;
345*4882a593Smuzhiyun enum nl80211_band band = mphy->chandef.chan->band;
346*4882a593Smuzhiyun s8 *delta = dev->rate_power[band];
347*4882a593Smuzhiyun s8 txpower_base = mphy->txpower_cur - delta[MT7915_SKU_MAX_DELTA_IDX];
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun seq_puts(s, "Band 0:\n");
350*4882a593Smuzhiyun mt7915_puts_rate_txpower(s, delta, txpower_base, band);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun if (dev->mt76.phy2) {
353*4882a593Smuzhiyun mphy = dev->mt76.phy2;
354*4882a593Smuzhiyun band = mphy->chandef.chan->band;
355*4882a593Smuzhiyun delta = dev->rate_power[band];
356*4882a593Smuzhiyun txpower_base = mphy->txpower_cur -
357*4882a593Smuzhiyun delta[MT7915_SKU_MAX_DELTA_IDX];
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun seq_puts(s, "Band 1:\n");
360*4882a593Smuzhiyun mt7915_puts_rate_txpower(s, delta, txpower_base, band);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
mt7915_init_debugfs(struct mt7915_dev * dev)366*4882a593Smuzhiyun int mt7915_init_debugfs(struct mt7915_dev *dev)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun struct dentry *dir;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun dir = mt76_register_debugfs(&dev->mt76);
371*4882a593Smuzhiyun if (!dir)
372*4882a593Smuzhiyun return -ENOMEM;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun debugfs_create_devm_seqfile(dev->mt76.dev, "queues", dir,
375*4882a593Smuzhiyun mt7915_queues_read);
376*4882a593Smuzhiyun debugfs_create_devm_seqfile(dev->mt76.dev, "acq", dir,
377*4882a593Smuzhiyun mt7915_queues_acq);
378*4882a593Smuzhiyun debugfs_create_file("tx_stats", 0400, dir, dev, &fops_tx_stats);
379*4882a593Smuzhiyun debugfs_create_file("dbdc", 0600, dir, dev, &fops_dbdc);
380*4882a593Smuzhiyun debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug);
381*4882a593Smuzhiyun debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern);
382*4882a593Smuzhiyun /* test knobs */
383*4882a593Smuzhiyun debugfs_create_file("radar_trigger", 0200, dir, dev,
384*4882a593Smuzhiyun &fops_radar_trigger);
385*4882a593Smuzhiyun debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger);
386*4882a593Smuzhiyun debugfs_create_devm_seqfile(dev->mt76.dev, "temperature", dir,
387*4882a593Smuzhiyun mt7915_read_temperature);
388*4882a593Smuzhiyun debugfs_create_devm_seqfile(dev->mt76.dev, "txpower_sku", dir,
389*4882a593Smuzhiyun mt7915_read_rate_txpower);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun return 0;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun #ifdef CONFIG_MAC80211_DEBUGFS
395*4882a593Smuzhiyun /** per-station debugfs **/
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun /* usage: <tx mode> <ldpc> <stbc> <bw> <gi> <nss> <mcs> */
mt7915_sta_fixed_rate_set(void * data,u64 rate)398*4882a593Smuzhiyun static int mt7915_sta_fixed_rate_set(void *data, u64 rate)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun struct ieee80211_sta *sta = data;
401*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun return mt7915_mcu_set_fixed_rate(msta->vif->phy->dev, sta, rate);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(fops_fixed_rate, NULL,
407*4882a593Smuzhiyun mt7915_sta_fixed_rate_set, "%llx\n");
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun static int
mt7915_sta_stats_read(struct seq_file * s,void * data)410*4882a593Smuzhiyun mt7915_sta_stats_read(struct seq_file *s, void *data)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun struct ieee80211_sta *sta = s->private;
413*4882a593Smuzhiyun struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
414*4882a593Smuzhiyun struct mt7915_sta_stats *stats = &msta->stats;
415*4882a593Smuzhiyun struct rate_info *rate = &stats->prob_rate;
416*4882a593Smuzhiyun static const char * const bw[] = {
417*4882a593Smuzhiyun "BW20", "BW5", "BW10", "BW40",
418*4882a593Smuzhiyun "BW80", "BW160", "BW_HE_RU"
419*4882a593Smuzhiyun };
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (!rate->legacy && !rate->flags)
422*4882a593Smuzhiyun return 0;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun seq_puts(s, "Probing rate - ");
425*4882a593Smuzhiyun if (rate->flags & RATE_INFO_FLAGS_MCS)
426*4882a593Smuzhiyun seq_puts(s, "HT ");
427*4882a593Smuzhiyun else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
428*4882a593Smuzhiyun seq_puts(s, "VHT ");
429*4882a593Smuzhiyun else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
430*4882a593Smuzhiyun seq_puts(s, "HE ");
431*4882a593Smuzhiyun else
432*4882a593Smuzhiyun seq_printf(s, "Bitrate %d\n", rate->legacy);
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun if (rate->flags) {
435*4882a593Smuzhiyun seq_printf(s, "%s NSS%d MCS%d ",
436*4882a593Smuzhiyun bw[rate->bw], rate->nss, rate->mcs);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun if (rate->flags & RATE_INFO_FLAGS_SHORT_GI)
439*4882a593Smuzhiyun seq_puts(s, "SGI ");
440*4882a593Smuzhiyun else if (rate->he_gi)
441*4882a593Smuzhiyun seq_puts(s, "HE GI ");
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun if (rate->he_dcm)
444*4882a593Smuzhiyun seq_puts(s, "DCM ");
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun seq_printf(s, "\nPPDU PER: %ld.%1ld%%\n",
448*4882a593Smuzhiyun stats->per / 10, stats->per % 10);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun return 0;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun static int
mt7915_sta_stats_open(struct inode * inode,struct file * f)454*4882a593Smuzhiyun mt7915_sta_stats_open(struct inode *inode, struct file *f)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun return single_open(f, mt7915_sta_stats_read, inode->i_private);
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun static const struct file_operations fops_sta_stats = {
460*4882a593Smuzhiyun .open = mt7915_sta_stats_open,
461*4882a593Smuzhiyun .read = seq_read,
462*4882a593Smuzhiyun .llseek = seq_lseek,
463*4882a593Smuzhiyun .release = single_release,
464*4882a593Smuzhiyun .owner = THIS_MODULE,
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun
mt7915_sta_add_debugfs(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct dentry * dir)467*4882a593Smuzhiyun void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
468*4882a593Smuzhiyun struct ieee80211_sta *sta, struct dentry *dir)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);
471*4882a593Smuzhiyun debugfs_create_file("stats", 0400, dir, sta, &fops_sta_stats);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun #endif
474