1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MT76x2_MCU_H 7*4882a593Smuzhiyun #define __MT76x2_MCU_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "../mt76x02_mcu.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Register definitions */ 12*4882a593Smuzhiyun #define MT_MCU_CPU_CTL 0x0704 13*4882a593Smuzhiyun #define MT_MCU_CLOCK_CTL 0x0708 14*4882a593Smuzhiyun #define MT_MCU_PCIE_REMAP_BASE1 0x0740 15*4882a593Smuzhiyun #define MT_MCU_PCIE_REMAP_BASE2 0x0744 16*4882a593Smuzhiyun #define MT_MCU_PCIE_REMAP_BASE3 0x0748 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MT_MCU_ROM_PATCH_OFFSET 0x80000 19*4882a593Smuzhiyun #define MT_MCU_ROM_PATCH_ADDR 0x90000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MT_MCU_ILM_OFFSET 0x80000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MT_MCU_DLM_OFFSET 0x100000 24*4882a593Smuzhiyun #define MT_MCU_DLM_ADDR 0x90000 25*4882a593Smuzhiyun #define MT_MCU_DLM_ADDR_E3 0x90800 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun enum mcu_calibration { 28*4882a593Smuzhiyun MCU_CAL_R = 1, 29*4882a593Smuzhiyun MCU_CAL_TEMP_SENSOR, 30*4882a593Smuzhiyun MCU_CAL_RXDCOC, 31*4882a593Smuzhiyun MCU_CAL_RC, 32*4882a593Smuzhiyun MCU_CAL_SX_LOGEN, 33*4882a593Smuzhiyun MCU_CAL_LC, 34*4882a593Smuzhiyun MCU_CAL_TX_LOFT, 35*4882a593Smuzhiyun MCU_CAL_TXIQ, 36*4882a593Smuzhiyun MCU_CAL_TSSI, 37*4882a593Smuzhiyun MCU_CAL_TSSI_COMP, 38*4882a593Smuzhiyun MCU_CAL_DPD, 39*4882a593Smuzhiyun MCU_CAL_RXIQC_FI, 40*4882a593Smuzhiyun MCU_CAL_RXIQC_FD, 41*4882a593Smuzhiyun MCU_CAL_PWRON, 42*4882a593Smuzhiyun MCU_CAL_TX_SHAPING, 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum mt76x2_mcu_cr_mode { 46*4882a593Smuzhiyun MT_RF_CR, 47*4882a593Smuzhiyun MT_BBP_CR, 48*4882a593Smuzhiyun MT_RF_BBP_CR, 49*4882a593Smuzhiyun MT_HL_TEMP_CR_UPDATE, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct mt76x2_tssi_comp { 53*4882a593Smuzhiyun u8 pa_mode; 54*4882a593Smuzhiyun u8 cal_mode; 55*4882a593Smuzhiyun u16 pad; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun u8 slope0; 58*4882a593Smuzhiyun u8 slope1; 59*4882a593Smuzhiyun u8 offset0; 60*4882a593Smuzhiyun u8 offset1; 61*4882a593Smuzhiyun } __packed __aligned(4); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun int mt76x2_mcu_tssi_comp(struct mt76x02_dev *dev, 64*4882a593Smuzhiyun struct mt76x2_tssi_comp *tssi_data); 65*4882a593Smuzhiyun int mt76x2_mcu_init_gain(struct mt76x02_dev *dev, u8 channel, u32 gain, 66*4882a593Smuzhiyun bool force); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69