1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
4*4882a593Smuzhiyun * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include "mt76x02.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define CCK_RATE(_idx, _rate) { \
11*4882a593Smuzhiyun .bitrate = _rate, \
12*4882a593Smuzhiyun .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
13*4882a593Smuzhiyun .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
14*4882a593Smuzhiyun .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + (_idx)), \
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define OFDM_RATE(_idx, _rate) { \
18*4882a593Smuzhiyun .bitrate = _rate, \
19*4882a593Smuzhiyun .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
20*4882a593Smuzhiyun .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct ieee80211_rate mt76x02_rates[] = {
24*4882a593Smuzhiyun CCK_RATE(0, 10),
25*4882a593Smuzhiyun CCK_RATE(1, 20),
26*4882a593Smuzhiyun CCK_RATE(2, 55),
27*4882a593Smuzhiyun CCK_RATE(3, 110),
28*4882a593Smuzhiyun OFDM_RATE(0, 60),
29*4882a593Smuzhiyun OFDM_RATE(1, 90),
30*4882a593Smuzhiyun OFDM_RATE(2, 120),
31*4882a593Smuzhiyun OFDM_RATE(3, 180),
32*4882a593Smuzhiyun OFDM_RATE(4, 240),
33*4882a593Smuzhiyun OFDM_RATE(5, 360),
34*4882a593Smuzhiyun OFDM_RATE(6, 480),
35*4882a593Smuzhiyun OFDM_RATE(7, 540),
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_rates);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const struct ieee80211_iface_limit mt76x02_if_limits[] = {
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun .max = 1,
42*4882a593Smuzhiyun .types = BIT(NL80211_IFTYPE_ADHOC)
43*4882a593Smuzhiyun }, {
44*4882a593Smuzhiyun .max = 8,
45*4882a593Smuzhiyun .types = BIT(NL80211_IFTYPE_STATION) |
46*4882a593Smuzhiyun #ifdef CONFIG_MAC80211_MESH
47*4882a593Smuzhiyun BIT(NL80211_IFTYPE_MESH_POINT) |
48*4882a593Smuzhiyun #endif
49*4882a593Smuzhiyun BIT(NL80211_IFTYPE_P2P_CLIENT) |
50*4882a593Smuzhiyun BIT(NL80211_IFTYPE_P2P_GO) |
51*4882a593Smuzhiyun BIT(NL80211_IFTYPE_AP)
52*4882a593Smuzhiyun },
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const struct ieee80211_iface_limit mt76x02u_if_limits[] = {
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun .max = 1,
58*4882a593Smuzhiyun .types = BIT(NL80211_IFTYPE_ADHOC)
59*4882a593Smuzhiyun }, {
60*4882a593Smuzhiyun .max = 2,
61*4882a593Smuzhiyun .types = BIT(NL80211_IFTYPE_STATION) |
62*4882a593Smuzhiyun #ifdef CONFIG_MAC80211_MESH
63*4882a593Smuzhiyun BIT(NL80211_IFTYPE_MESH_POINT) |
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun BIT(NL80211_IFTYPE_P2P_CLIENT) |
66*4882a593Smuzhiyun BIT(NL80211_IFTYPE_P2P_GO) |
67*4882a593Smuzhiyun BIT(NL80211_IFTYPE_AP)
68*4882a593Smuzhiyun },
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct ieee80211_iface_combination mt76x02_if_comb[] = {
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun .limits = mt76x02_if_limits,
74*4882a593Smuzhiyun .n_limits = ARRAY_SIZE(mt76x02_if_limits),
75*4882a593Smuzhiyun .max_interfaces = 8,
76*4882a593Smuzhiyun .num_different_channels = 1,
77*4882a593Smuzhiyun .beacon_int_infra_match = true,
78*4882a593Smuzhiyun .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
79*4882a593Smuzhiyun BIT(NL80211_CHAN_WIDTH_20) |
80*4882a593Smuzhiyun BIT(NL80211_CHAN_WIDTH_40) |
81*4882a593Smuzhiyun BIT(NL80211_CHAN_WIDTH_80),
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct ieee80211_iface_combination mt76x02u_if_comb[] = {
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun .limits = mt76x02u_if_limits,
88*4882a593Smuzhiyun .n_limits = ARRAY_SIZE(mt76x02u_if_limits),
89*4882a593Smuzhiyun .max_interfaces = 2,
90*4882a593Smuzhiyun .num_different_channels = 1,
91*4882a593Smuzhiyun .beacon_int_infra_match = true,
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static void
mt76x02_led_set_config(struct mt76_dev * mdev,u8 delay_on,u8 delay_off)96*4882a593Smuzhiyun mt76x02_led_set_config(struct mt76_dev *mdev, u8 delay_on,
97*4882a593Smuzhiyun u8 delay_off)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev,
100*4882a593Smuzhiyun mt76);
101*4882a593Smuzhiyun u32 val;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xff) |
104*4882a593Smuzhiyun FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
105*4882a593Smuzhiyun FIELD_PREP(MT_LED_STATUS_ON, delay_on);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun mt76_wr(dev, MT_LED_S0(mdev->led_pin), val);
108*4882a593Smuzhiyun mt76_wr(dev, MT_LED_S1(mdev->led_pin), val);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun val = MT_LED_CTRL_REPLAY(mdev->led_pin) |
111*4882a593Smuzhiyun MT_LED_CTRL_KICK(mdev->led_pin);
112*4882a593Smuzhiyun if (mdev->led_al)
113*4882a593Smuzhiyun val |= MT_LED_CTRL_POLARITY(mdev->led_pin);
114*4882a593Smuzhiyun mt76_wr(dev, MT_LED_CTRL, val);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static int
mt76x02_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)118*4882a593Smuzhiyun mt76x02_led_set_blink(struct led_classdev *led_cdev,
119*4882a593Smuzhiyun unsigned long *delay_on,
120*4882a593Smuzhiyun unsigned long *delay_off)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct mt76_dev *mdev = container_of(led_cdev, struct mt76_dev,
123*4882a593Smuzhiyun led_cdev);
124*4882a593Smuzhiyun u8 delta_on, delta_off;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun delta_off = max_t(u8, *delay_off / 10, 1);
127*4882a593Smuzhiyun delta_on = max_t(u8, *delay_on / 10, 1);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun mt76x02_led_set_config(mdev, delta_on, delta_off);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun static void
mt76x02_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)135*4882a593Smuzhiyun mt76x02_led_set_brightness(struct led_classdev *led_cdev,
136*4882a593Smuzhiyun enum led_brightness brightness)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct mt76_dev *mdev = container_of(led_cdev, struct mt76_dev,
139*4882a593Smuzhiyun led_cdev);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if (!brightness)
142*4882a593Smuzhiyun mt76x02_led_set_config(mdev, 0, 0xff);
143*4882a593Smuzhiyun else
144*4882a593Smuzhiyun mt76x02_led_set_config(mdev, 0xff, 0);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
mt76x02_init_device(struct mt76x02_dev * dev)147*4882a593Smuzhiyun void mt76x02_init_device(struct mt76x02_dev *dev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct ieee80211_hw *hw = mt76_hw(dev);
150*4882a593Smuzhiyun struct wiphy *wiphy = hw->wiphy;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun INIT_DELAYED_WORK(&dev->mt76.mac_work, mt76x02_mac_work);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun hw->queues = 4;
155*4882a593Smuzhiyun hw->max_rates = 1;
156*4882a593Smuzhiyun hw->max_report_rates = 7;
157*4882a593Smuzhiyun hw->max_rate_tries = 1;
158*4882a593Smuzhiyun hw->extra_tx_headroom = 2;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (mt76_is_usb(&dev->mt76)) {
161*4882a593Smuzhiyun hw->extra_tx_headroom += sizeof(struct mt76x02_txwi) +
162*4882a593Smuzhiyun MT_DMA_HDR_LEN;
163*4882a593Smuzhiyun wiphy->iface_combinations = mt76x02u_if_comb;
164*4882a593Smuzhiyun wiphy->n_iface_combinations = ARRAY_SIZE(mt76x02u_if_comb);
165*4882a593Smuzhiyun } else {
166*4882a593Smuzhiyun INIT_DELAYED_WORK(&dev->wdt_work, mt76x02_wdt_work);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun mt76x02_dfs_init_detector(dev);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun wiphy->reg_notifier = mt76x02_regd_notifier;
171*4882a593Smuzhiyun wiphy->iface_combinations = mt76x02_if_comb;
172*4882a593Smuzhiyun wiphy->n_iface_combinations = ARRAY_SIZE(mt76x02_if_comb);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* init led callbacks */
175*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_MT76_LEDS)) {
176*4882a593Smuzhiyun dev->mt76.led_cdev.brightness_set =
177*4882a593Smuzhiyun mt76x02_led_set_brightness;
178*4882a593Smuzhiyun dev->mt76.led_cdev.blink_set = mt76x02_led_set_blink;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun hw->sta_data_size = sizeof(struct mt76x02_sta);
185*4882a593Smuzhiyun hw->vif_data_size = sizeof(struct mt76x02_vif);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
188*4882a593Smuzhiyun ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun dev->mt76.global_wcid.idx = 255;
191*4882a593Smuzhiyun dev->mt76.global_wcid.hw_key_idx = -1;
192*4882a593Smuzhiyun dev->slottime = 9;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun if (is_mt76x2(dev)) {
195*4882a593Smuzhiyun dev->mphy.sband_2g.sband.ht_cap.cap |=
196*4882a593Smuzhiyun IEEE80211_HT_CAP_LDPC_CODING;
197*4882a593Smuzhiyun dev->mphy.sband_5g.sband.ht_cap.cap |=
198*4882a593Smuzhiyun IEEE80211_HT_CAP_LDPC_CODING;
199*4882a593Smuzhiyun dev->chainmask = 0x202;
200*4882a593Smuzhiyun dev->mphy.antenna_mask = 3;
201*4882a593Smuzhiyun } else {
202*4882a593Smuzhiyun dev->chainmask = 0x101;
203*4882a593Smuzhiyun dev->mphy.antenna_mask = 1;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_init_device);
207*4882a593Smuzhiyun
mt76x02_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)208*4882a593Smuzhiyun void mt76x02_configure_filter(struct ieee80211_hw *hw,
209*4882a593Smuzhiyun unsigned int changed_flags,
210*4882a593Smuzhiyun unsigned int *total_flags, u64 multicast)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
213*4882a593Smuzhiyun u32 flags = 0;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun #define MT76_FILTER(_flag, _hw) do { \
216*4882a593Smuzhiyun flags |= *total_flags & FIF_##_flag; \
217*4882a593Smuzhiyun dev->mt76.rxfilter &= ~(_hw); \
218*4882a593Smuzhiyun dev->mt76.rxfilter |= !(flags & FIF_##_flag) * (_hw); \
219*4882a593Smuzhiyun } while (0)
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun mutex_lock(&dev->mt76.mutex);
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun dev->mt76.rxfilter &= ~MT_RX_FILTR_CFG_OTHER_BSS;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun MT76_FILTER(FCSFAIL, MT_RX_FILTR_CFG_CRC_ERR);
226*4882a593Smuzhiyun MT76_FILTER(PLCPFAIL, MT_RX_FILTR_CFG_PHY_ERR);
227*4882a593Smuzhiyun MT76_FILTER(CONTROL, MT_RX_FILTR_CFG_ACK |
228*4882a593Smuzhiyun MT_RX_FILTR_CFG_CTS |
229*4882a593Smuzhiyun MT_RX_FILTR_CFG_CFEND |
230*4882a593Smuzhiyun MT_RX_FILTR_CFG_CFACK |
231*4882a593Smuzhiyun MT_RX_FILTR_CFG_BA |
232*4882a593Smuzhiyun MT_RX_FILTR_CFG_CTRL_RSV);
233*4882a593Smuzhiyun MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun *total_flags = flags;
236*4882a593Smuzhiyun mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun mutex_unlock(&dev->mt76.mutex);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_configure_filter);
241*4882a593Smuzhiyun
mt76x02_sta_add(struct mt76_dev * mdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)242*4882a593Smuzhiyun int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
243*4882a593Smuzhiyun struct ieee80211_sta *sta)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
246*4882a593Smuzhiyun struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
247*4882a593Smuzhiyun struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
248*4882a593Smuzhiyun int idx = 0;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun memset(msta, 0, sizeof(*msta));
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT76x02_N_WCIDS);
253*4882a593Smuzhiyun if (idx < 0)
254*4882a593Smuzhiyun return -ENOSPC;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun msta->vif = mvif;
257*4882a593Smuzhiyun msta->wcid.sta = 1;
258*4882a593Smuzhiyun msta->wcid.idx = idx;
259*4882a593Smuzhiyun msta->wcid.hw_key_idx = -1;
260*4882a593Smuzhiyun mt76x02_mac_wcid_setup(dev, idx, mvif->idx, sta->addr);
261*4882a593Smuzhiyun mt76x02_mac_wcid_set_drop(dev, idx, false);
262*4882a593Smuzhiyun ewma_pktlen_init(&msta->pktlen);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_AP)
265*4882a593Smuzhiyun set_bit(MT_WCID_FLAG_CHECK_PS, &msta->wcid.flags);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return 0;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_sta_add);
270*4882a593Smuzhiyun
mt76x02_sta_remove(struct mt76_dev * mdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)271*4882a593Smuzhiyun void mt76x02_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
272*4882a593Smuzhiyun struct ieee80211_sta *sta)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
275*4882a593Smuzhiyun struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv;
276*4882a593Smuzhiyun int idx = wcid->idx;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun mt76x02_mac_wcid_set_drop(dev, idx, true);
279*4882a593Smuzhiyun mt76x02_mac_wcid_setup(dev, idx, 0, NULL);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_sta_remove);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun static void
mt76x02_vif_init(struct mt76x02_dev * dev,struct ieee80211_vif * vif,unsigned int idx)284*4882a593Smuzhiyun mt76x02_vif_init(struct mt76x02_dev *dev, struct ieee80211_vif *vif,
285*4882a593Smuzhiyun unsigned int idx)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
288*4882a593Smuzhiyun struct mt76_txq *mtxq;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun memset(mvif, 0, sizeof(*mvif));
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun mvif->idx = idx;
293*4882a593Smuzhiyun mvif->group_wcid.idx = MT_VIF_WCID(idx);
294*4882a593Smuzhiyun mvif->group_wcid.hw_key_idx = -1;
295*4882a593Smuzhiyun mtxq = (struct mt76_txq *)vif->txq->drv_priv;
296*4882a593Smuzhiyun mtxq->wcid = &mvif->group_wcid;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun int
mt76x02_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)300*4882a593Smuzhiyun mt76x02_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
303*4882a593Smuzhiyun unsigned int idx = 0;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* Allow to change address in HW if we create first interface. */
306*4882a593Smuzhiyun if (!dev->mphy.vif_mask &&
307*4882a593Smuzhiyun (((vif->addr[0] ^ dev->mt76.macaddr[0]) & ~GENMASK(4, 1)) ||
308*4882a593Smuzhiyun memcmp(vif->addr + 1, dev->mt76.macaddr + 1, ETH_ALEN - 1)))
309*4882a593Smuzhiyun mt76x02_mac_setaddr(dev, vif->addr);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun if (vif->addr[0] & BIT(1))
312*4882a593Smuzhiyun idx = 1 + (((dev->mt76.macaddr[0] ^ vif->addr[0]) >> 2) & 7);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /*
315*4882a593Smuzhiyun * Client mode typically only has one configurable BSSID register,
316*4882a593Smuzhiyun * which is used for bssidx=0. This is linked to the MAC address.
317*4882a593Smuzhiyun * Since mac80211 allows changing interface types, and we cannot
318*4882a593Smuzhiyun * force the use of the primary MAC address for a station mode
319*4882a593Smuzhiyun * interface, we need some other way of configuring a per-interface
320*4882a593Smuzhiyun * remote BSSID.
321*4882a593Smuzhiyun * The hardware provides an AP-Client feature, where bssidx 0-7 are
322*4882a593Smuzhiyun * used for AP mode and bssidx 8-15 for client mode.
323*4882a593Smuzhiyun * We shift the station interface bss index by 8 to force the
324*4882a593Smuzhiyun * hardware to recognize the BSSID.
325*4882a593Smuzhiyun * The resulting bssidx mismatch for unicast frames is ignored by hw.
326*4882a593Smuzhiyun */
327*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_STATION)
328*4882a593Smuzhiyun idx += 8;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* vif is already set or idx is 8 for AP/Mesh/... */
331*4882a593Smuzhiyun if (dev->mphy.vif_mask & BIT(idx) ||
332*4882a593Smuzhiyun (vif->type != NL80211_IFTYPE_STATION && idx > 7))
333*4882a593Smuzhiyun return -EBUSY;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun dev->mphy.vif_mask |= BIT(idx);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun mt76x02_vif_init(dev, vif, idx);
338*4882a593Smuzhiyun return 0;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_add_interface);
341*4882a593Smuzhiyun
mt76x02_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)342*4882a593Smuzhiyun void mt76x02_remove_interface(struct ieee80211_hw *hw,
343*4882a593Smuzhiyun struct ieee80211_vif *vif)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
346*4882a593Smuzhiyun struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun dev->mphy.vif_mask &= ~BIT(mvif->idx);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_remove_interface);
351*4882a593Smuzhiyun
mt76x02_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)352*4882a593Smuzhiyun int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
353*4882a593Smuzhiyun struct ieee80211_ampdu_params *params)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun enum ieee80211_ampdu_mlme_action action = params->action;
356*4882a593Smuzhiyun struct ieee80211_sta *sta = params->sta;
357*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
358*4882a593Smuzhiyun struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
359*4882a593Smuzhiyun struct ieee80211_txq *txq = sta->txq[params->tid];
360*4882a593Smuzhiyun u16 tid = params->tid;
361*4882a593Smuzhiyun u16 ssn = params->ssn;
362*4882a593Smuzhiyun struct mt76_txq *mtxq;
363*4882a593Smuzhiyun int ret = 0;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun if (!txq)
366*4882a593Smuzhiyun return -EINVAL;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun mtxq = (struct mt76_txq *)txq->drv_priv;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun mutex_lock(&dev->mt76.mutex);
371*4882a593Smuzhiyun switch (action) {
372*4882a593Smuzhiyun case IEEE80211_AMPDU_RX_START:
373*4882a593Smuzhiyun mt76_rx_aggr_start(&dev->mt76, &msta->wcid, tid,
374*4882a593Smuzhiyun ssn, params->buf_size);
375*4882a593Smuzhiyun mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid));
376*4882a593Smuzhiyun break;
377*4882a593Smuzhiyun case IEEE80211_AMPDU_RX_STOP:
378*4882a593Smuzhiyun mt76_rx_aggr_stop(&dev->mt76, &msta->wcid, tid);
379*4882a593Smuzhiyun mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx) + 4,
380*4882a593Smuzhiyun BIT(16 + tid));
381*4882a593Smuzhiyun break;
382*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_OPERATIONAL:
383*4882a593Smuzhiyun mtxq->aggr = true;
384*4882a593Smuzhiyun mtxq->send_bar = false;
385*4882a593Smuzhiyun ieee80211_send_bar(vif, sta->addr, tid, mtxq->agg_ssn);
386*4882a593Smuzhiyun break;
387*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_STOP_FLUSH:
388*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
389*4882a593Smuzhiyun mtxq->aggr = false;
390*4882a593Smuzhiyun break;
391*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_START:
392*4882a593Smuzhiyun mtxq->agg_ssn = IEEE80211_SN_TO_SEQ(ssn);
393*4882a593Smuzhiyun ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
394*4882a593Smuzhiyun break;
395*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_STOP_CONT:
396*4882a593Smuzhiyun mtxq->aggr = false;
397*4882a593Smuzhiyun ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
398*4882a593Smuzhiyun break;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun mutex_unlock(&dev->mt76.mutex);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun return ret;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_ampdu_action);
405*4882a593Smuzhiyun
mt76x02_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)406*4882a593Smuzhiyun int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
407*4882a593Smuzhiyun struct ieee80211_vif *vif, struct ieee80211_sta *sta,
408*4882a593Smuzhiyun struct ieee80211_key_conf *key)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
411*4882a593Smuzhiyun struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
412*4882a593Smuzhiyun struct mt76x02_sta *msta;
413*4882a593Smuzhiyun struct mt76_wcid *wcid;
414*4882a593Smuzhiyun int idx = key->keyidx;
415*4882a593Smuzhiyun int ret;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* fall back to sw encryption for unsupported ciphers */
418*4882a593Smuzhiyun switch (key->cipher) {
419*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
420*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
421*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
422*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
423*4882a593Smuzhiyun break;
424*4882a593Smuzhiyun default:
425*4882a593Smuzhiyun return -EOPNOTSUPP;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /*
429*4882a593Smuzhiyun * The hardware does not support per-STA RX GTK, fall back
430*4882a593Smuzhiyun * to software mode for these.
431*4882a593Smuzhiyun */
432*4882a593Smuzhiyun if ((vif->type == NL80211_IFTYPE_ADHOC ||
433*4882a593Smuzhiyun vif->type == NL80211_IFTYPE_MESH_POINT) &&
434*4882a593Smuzhiyun (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
435*4882a593Smuzhiyun key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
436*4882a593Smuzhiyun !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
437*4882a593Smuzhiyun return -EOPNOTSUPP;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun /*
440*4882a593Smuzhiyun * In USB AP mode, broadcast/multicast frames are setup in beacon
441*4882a593Smuzhiyun * data registers and sent via HW beacons engine, they require to
442*4882a593Smuzhiyun * be already encrypted.
443*4882a593Smuzhiyun */
444*4882a593Smuzhiyun if (mt76_is_usb(&dev->mt76) &&
445*4882a593Smuzhiyun vif->type == NL80211_IFTYPE_AP &&
446*4882a593Smuzhiyun !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
447*4882a593Smuzhiyun return -EOPNOTSUPP;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* MT76x0 GTK offloading does not work with more than one VIF */
450*4882a593Smuzhiyun if (is_mt76x0(dev) && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
451*4882a593Smuzhiyun return -EOPNOTSUPP;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun msta = sta ? (struct mt76x02_sta *)sta->drv_priv : NULL;
454*4882a593Smuzhiyun wcid = msta ? &msta->wcid : &mvif->group_wcid;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun if (cmd == SET_KEY) {
457*4882a593Smuzhiyun key->hw_key_idx = wcid->idx;
458*4882a593Smuzhiyun wcid->hw_key_idx = idx;
459*4882a593Smuzhiyun if (key->flags & IEEE80211_KEY_FLAG_RX_MGMT) {
460*4882a593Smuzhiyun key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
461*4882a593Smuzhiyun wcid->sw_iv = true;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun } else {
464*4882a593Smuzhiyun if (idx == wcid->hw_key_idx) {
465*4882a593Smuzhiyun wcid->hw_key_idx = -1;
466*4882a593Smuzhiyun wcid->sw_iv = false;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun key = NULL;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun mt76_wcid_key_setup(&dev->mt76, wcid, key);
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun if (!msta) {
474*4882a593Smuzhiyun if (key || wcid->hw_key_idx == idx) {
475*4882a593Smuzhiyun ret = mt76x02_mac_wcid_set_key(dev, wcid->idx, key);
476*4882a593Smuzhiyun if (ret)
477*4882a593Smuzhiyun return ret;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun return mt76x02_mac_shared_key_setup(dev, mvif->idx, idx, key);
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun return mt76x02_mac_wcid_set_key(dev, msta->wcid.idx, key);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_set_key);
486*4882a593Smuzhiyun
mt76x02_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)487*4882a593Smuzhiyun int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
488*4882a593Smuzhiyun u16 queue, const struct ieee80211_tx_queue_params *params)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
491*4882a593Smuzhiyun u8 cw_min = 5, cw_max = 10, qid;
492*4882a593Smuzhiyun u32 val;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun qid = dev->mt76.q_tx[queue]->hw_idx;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun if (params->cw_min)
497*4882a593Smuzhiyun cw_min = fls(params->cw_min);
498*4882a593Smuzhiyun if (params->cw_max)
499*4882a593Smuzhiyun cw_max = fls(params->cw_max);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun val = FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop) |
502*4882a593Smuzhiyun FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) |
503*4882a593Smuzhiyun FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) |
504*4882a593Smuzhiyun FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max);
505*4882a593Smuzhiyun mt76_wr(dev, MT_EDCA_CFG_AC(qid), val);
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_TXOP(qid));
508*4882a593Smuzhiyun val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(qid));
509*4882a593Smuzhiyun val |= params->txop << MT_WMM_TXOP_SHIFT(qid);
510*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_TXOP(qid), val);
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_AIFSN);
513*4882a593Smuzhiyun val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(qid));
514*4882a593Smuzhiyun val |= params->aifs << MT_WMM_AIFSN_SHIFT(qid);
515*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_AIFSN, val);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_CWMIN);
518*4882a593Smuzhiyun val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(qid));
519*4882a593Smuzhiyun val |= cw_min << MT_WMM_CWMIN_SHIFT(qid);
520*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_CWMIN, val);
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun val = mt76_rr(dev, MT_WMM_CWMAX);
523*4882a593Smuzhiyun val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(qid));
524*4882a593Smuzhiyun val |= cw_max << MT_WMM_CWMAX_SHIFT(qid);
525*4882a593Smuzhiyun mt76_wr(dev, MT_WMM_CWMAX, val);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun return 0;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_conf_tx);
530*4882a593Smuzhiyun
mt76x02_set_tx_ackto(struct mt76x02_dev * dev)531*4882a593Smuzhiyun void mt76x02_set_tx_ackto(struct mt76x02_dev *dev)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun u8 ackto, sifs, slottime = dev->slottime;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* As defined by IEEE 802.11-2007 17.3.8.6 */
536*4882a593Smuzhiyun slottime += 3 * dev->coverage_class;
537*4882a593Smuzhiyun mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
538*4882a593Smuzhiyun MT_BKOFF_SLOT_CFG_SLOTTIME, slottime);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
541*4882a593Smuzhiyun MT_XIFS_TIME_CFG_OFDM_SIFS);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun ackto = slottime + sifs;
544*4882a593Smuzhiyun mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
545*4882a593Smuzhiyun MT_TX_TIMEOUT_CFG_ACKTO, ackto);
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_set_tx_ackto);
548*4882a593Smuzhiyun
mt76x02_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)549*4882a593Smuzhiyun void mt76x02_set_coverage_class(struct ieee80211_hw *hw,
550*4882a593Smuzhiyun s16 coverage_class)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun mutex_lock(&dev->mt76.mutex);
555*4882a593Smuzhiyun dev->coverage_class = max_t(s16, coverage_class, 0);
556*4882a593Smuzhiyun mt76x02_set_tx_ackto(dev);
557*4882a593Smuzhiyun mutex_unlock(&dev->mt76.mutex);
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_set_coverage_class);
560*4882a593Smuzhiyun
mt76x02_set_rts_threshold(struct ieee80211_hw * hw,u32 val)561*4882a593Smuzhiyun int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun if (val != ~0 && val > 0xffff)
566*4882a593Smuzhiyun return -EINVAL;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun mutex_lock(&dev->mt76.mutex);
569*4882a593Smuzhiyun mt76x02_mac_set_rts_thresh(dev, val);
570*4882a593Smuzhiyun mutex_unlock(&dev->mt76.mutex);
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun return 0;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_set_rts_threshold);
575*4882a593Smuzhiyun
mt76x02_sta_rate_tbl_update(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)576*4882a593Smuzhiyun void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
577*4882a593Smuzhiyun struct ieee80211_vif *vif,
578*4882a593Smuzhiyun struct ieee80211_sta *sta)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
581*4882a593Smuzhiyun struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
582*4882a593Smuzhiyun struct ieee80211_sta_rates *rates = rcu_dereference(sta->rates);
583*4882a593Smuzhiyun struct ieee80211_tx_rate rate = {};
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun if (!rates)
586*4882a593Smuzhiyun return;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun rate.idx = rates->rate[0].idx;
589*4882a593Smuzhiyun rate.flags = rates->rate[0].flags;
590*4882a593Smuzhiyun mt76x02_mac_wcid_set_rate(dev, &msta->wcid, &rate);
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_sta_rate_tbl_update);
593*4882a593Smuzhiyun
mt76x02_remove_hdr_pad(struct sk_buff * skb,int len)594*4882a593Smuzhiyun void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun int hdrlen;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun if (!len)
599*4882a593Smuzhiyun return;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun hdrlen = ieee80211_get_hdrlen_from_skb(skb);
602*4882a593Smuzhiyun memmove(skb->data + len, skb->data, hdrlen);
603*4882a593Smuzhiyun skb_pull(skb, len);
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_remove_hdr_pad);
606*4882a593Smuzhiyun
mt76x02_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)607*4882a593Smuzhiyun void mt76x02_sw_scan_complete(struct ieee80211_hw *hw,
608*4882a593Smuzhiyun struct ieee80211_vif *vif)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun clear_bit(MT76_SCANNING, &dev->mphy.state);
613*4882a593Smuzhiyun if (dev->cal.gain_init_done) {
614*4882a593Smuzhiyun /* Restore AGC gain and resume calibration after scanning. */
615*4882a593Smuzhiyun dev->cal.low_gain = -1;
616*4882a593Smuzhiyun ieee80211_queue_delayed_work(hw, &dev->cal_work, 0);
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_sw_scan_complete);
620*4882a593Smuzhiyun
mt76x02_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)621*4882a593Smuzhiyun void mt76x02_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta,
622*4882a593Smuzhiyun bool ps)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
625*4882a593Smuzhiyun struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
626*4882a593Smuzhiyun int idx = msta->wcid.idx;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun mt76_stop_tx_queues(&dev->mt76, sta, true);
629*4882a593Smuzhiyun if (mt76_is_mmio(mdev))
630*4882a593Smuzhiyun mt76x02_mac_wcid_set_drop(dev, idx, ps);
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_sta_ps);
633*4882a593Smuzhiyun
mt76x02_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * info,u32 changed)634*4882a593Smuzhiyun void mt76x02_bss_info_changed(struct ieee80211_hw *hw,
635*4882a593Smuzhiyun struct ieee80211_vif *vif,
636*4882a593Smuzhiyun struct ieee80211_bss_conf *info,
637*4882a593Smuzhiyun u32 changed)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
640*4882a593Smuzhiyun struct mt76x02_dev *dev = hw->priv;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun mutex_lock(&dev->mt76.mutex);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun if (changed & BSS_CHANGED_BSSID)
645*4882a593Smuzhiyun mt76x02_mac_set_bssid(dev, mvif->idx, info->bssid);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun if (changed & BSS_CHANGED_HT || changed & BSS_CHANGED_ERP_CTS_PROT)
648*4882a593Smuzhiyun mt76x02_mac_set_tx_protection(dev, info->use_cts_prot,
649*4882a593Smuzhiyun info->ht_operation_mode);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun if (changed & BSS_CHANGED_BEACON_INT) {
652*4882a593Smuzhiyun mt76_rmw_field(dev, MT_BEACON_TIME_CFG,
653*4882a593Smuzhiyun MT_BEACON_TIME_CFG_INTVAL,
654*4882a593Smuzhiyun info->beacon_int << 4);
655*4882a593Smuzhiyun dev->mt76.beacon_int = info->beacon_int;
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun if (changed & BSS_CHANGED_BEACON_ENABLED)
659*4882a593Smuzhiyun mt76x02_mac_set_beacon_enable(dev, vif, info->enable_beacon);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun if (changed & BSS_CHANGED_ERP_PREAMBLE)
662*4882a593Smuzhiyun mt76x02_mac_set_short_preamble(dev, info->use_short_preamble);
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun if (changed & BSS_CHANGED_ERP_SLOT) {
665*4882a593Smuzhiyun int slottime = info->use_short_slot ? 9 : 20;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun dev->slottime = slottime;
668*4882a593Smuzhiyun mt76x02_set_tx_ackto(dev);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun mutex_unlock(&dev->mt76.mutex);
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_bss_info_changed);
674*4882a593Smuzhiyun
mt76x02_config_mac_addr_list(struct mt76x02_dev * dev)675*4882a593Smuzhiyun void mt76x02_config_mac_addr_list(struct mt76x02_dev *dev)
676*4882a593Smuzhiyun {
677*4882a593Smuzhiyun struct ieee80211_hw *hw = mt76_hw(dev);
678*4882a593Smuzhiyun struct wiphy *wiphy = hw->wiphy;
679*4882a593Smuzhiyun int i;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(dev->macaddr_list); i++) {
682*4882a593Smuzhiyun u8 *addr = dev->macaddr_list[i].addr;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun memcpy(addr, dev->mt76.macaddr, ETH_ALEN);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun if (!i)
687*4882a593Smuzhiyun continue;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun addr[0] |= BIT(1);
690*4882a593Smuzhiyun addr[0] ^= ((i - 1) << 2);
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun wiphy->addresses = dev->macaddr_list;
693*4882a593Smuzhiyun wiphy->n_addresses = ARRAY_SIZE(dev->macaddr_list);
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76x02_config_mac_addr_list);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
698