1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MT76x02_MCU_H 7*4882a593Smuzhiyun #define __MT76x02_MCU_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "mt76x02.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MT_MCU_RESET_CTL 0x070C 12*4882a593Smuzhiyun #define MT_MCU_INT_LEVEL 0x0718 13*4882a593Smuzhiyun #define MT_MCU_COM_REG0 0x0730 14*4882a593Smuzhiyun #define MT_MCU_COM_REG1 0x0734 15*4882a593Smuzhiyun #define MT_MCU_COM_REG2 0x0738 16*4882a593Smuzhiyun #define MT_MCU_COM_REG3 0x073C 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MT_INBAND_PACKET_MAX_LEN 192 19*4882a593Smuzhiyun #define MT_MCU_MEMMAP_WLAN 0x410000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MT_MCU_PCIE_REMAP_BASE4 0x074C 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MT_MCU_SEMAPHORE_00 0x07B0 24*4882a593Smuzhiyun #define MT_MCU_SEMAPHORE_01 0x07B4 25*4882a593Smuzhiyun #define MT_MCU_SEMAPHORE_02 0x07B8 26*4882a593Smuzhiyun #define MT_MCU_SEMAPHORE_03 0x07BC 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define MT_MCU_ILM_ADDR 0x80000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum mcu_cmd { 31*4882a593Smuzhiyun CMD_FUN_SET_OP = 1, 32*4882a593Smuzhiyun CMD_LOAD_CR = 2, 33*4882a593Smuzhiyun CMD_INIT_GAIN_OP = 3, 34*4882a593Smuzhiyun CMD_DYNC_VGA_OP = 6, 35*4882a593Smuzhiyun CMD_TDLS_CH_SW = 7, 36*4882a593Smuzhiyun CMD_BURST_WRITE = 8, 37*4882a593Smuzhiyun CMD_READ_MODIFY_WRITE = 9, 38*4882a593Smuzhiyun CMD_RANDOM_READ = 10, 39*4882a593Smuzhiyun CMD_BURST_READ = 11, 40*4882a593Smuzhiyun CMD_RANDOM_WRITE = 12, 41*4882a593Smuzhiyun CMD_LED_MODE_OP = 16, 42*4882a593Smuzhiyun CMD_POWER_SAVING_OP = 20, 43*4882a593Smuzhiyun CMD_WOW_CONFIG = 21, 44*4882a593Smuzhiyun CMD_WOW_QUERY = 22, 45*4882a593Smuzhiyun CMD_WOW_FEATURE = 24, 46*4882a593Smuzhiyun CMD_CARRIER_DETECT_OP = 28, 47*4882a593Smuzhiyun CMD_RADOR_DETECT_OP = 29, 48*4882a593Smuzhiyun CMD_SWITCH_CHANNEL_OP = 30, 49*4882a593Smuzhiyun CMD_CALIBRATION_OP = 31, 50*4882a593Smuzhiyun CMD_BEACON_OP = 32, 51*4882a593Smuzhiyun CMD_ANTENNA_OP = 33, 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum mcu_power_mode { 55*4882a593Smuzhiyun RADIO_OFF = 0x30, 56*4882a593Smuzhiyun RADIO_ON = 0x31, 57*4882a593Smuzhiyun RADIO_OFF_AUTO_WAKEUP = 0x32, 58*4882a593Smuzhiyun RADIO_OFF_ADVANCE = 0x33, 59*4882a593Smuzhiyun RADIO_ON_ADVANCE = 0x34, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun enum mcu_function { 63*4882a593Smuzhiyun Q_SELECT = 1, 64*4882a593Smuzhiyun BW_SETTING = 2, 65*4882a593Smuzhiyun USB2_SW_DISCONNECT = 2, 66*4882a593Smuzhiyun USB3_SW_DISCONNECT = 3, 67*4882a593Smuzhiyun LOG_FW_DEBUG_MSG = 4, 68*4882a593Smuzhiyun GET_FW_VERSION = 5, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct mt76x02_fw_header { 72*4882a593Smuzhiyun __le32 ilm_len; 73*4882a593Smuzhiyun __le32 dlm_len; 74*4882a593Smuzhiyun __le16 build_ver; 75*4882a593Smuzhiyun __le16 fw_ver; 76*4882a593Smuzhiyun u8 pad[4]; 77*4882a593Smuzhiyun char build_time[16]; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct mt76x02_patch_header { 81*4882a593Smuzhiyun char build_time[16]; 82*4882a593Smuzhiyun char platform[4]; 83*4882a593Smuzhiyun char hw_version[4]; 84*4882a593Smuzhiyun char patch_version[4]; 85*4882a593Smuzhiyun u8 pad[2]; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun int mt76x02_mcu_cleanup(struct mt76x02_dev *dev); 89*4882a593Smuzhiyun int mt76x02_mcu_calibrate(struct mt76x02_dev *dev, int type, u32 param); 90*4882a593Smuzhiyun int mt76x02_mcu_msg_send(struct mt76_dev *mdev, int cmd, const void *data, 91*4882a593Smuzhiyun int len, bool wait_resp); 92*4882a593Smuzhiyun int mt76x02_mcu_function_select(struct mt76x02_dev *dev, enum mcu_function func, 93*4882a593Smuzhiyun u32 val); 94*4882a593Smuzhiyun int mt76x02_mcu_set_radio_state(struct mt76x02_dev *dev, bool on); 95*4882a593Smuzhiyun void mt76x02_set_ethtool_fwver(struct mt76x02_dev *dev, 96*4882a593Smuzhiyun const struct mt76x02_fw_header *h); 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* __MT76x02_MCU_H */ 99