1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __MT76x02_DMA_H
7*4882a593Smuzhiyun #define __MT76x02_DMA_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "mt76x02.h"
10*4882a593Smuzhiyun #include "dma.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define MT_TXD_INFO_LEN GENMASK(15, 0)
13*4882a593Smuzhiyun #define MT_TXD_INFO_NEXT_VLD BIT(16)
14*4882a593Smuzhiyun #define MT_TXD_INFO_TX_BURST BIT(17)
15*4882a593Smuzhiyun #define MT_TXD_INFO_80211 BIT(19)
16*4882a593Smuzhiyun #define MT_TXD_INFO_TSO BIT(20)
17*4882a593Smuzhiyun #define MT_TXD_INFO_CSO BIT(21)
18*4882a593Smuzhiyun #define MT_TXD_INFO_WIV BIT(24)
19*4882a593Smuzhiyun #define MT_TXD_INFO_QSEL GENMASK(26, 25)
20*4882a593Smuzhiyun #define MT_TXD_INFO_DPORT GENMASK(29, 27)
21*4882a593Smuzhiyun #define MT_TXD_INFO_TYPE GENMASK(31, 30)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MT_RX_FCE_INFO_LEN GENMASK(13, 0)
24*4882a593Smuzhiyun #define MT_RX_FCE_INFO_SELF_GEN BIT(15)
25*4882a593Smuzhiyun #define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16)
26*4882a593Smuzhiyun #define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20)
27*4882a593Smuzhiyun #define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
28*4882a593Smuzhiyun #define MT_RX_FCE_INFO_QSEL GENMASK(26, 25)
29*4882a593Smuzhiyun #define MT_RX_FCE_INFO_D_PORT GENMASK(29, 27)
30*4882a593Smuzhiyun #define MT_RX_FCE_INFO_TYPE GENMASK(31, 30)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* MCU request message header */
33*4882a593Smuzhiyun #define MT_MCU_MSG_LEN GENMASK(15, 0)
34*4882a593Smuzhiyun #define MT_MCU_MSG_CMD_SEQ GENMASK(19, 16)
35*4882a593Smuzhiyun #define MT_MCU_MSG_CMD_TYPE GENMASK(26, 20)
36*4882a593Smuzhiyun #define MT_MCU_MSG_PORT GENMASK(29, 27)
37*4882a593Smuzhiyun #define MT_MCU_MSG_TYPE GENMASK(31, 30)
38*4882a593Smuzhiyun #define MT_MCU_MSG_TYPE_CMD BIT(30)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define MT_RX_HEADROOM 32
41*4882a593Smuzhiyun #define MT76X02_RX_RING_SIZE 256
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun enum dma_msg_port {
44*4882a593Smuzhiyun WLAN_PORT,
45*4882a593Smuzhiyun CPU_RX_PORT,
46*4882a593Smuzhiyun CPU_TX_PORT,
47*4882a593Smuzhiyun HOST_PORT,
48*4882a593Smuzhiyun VIRTUAL_CPU_RX_PORT,
49*4882a593Smuzhiyun VIRTUAL_CPU_TX_PORT,
50*4882a593Smuzhiyun DISCARD,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static inline bool
mt76x02_wait_for_wpdma(struct mt76_dev * dev,int timeout)54*4882a593Smuzhiyun mt76x02_wait_for_wpdma(struct mt76_dev *dev, int timeout)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return __mt76_poll(dev, MT_WPDMA_GLO_CFG,
57*4882a593Smuzhiyun MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
58*4882a593Smuzhiyun MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
59*4882a593Smuzhiyun 0, timeout);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun int mt76x02_dma_init(struct mt76x02_dev *dev);
63*4882a593Smuzhiyun void mt76x02_dma_disable(struct mt76x02_dev *dev);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #endif /* __MT76x02_DMA_H */
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