1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MT76x02_DFS_H 7*4882a593Smuzhiyun #define __MT76x02_DFS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun #include <linux/nl80211.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MT_DFS_GP_INTERVAL (10 << 4) /* 64 us unit */ 13*4882a593Smuzhiyun #define MT_DFS_NUM_ENGINES 4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* bbp params */ 16*4882a593Smuzhiyun #define MT_DFS_SYM_ROUND 0 17*4882a593Smuzhiyun #define MT_DFS_DELTA_DELAY 2 18*4882a593Smuzhiyun #define MT_DFS_VGA_MASK 0 19*4882a593Smuzhiyun #define MT_DFS_PWR_GAIN_OFFSET 3 20*4882a593Smuzhiyun #define MT_DFS_PWR_DOWN_TIME 0xf 21*4882a593Smuzhiyun #define MT_DFS_RX_PE_MASK 0xff 22*4882a593Smuzhiyun #define MT_DFS_PKT_END_MASK 0 23*4882a593Smuzhiyun #define MT_DFS_CH_EN 0xf 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* sw detector params */ 26*4882a593Smuzhiyun #define MT_DFS_EVENT_LOOP 64 27*4882a593Smuzhiyun #define MT_DFS_SW_TIMEOUT (HZ / 20) 28*4882a593Smuzhiyun #define MT_DFS_EVENT_WINDOW (HZ / 5) 29*4882a593Smuzhiyun #define MT_DFS_SEQUENCE_WINDOW (200 * (1 << 20)) 30*4882a593Smuzhiyun #define MT_DFS_EVENT_TIME_MARGIN 2000 31*4882a593Smuzhiyun #define MT_DFS_PRI_MARGIN 4 32*4882a593Smuzhiyun #define MT_DFS_SEQUENCE_TH 6 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define MT_DFS_FCC_MAX_PRI ((28570 << 1) + 1000) 35*4882a593Smuzhiyun #define MT_DFS_FCC_MIN_PRI (3000 - 2) 36*4882a593Smuzhiyun #define MT_DFS_JP_MAX_PRI ((80000 << 1) + 1000) 37*4882a593Smuzhiyun #define MT_DFS_JP_MIN_PRI (28500 - 2) 38*4882a593Smuzhiyun #define MT_DFS_ETSI_MAX_PRI (133333 + 125000 + 117647 + 1000) 39*4882a593Smuzhiyun #define MT_DFS_ETSI_MIN_PRI (4500 - 20) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct mt76x02_radar_specs { 42*4882a593Smuzhiyun u8 mode; 43*4882a593Smuzhiyun u16 avg_len; 44*4882a593Smuzhiyun u16 e_low; 45*4882a593Smuzhiyun u16 e_high; 46*4882a593Smuzhiyun u16 w_low; 47*4882a593Smuzhiyun u16 w_high; 48*4882a593Smuzhiyun u16 w_margin; 49*4882a593Smuzhiyun u32 t_low; 50*4882a593Smuzhiyun u32 t_high; 51*4882a593Smuzhiyun u16 t_margin; 52*4882a593Smuzhiyun u32 b_low; 53*4882a593Smuzhiyun u32 b_high; 54*4882a593Smuzhiyun u32 event_expiration; 55*4882a593Smuzhiyun u16 pwr_jmp; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define MT_DFS_CHECK_EVENT(x) ((x) != GENMASK(31, 0)) 59*4882a593Smuzhiyun #define MT_DFS_EVENT_ENGINE(x) (((x) & BIT(31)) ? 2 : 0) 60*4882a593Smuzhiyun #define MT_DFS_EVENT_TIMESTAMP(x) ((x) & GENMASK(21, 0)) 61*4882a593Smuzhiyun #define MT_DFS_EVENT_WIDTH(x) ((x) & GENMASK(11, 0)) 62*4882a593Smuzhiyun struct mt76x02_dfs_event { 63*4882a593Smuzhiyun unsigned long fetch_ts; 64*4882a593Smuzhiyun u32 ts; 65*4882a593Smuzhiyun u16 width; 66*4882a593Smuzhiyun u8 engine; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define MT_DFS_EVENT_BUFLEN 256 70*4882a593Smuzhiyun struct mt76x02_dfs_event_rb { 71*4882a593Smuzhiyun struct mt76x02_dfs_event data[MT_DFS_EVENT_BUFLEN]; 72*4882a593Smuzhiyun int h_rb, t_rb; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct mt76x02_dfs_sequence { 76*4882a593Smuzhiyun struct list_head head; 77*4882a593Smuzhiyun u32 first_ts; 78*4882a593Smuzhiyun u32 last_ts; 79*4882a593Smuzhiyun u32 pri; 80*4882a593Smuzhiyun u16 count; 81*4882a593Smuzhiyun u8 engine; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct mt76x02_dfs_hw_pulse { 85*4882a593Smuzhiyun u8 engine; 86*4882a593Smuzhiyun u32 period; 87*4882a593Smuzhiyun u32 w1; 88*4882a593Smuzhiyun u32 w2; 89*4882a593Smuzhiyun u32 burst; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct mt76x02_dfs_sw_detector_params { 93*4882a593Smuzhiyun u32 min_pri; 94*4882a593Smuzhiyun u32 max_pri; 95*4882a593Smuzhiyun u32 pri_margin; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct mt76x02_dfs_engine_stats { 99*4882a593Smuzhiyun u32 hw_pattern; 100*4882a593Smuzhiyun u32 hw_pulse_discarded; 101*4882a593Smuzhiyun u32 sw_pattern; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct mt76x02_dfs_seq_stats { 105*4882a593Smuzhiyun u32 seq_pool_len; 106*4882a593Smuzhiyun u32 seq_len; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun struct mt76x02_dfs_pattern_detector { 110*4882a593Smuzhiyun u8 chirp_pulse_cnt; 111*4882a593Smuzhiyun u32 chirp_pulse_ts; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun struct mt76x02_dfs_sw_detector_params sw_dpd_params; 114*4882a593Smuzhiyun struct mt76x02_dfs_event_rb event_rb[2]; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun struct list_head sequences; 117*4882a593Smuzhiyun struct list_head seq_pool; 118*4882a593Smuzhiyun struct mt76x02_dfs_seq_stats seq_stats; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun unsigned long last_sw_check; 121*4882a593Smuzhiyun u32 last_event_ts; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct mt76x02_dfs_engine_stats stats[MT_DFS_NUM_ENGINES]; 124*4882a593Smuzhiyun struct tasklet_struct dfs_tasklet; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun void mt76x02_dfs_init_params(struct mt76x02_dev *dev); 128*4882a593Smuzhiyun void mt76x02_dfs_init_detector(struct mt76x02_dev *dev); 129*4882a593Smuzhiyun void mt76x02_regd_notifier(struct wiphy *wiphy, 130*4882a593Smuzhiyun struct regulatory_request *request); 131*4882a593Smuzhiyun void mt76x02_phy_dfs_adjust_agc(struct mt76x02_dev *dev); 132*4882a593Smuzhiyun #endif /* __MT76x02_DFS_H */ 133