1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4*4882a593Smuzhiyun * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __MT76x02_H
8*4882a593Smuzhiyun #define __MT76x02_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kfifo.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "mt76.h"
13*4882a593Smuzhiyun #include "mt76x02_regs.h"
14*4882a593Smuzhiyun #include "mt76x02_mac.h"
15*4882a593Smuzhiyun #include "mt76x02_dfs.h"
16*4882a593Smuzhiyun #include "mt76x02_dma.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define MT76x02_TX_RING_SIZE 512
19*4882a593Smuzhiyun #define MT76x02_PSD_RING_SIZE 128
20*4882a593Smuzhiyun #define MT76x02_N_WCIDS 128
21*4882a593Smuzhiyun #define MT_CALIBRATE_INTERVAL HZ
22*4882a593Smuzhiyun #define MT_MAC_WORK_INTERVAL (HZ / 10)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MT_WATCHDOG_TIME (HZ / 10)
25*4882a593Smuzhiyun #define MT_TX_HANG_TH 10
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define MT_MAX_CHAINS 2
28*4882a593Smuzhiyun struct mt76x02_rx_freq_cal {
29*4882a593Smuzhiyun s8 high_gain[MT_MAX_CHAINS];
30*4882a593Smuzhiyun s8 rssi_offset[MT_MAX_CHAINS];
31*4882a593Smuzhiyun s8 lna_gain;
32*4882a593Smuzhiyun u32 mcu_gain;
33*4882a593Smuzhiyun s16 temp_offset;
34*4882a593Smuzhiyun u8 freq_offset;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun struct mt76x02_calibration {
38*4882a593Smuzhiyun struct mt76x02_rx_freq_cal rx;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun u8 agc_gain_init[MT_MAX_CHAINS];
41*4882a593Smuzhiyun u8 agc_gain_cur[MT_MAX_CHAINS];
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun u16 false_cca;
44*4882a593Smuzhiyun s8 avg_rssi_all;
45*4882a593Smuzhiyun s8 agc_gain_adjust;
46*4882a593Smuzhiyun s8 agc_lowest_gain;
47*4882a593Smuzhiyun s8 low_gain;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun s8 temp_vco;
50*4882a593Smuzhiyun s8 temp;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun bool init_cal_done;
53*4882a593Smuzhiyun bool tssi_cal_done;
54*4882a593Smuzhiyun bool tssi_comp_pending;
55*4882a593Smuzhiyun bool dpd_cal_done;
56*4882a593Smuzhiyun bool channel_cal_done;
57*4882a593Smuzhiyun bool gain_init_done;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun int tssi_target;
60*4882a593Smuzhiyun s8 tssi_dc;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct mt76x02_beacon_ops {
64*4882a593Smuzhiyun unsigned int nslots;
65*4882a593Smuzhiyun unsigned int slot_size;
66*4882a593Smuzhiyun void (*pre_tbtt_enable)(struct mt76x02_dev *dev, bool en);
67*4882a593Smuzhiyun void (*beacon_enable)(struct mt76x02_dev *dev, bool en);
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define mt76x02_beacon_enable(dev, enable) \
71*4882a593Smuzhiyun (dev)->beacon_ops->beacon_enable(dev, enable)
72*4882a593Smuzhiyun #define mt76x02_pre_tbtt_enable(dev, enable) \
73*4882a593Smuzhiyun (dev)->beacon_ops->pre_tbtt_enable(dev, enable)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun struct mt76x02_dev {
76*4882a593Smuzhiyun union { /* must be first */
77*4882a593Smuzhiyun struct mt76_dev mt76;
78*4882a593Smuzhiyun struct mt76_phy mphy;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct mac_address macaddr_list[8];
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun struct mutex phy_mutex;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun u16 chainmask;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun u8 txdone_seq;
88*4882a593Smuzhiyun DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);
89*4882a593Smuzhiyun spinlock_t txstatus_fifo_lock;
90*4882a593Smuzhiyun u32 tx_airtime;
91*4882a593Smuzhiyun u32 ampdu_ref;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun struct sk_buff *rx_head;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct delayed_work cal_work;
96*4882a593Smuzhiyun struct delayed_work wdt_work;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun struct hrtimer pre_tbtt_timer;
99*4882a593Smuzhiyun struct work_struct pre_tbtt_work;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun const struct mt76x02_beacon_ops *beacon_ops;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun u8 beacon_data_count;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun u8 tbtt_count;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun u32 tx_hang_reset;
108*4882a593Smuzhiyun u8 tx_hang_check;
109*4882a593Smuzhiyun u8 mcu_timeout;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun struct mt76x02_calibration cal;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun int txpower_conf;
114*4882a593Smuzhiyun s8 target_power;
115*4882a593Smuzhiyun s8 target_power_delta[2];
116*4882a593Smuzhiyun bool enable_tpc;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun bool no_2ghz;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun s16 coverage_class;
121*4882a593Smuzhiyun u8 slottime;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct mt76x02_dfs_pattern_detector dfs_pd;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* edcca monitor */
126*4882a593Smuzhiyun unsigned long ed_trigger_timeout;
127*4882a593Smuzhiyun bool ed_tx_blocked;
128*4882a593Smuzhiyun bool ed_monitor;
129*4882a593Smuzhiyun u8 ed_monitor_enabled;
130*4882a593Smuzhiyun u8 ed_monitor_learning;
131*4882a593Smuzhiyun u8 ed_trigger;
132*4882a593Smuzhiyun u8 ed_silent;
133*4882a593Smuzhiyun ktime_t ed_time;
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun extern struct ieee80211_rate mt76x02_rates[12];
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun void mt76x02_init_device(struct mt76x02_dev *dev);
139*4882a593Smuzhiyun void mt76x02_configure_filter(struct ieee80211_hw *hw,
140*4882a593Smuzhiyun unsigned int changed_flags,
141*4882a593Smuzhiyun unsigned int *total_flags, u64 multicast);
142*4882a593Smuzhiyun int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
143*4882a593Smuzhiyun struct ieee80211_sta *sta);
144*4882a593Smuzhiyun void mt76x02_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
145*4882a593Smuzhiyun struct ieee80211_sta *sta);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun void mt76x02_config_mac_addr_list(struct mt76x02_dev *dev);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun int mt76x02_add_interface(struct ieee80211_hw *hw,
150*4882a593Smuzhiyun struct ieee80211_vif *vif);
151*4882a593Smuzhiyun void mt76x02_remove_interface(struct ieee80211_hw *hw,
152*4882a593Smuzhiyun struct ieee80211_vif *vif);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
155*4882a593Smuzhiyun struct ieee80211_ampdu_params *params);
156*4882a593Smuzhiyun int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
157*4882a593Smuzhiyun struct ieee80211_vif *vif, struct ieee80211_sta *sta,
158*4882a593Smuzhiyun struct ieee80211_key_conf *key);
159*4882a593Smuzhiyun int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
160*4882a593Smuzhiyun u16 queue, const struct ieee80211_tx_queue_params *params);
161*4882a593Smuzhiyun void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
162*4882a593Smuzhiyun struct ieee80211_vif *vif,
163*4882a593Smuzhiyun struct ieee80211_sta *sta);
164*4882a593Smuzhiyun s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
165*4882a593Smuzhiyun const struct ieee80211_tx_rate *rate);
166*4882a593Smuzhiyun s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr,
167*4882a593Smuzhiyun s8 max_txpwr_adj);
168*4882a593Smuzhiyun void mt76x02_wdt_work(struct work_struct *work);
169*4882a593Smuzhiyun void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr);
170*4882a593Smuzhiyun void mt76x02_set_tx_ackto(struct mt76x02_dev *dev);
171*4882a593Smuzhiyun void mt76x02_set_coverage_class(struct ieee80211_hw *hw,
172*4882a593Smuzhiyun s16 coverage_class);
173*4882a593Smuzhiyun int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
174*4882a593Smuzhiyun void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
175*4882a593Smuzhiyun bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
176*4882a593Smuzhiyun void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
177*4882a593Smuzhiyun struct sk_buff *skb);
178*4882a593Smuzhiyun void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
179*4882a593Smuzhiyun irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
180*4882a593Smuzhiyun void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
181*4882a593Smuzhiyun struct sk_buff *skb);
182*4882a593Smuzhiyun int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
183*4882a593Smuzhiyun enum mt76_txq_id qid, struct mt76_wcid *wcid,
184*4882a593Smuzhiyun struct ieee80211_sta *sta,
185*4882a593Smuzhiyun struct mt76_tx_info *tx_info);
186*4882a593Smuzhiyun void mt76x02_sw_scan_complete(struct ieee80211_hw *hw,
187*4882a593Smuzhiyun struct ieee80211_vif *vif);
188*4882a593Smuzhiyun void mt76x02_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
189*4882a593Smuzhiyun void mt76x02_bss_info_changed(struct ieee80211_hw *hw,
190*4882a593Smuzhiyun struct ieee80211_vif *vif,
191*4882a593Smuzhiyun struct ieee80211_bss_conf *info, u32 changed);
192*4882a593Smuzhiyun void mt76x02_reconfig_complete(struct ieee80211_hw *hw,
193*4882a593Smuzhiyun enum ieee80211_reconfig_type reconfig_type);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun struct beacon_bc_data {
196*4882a593Smuzhiyun struct mt76x02_dev *dev;
197*4882a593Smuzhiyun struct sk_buff_head q;
198*4882a593Smuzhiyun struct sk_buff *tail[8];
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun void mt76x02_init_beacon_config(struct mt76x02_dev *dev);
202*4882a593Smuzhiyun void mt76x02e_init_beacon_config(struct mt76x02_dev *dev);
203*4882a593Smuzhiyun void mt76x02_resync_beacon_timer(struct mt76x02_dev *dev);
204*4882a593Smuzhiyun void mt76x02_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif);
205*4882a593Smuzhiyun void mt76x02_enqueue_buffered_bc(struct mt76x02_dev *dev,
206*4882a593Smuzhiyun struct beacon_bc_data *data,
207*4882a593Smuzhiyun int max_nframes);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun void mt76x02_mac_start(struct mt76x02_dev *dev);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun void mt76x02_init_debugfs(struct mt76x02_dev *dev);
212*4882a593Smuzhiyun
is_mt76x0(struct mt76x02_dev * dev)213*4882a593Smuzhiyun static inline bool is_mt76x0(struct mt76x02_dev *dev)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun return mt76_chip(&dev->mt76) == 0x7610 ||
216*4882a593Smuzhiyun mt76_chip(&dev->mt76) == 0x7630 ||
217*4882a593Smuzhiyun mt76_chip(&dev->mt76) == 0x7650;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
is_mt76x2(struct mt76x02_dev * dev)220*4882a593Smuzhiyun static inline bool is_mt76x2(struct mt76x02_dev *dev)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun return mt76_chip(&dev->mt76) == 0x7612 ||
223*4882a593Smuzhiyun mt76_chip(&dev->mt76) == 0x7632 ||
224*4882a593Smuzhiyun mt76_chip(&dev->mt76) == 0x7662 ||
225*4882a593Smuzhiyun mt76_chip(&dev->mt76) == 0x7602;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
mt76x02_irq_enable(struct mt76x02_dev * dev,u32 mask)228*4882a593Smuzhiyun static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
mt76x02_irq_disable(struct mt76x02_dev * dev,u32 mask)233*4882a593Smuzhiyun static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static inline bool
mt76x02_wait_for_txrx_idle(struct mt76_dev * dev)239*4882a593Smuzhiyun mt76x02_wait_for_txrx_idle(struct mt76_dev *dev)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun return __mt76_poll_msec(dev, MT_MAC_STATUS,
242*4882a593Smuzhiyun MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
243*4882a593Smuzhiyun 0, 100);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun static inline struct mt76x02_sta *
mt76x02_rx_get_sta(struct mt76_dev * dev,u8 idx)247*4882a593Smuzhiyun mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct mt76_wcid *wcid;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (idx >= MT76x02_N_WCIDS)
252*4882a593Smuzhiyun return NULL;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun wcid = rcu_dereference(dev->wcid[idx]);
255*4882a593Smuzhiyun if (!wcid)
256*4882a593Smuzhiyun return NULL;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return container_of(wcid, struct mt76x02_sta, wcid);
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun static inline struct mt76_wcid *
mt76x02_rx_get_sta_wcid(struct mt76x02_sta * sta,bool unicast)262*4882a593Smuzhiyun mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun if (!sta)
265*4882a593Smuzhiyun return NULL;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (unicast)
268*4882a593Smuzhiyun return &sta->wcid;
269*4882a593Smuzhiyun else
270*4882a593Smuzhiyun return &sta->vif->group_wcid;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun #endif /* __MT76x02_H */
274