xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x0/phy.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * (c) Copyright 2002-2010, Ralink Technology, Inc.
4*4882a593Smuzhiyun  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #ifndef _MT76X0_PHY_H_
7*4882a593Smuzhiyun #define _MT76X0_PHY_H_
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define RF_G_BAND	0x0100
10*4882a593Smuzhiyun #define RF_A_BAND	0x0200
11*4882a593Smuzhiyun #define RF_A_BAND_LB	0x0400
12*4882a593Smuzhiyun #define RF_A_BAND_MB	0x0800
13*4882a593Smuzhiyun #define RF_A_BAND_HB	0x1000
14*4882a593Smuzhiyun #define RF_A_BAND_11J	0x2000
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define RF_BW_20        1
17*4882a593Smuzhiyun #define RF_BW_40        2
18*4882a593Smuzhiyun #define RF_BW_10        4
19*4882a593Smuzhiyun #define RF_BW_80        8
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define MT_RF(bank, reg)		((bank) << 16 | (reg))
22*4882a593Smuzhiyun #define MT_RF_BANK(offset)		((offset) >> 16)
23*4882a593Smuzhiyun #define MT_RF_REG(offset)		((offset) & 0xff)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define MT_RF_VCO_BP_CLOSE_LOOP		BIT(3)
26*4882a593Smuzhiyun #define MT_RF_VCO_BP_CLOSE_LOOP_MASK	GENMASK(3, 0)
27*4882a593Smuzhiyun #define MT_RF_VCO_CAL_MASK		GENMASK(2, 0)
28*4882a593Smuzhiyun #define MT_RF_START_TIME		0x3
29*4882a593Smuzhiyun #define MT_RF_START_TIME_MASK		GENMASK(2, 0)
30*4882a593Smuzhiyun #define MT_RF_SETTLE_TIME_MASK		GENMASK(6, 4)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define MT_RF_PLL_DEN_MASK		GENMASK(4, 0)
33*4882a593Smuzhiyun #define MT_RF_PLL_K_MASK		GENMASK(4, 0)
34*4882a593Smuzhiyun #define MT_RF_SDM_RESET_MASK		BIT(7)
35*4882a593Smuzhiyun #define MT_RF_SDM_MASH_PRBS_MASK	GENMASK(6, 2)
36*4882a593Smuzhiyun #define MT_RF_SDM_BP_MASK		BIT(1)
37*4882a593Smuzhiyun #define MT_RF_ISI_ISO_MASK		GENMASK(7, 6)
38*4882a593Smuzhiyun #define MT_RF_PFD_DLY_MASK		GENMASK(5, 4)
39*4882a593Smuzhiyun #define MT_RF_CLK_SEL_MASK		GENMASK(3, 2)
40*4882a593Smuzhiyun #define MT_RF_XO_DIV_MASK		GENMASK(1, 0)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun struct mt76x0_bbp_switch_item {
43*4882a593Smuzhiyun 	u16 bw_band;
44*4882a593Smuzhiyun 	struct mt76_reg_pair reg_pair;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct mt76x0_rf_switch_item {
48*4882a593Smuzhiyun 	u32 rf_bank_reg;
49*4882a593Smuzhiyun 	u16 bw_band;
50*4882a593Smuzhiyun 	u8 value;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun struct mt76x0_freq_item {
54*4882a593Smuzhiyun 	u8 channel;
55*4882a593Smuzhiyun 	u32 band;
56*4882a593Smuzhiyun 	u8 pllR37;
57*4882a593Smuzhiyun 	u8 pllR36;
58*4882a593Smuzhiyun 	u8 pllR35;
59*4882a593Smuzhiyun 	u8 pllR34;
60*4882a593Smuzhiyun 	u8 pllR33;
61*4882a593Smuzhiyun 	u8 pllR32_b7b5;
62*4882a593Smuzhiyun 	u8 pllR32_b4b0; /* PLL_DEN (Denomina - 8) */
63*4882a593Smuzhiyun 	u8 pllR31_b7b5;
64*4882a593Smuzhiyun 	u8 pllR31_b4b0; /* PLL_K (Nominator *)*/
65*4882a593Smuzhiyun 	u8 pllR30_b7;	/* sdm_reset_n */
66*4882a593Smuzhiyun 	u8 pllR30_b6b2; /* sdmmash_prbs,sin */
67*4882a593Smuzhiyun 	u8 pllR30_b1;	/* sdm_bp */
68*4882a593Smuzhiyun 	u16 pll_n;	/* R30<0>, R29<7:0> (hex) */
69*4882a593Smuzhiyun 	u8 pllR28_b7b6; /* isi,iso */
70*4882a593Smuzhiyun 	u8 pllR28_b5b4;	/* pfd_dly */
71*4882a593Smuzhiyun 	u8 pllR28_b3b2;	/* clksel option */
72*4882a593Smuzhiyun 	u32 pll_sdm_k;	/* R28<1:0>, R27<7:0>, R26<7:0> (hex) SDM_k */
73*4882a593Smuzhiyun 	u8 pllR24_b1b0;	/* xo_div */
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun struct mt76x0_rate_pwr_item {
77*4882a593Smuzhiyun 	s8 mcs_power;
78*4882a593Smuzhiyun 	u8 rf_pa_mode;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun struct mt76x0_rate_pwr_tab {
82*4882a593Smuzhiyun 	struct mt76x0_rate_pwr_item cck[4];
83*4882a593Smuzhiyun 	struct mt76x0_rate_pwr_item ofdm[8];
84*4882a593Smuzhiyun 	struct mt76x0_rate_pwr_item ht[8];
85*4882a593Smuzhiyun 	struct mt76x0_rate_pwr_item vht[10];
86*4882a593Smuzhiyun 	struct mt76x0_rate_pwr_item stbc[8];
87*4882a593Smuzhiyun 	struct mt76x0_rate_pwr_item mcs32;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #endif /* _MT76X0_PHY_H_ */
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