xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7615/testmode.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include "mt7615.h"
5*4882a593Smuzhiyun #include "eeprom.h"
6*4882a593Smuzhiyun #include "mcu.h"
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun enum {
9*4882a593Smuzhiyun 	TM_CHANGED_TXPOWER_CTRL,
10*4882a593Smuzhiyun 	TM_CHANGED_TXPOWER,
11*4882a593Smuzhiyun 	TM_CHANGED_FREQ_OFFSET,
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun 	/* must be last */
14*4882a593Smuzhiyun 	NUM_TM_CHANGED
15*4882a593Smuzhiyun };
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun static const u8 tm_change_map[] = {
19*4882a593Smuzhiyun 	[TM_CHANGED_TXPOWER_CTRL] = MT76_TM_ATTR_TX_POWER_CONTROL,
20*4882a593Smuzhiyun 	[TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
21*4882a593Smuzhiyun 	[TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun static const u32 reg_backup_list[] = {
25*4882a593Smuzhiyun 	MT_WF_PHY_RFINTF3_0(0),
26*4882a593Smuzhiyun 	MT_WF_PHY_RFINTF3_0(1),
27*4882a593Smuzhiyun 	MT_WF_PHY_RFINTF3_0(2),
28*4882a593Smuzhiyun 	MT_WF_PHY_RFINTF3_0(3),
29*4882a593Smuzhiyun 	MT_ANT_SWITCH_CON(2),
30*4882a593Smuzhiyun 	MT_ANT_SWITCH_CON(3),
31*4882a593Smuzhiyun 	MT_ANT_SWITCH_CON(4),
32*4882a593Smuzhiyun 	MT_ANT_SWITCH_CON(6),
33*4882a593Smuzhiyun 	MT_ANT_SWITCH_CON(7),
34*4882a593Smuzhiyun 	MT_ANT_SWITCH_CON(8),
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static const struct {
38*4882a593Smuzhiyun 	u16 wf;
39*4882a593Smuzhiyun 	u16 reg;
40*4882a593Smuzhiyun } rf_backup_list[] = {
41*4882a593Smuzhiyun 	{ 0, 0x48 },
42*4882a593Smuzhiyun 	{ 1, 0x48 },
43*4882a593Smuzhiyun 	{ 2, 0x48 },
44*4882a593Smuzhiyun 	{ 3, 0x48 },
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static int
mt7615_tm_set_tx_power(struct mt7615_phy * phy)48*4882a593Smuzhiyun mt7615_tm_set_tx_power(struct mt7615_phy *phy)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct mt7615_dev *dev = phy->dev;
51*4882a593Smuzhiyun 	struct mt76_phy *mphy = phy->mt76;
52*4882a593Smuzhiyun 	int i, ret, n_chains = hweight8(mphy->antenna_mask);
53*4882a593Smuzhiyun 	struct cfg80211_chan_def *chandef = &mphy->chandef;
54*4882a593Smuzhiyun 	int freq = chandef->center_freq1, len, target_chains;
55*4882a593Smuzhiyun 	u8 *data, *eep = (u8 *)dev->mt76.eeprom.data;
56*4882a593Smuzhiyun 	enum nl80211_band band = chandef->chan->band;
57*4882a593Smuzhiyun 	struct sk_buff *skb;
58*4882a593Smuzhiyun 	struct {
59*4882a593Smuzhiyun 		u8 center_chan;
60*4882a593Smuzhiyun 		u8 dbdc_idx;
61*4882a593Smuzhiyun 		u8 band;
62*4882a593Smuzhiyun 		u8 rsv;
63*4882a593Smuzhiyun 	} __packed req_hdr = {
64*4882a593Smuzhiyun 		.center_chan = ieee80211_frequency_to_channel(freq),
65*4882a593Smuzhiyun 		.band = band,
66*4882a593Smuzhiyun 		.dbdc_idx = phy != &dev->phy,
67*4882a593Smuzhiyun 	};
68*4882a593Smuzhiyun 	u8 *tx_power = NULL;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	if (dev->mt76.test.state != MT76_TM_STATE_OFF)
71*4882a593Smuzhiyun 		tx_power = dev->mt76.test.tx_power;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	len = MT7615_EE_MAX - MT_EE_NIC_CONF_0;
74*4882a593Smuzhiyun 	skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + len);
75*4882a593Smuzhiyun 	if (!skb)
76*4882a593Smuzhiyun 		return -ENOMEM;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	skb_put_data(skb, &req_hdr, sizeof(req_hdr));
79*4882a593Smuzhiyun 	data = skb_put_data(skb, eep + MT_EE_NIC_CONF_0, len);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	target_chains = mt7615_ext_pa_enabled(dev, band) ? 1 : n_chains;
82*4882a593Smuzhiyun 	for (i = 0; i < target_chains; i++) {
83*4882a593Smuzhiyun 		ret = mt7615_eeprom_get_target_power_index(dev, chandef->chan, i);
84*4882a593Smuzhiyun 		if (ret < 0) {
85*4882a593Smuzhiyun 			dev_kfree_skb(skb);
86*4882a593Smuzhiyun 			return -EINVAL;
87*4882a593Smuzhiyun 		}
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 		if (tx_power && tx_power[i])
90*4882a593Smuzhiyun 			data[ret - MT_EE_NIC_CONF_0] = tx_power[i];
91*4882a593Smuzhiyun 	}
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
94*4882a593Smuzhiyun 				       MCU_EXT_CMD_SET_TX_POWER_CTRL, false);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static void
mt7615_tm_reg_backup_restore(struct mt7615_dev * dev)98*4882a593Smuzhiyun mt7615_tm_reg_backup_restore(struct mt7615_dev *dev)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	u32 *b = dev->test.reg_backup;
101*4882a593Smuzhiyun 	int n_regs = ARRAY_SIZE(reg_backup_list);
102*4882a593Smuzhiyun 	int n_rf_regs = ARRAY_SIZE(rf_backup_list);
103*4882a593Smuzhiyun 	int i;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	if (dev->mt76.test.state == MT76_TM_STATE_OFF) {
106*4882a593Smuzhiyun 		for (i = 0; i < n_regs; i++)
107*4882a593Smuzhiyun 			mt76_wr(dev, reg_backup_list[i], b[i]);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 		for (i = 0; i < n_rf_regs; i++)
110*4882a593Smuzhiyun 			mt7615_rf_wr(dev, rf_backup_list[i].wf,
111*4882a593Smuzhiyun 				     rf_backup_list[i].reg, b[n_regs + i]);
112*4882a593Smuzhiyun 		return;
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	if (b)
116*4882a593Smuzhiyun 		return;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	b = devm_kzalloc(dev->mt76.dev, 4 * (n_regs + n_rf_regs),
119*4882a593Smuzhiyun 			 GFP_KERNEL);
120*4882a593Smuzhiyun 	if (!b)
121*4882a593Smuzhiyun 		return;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	dev->test.reg_backup = b;
124*4882a593Smuzhiyun 	for (i = 0; i < n_regs; i++)
125*4882a593Smuzhiyun 		b[i] = mt76_rr(dev, reg_backup_list[i]);
126*4882a593Smuzhiyun 	for (i = 0; i < n_rf_regs; i++)
127*4882a593Smuzhiyun 		b[n_regs + i] = mt7615_rf_rr(dev, rf_backup_list[i].wf,
128*4882a593Smuzhiyun 					     rf_backup_list[i].reg);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun static void
mt7615_tm_init_phy(struct mt7615_dev * dev,struct mt7615_phy * phy)133*4882a593Smuzhiyun mt7615_tm_init_phy(struct mt7615_dev *dev, struct mt7615_phy *phy)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	unsigned int total_flags = ~0;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
138*4882a593Smuzhiyun 		return;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
141*4882a593Smuzhiyun 	mt7615_set_channel(phy);
142*4882a593Smuzhiyun 	mt7615_ops.configure_filter(phy->mt76->hw, 0, &total_flags, 0);
143*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	mt7615_tm_reg_backup_restore(dev);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static void
mt7615_tm_init(struct mt7615_dev * dev)149*4882a593Smuzhiyun mt7615_tm_init(struct mt7615_dev *dev)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	mt7615_tm_init_phy(dev, &dev->phy);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	if (dev->mt76.phy2)
154*4882a593Smuzhiyun 		mt7615_tm_init_phy(dev, dev->mt76.phy2->priv);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static void
mt7615_tm_set_rx_enable(struct mt7615_dev * dev,bool en)158*4882a593Smuzhiyun mt7615_tm_set_rx_enable(struct mt7615_dev *dev, bool en)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	u32 rqcr_mask = (MT_ARB_RQCR_RX_START |
161*4882a593Smuzhiyun 			 MT_ARB_RQCR_RXV_START |
162*4882a593Smuzhiyun 			 MT_ARB_RQCR_RXV_R_EN |
163*4882a593Smuzhiyun 			 MT_ARB_RQCR_RXV_T_EN) *
164*4882a593Smuzhiyun 			(BIT(0) | BIT(MT_ARB_RQCR_BAND_SHIFT));
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	if (en) {
167*4882a593Smuzhiyun 		mt76_clear(dev, MT_ARB_SCR,
168*4882a593Smuzhiyun 			   MT_ARB_SCR_RX0_DISABLE | MT_ARB_SCR_RX1_DISABLE);
169*4882a593Smuzhiyun 		mt76_set(dev, MT_ARB_RQCR, rqcr_mask);
170*4882a593Smuzhiyun 	} else {
171*4882a593Smuzhiyun 		mt76_set(dev, MT_ARB_SCR,
172*4882a593Smuzhiyun 			 MT_ARB_SCR_RX0_DISABLE | MT_ARB_SCR_RX1_DISABLE);
173*4882a593Smuzhiyun 		mt76_clear(dev, MT_ARB_RQCR, rqcr_mask);
174*4882a593Smuzhiyun 	}
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static void
mt7615_tm_set_tx_antenna(struct mt7615_dev * dev,bool en)178*4882a593Smuzhiyun mt7615_tm_set_tx_antenna(struct mt7615_dev *dev, bool en)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	struct mt76_testmode_data *td = &dev->mt76.test;
181*4882a593Smuzhiyun 	u8 mask = td->tx_antenna_mask;
182*4882a593Smuzhiyun 	int i;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	if (!mask)
185*4882a593Smuzhiyun 		return;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	if (!en)
188*4882a593Smuzhiyun 		mask = dev->phy.chainmask;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	for (i = 0; i < 4; i++) {
191*4882a593Smuzhiyun 		mt76_rmw_field(dev, MT_WF_PHY_RFINTF3_0(i),
192*4882a593Smuzhiyun 			       MT_WF_PHY_RFINTF3_0_ANT,
193*4882a593Smuzhiyun 			       (td->tx_antenna_mask & BIT(i)) ? 0 : 0xa);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	}
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	/* 2.4 GHz band */
198*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(3), MT_ANT_SWITCH_CON_MODE(0),
199*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(0)) ? 0x8 : 0x1b);
200*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(4), MT_ANT_SWITCH_CON_MODE(2),
201*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(1)) ? 0xe : 0x1b);
202*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(6), MT_ANT_SWITCH_CON_MODE1(0),
203*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(2)) ? 0x0 : 0xf);
204*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(7), MT_ANT_SWITCH_CON_MODE1(2),
205*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(3)) ? 0x6 : 0xf);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* 5 GHz band */
208*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(4), MT_ANT_SWITCH_CON_MODE(1),
209*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(0)) ? 0xd : 0x1b);
210*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(2), MT_ANT_SWITCH_CON_MODE(3),
211*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(1)) ? 0x13 : 0x1b);
212*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(7), MT_ANT_SWITCH_CON_MODE1(1),
213*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(2)) ? 0x5 : 0xf);
214*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_ANT_SWITCH_CON(8), MT_ANT_SWITCH_CON_MODE1(3),
215*4882a593Smuzhiyun 		       (td->tx_antenna_mask & BIT(3)) ? 0xb : 0xf);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	for (i = 0; i < 4; i++) {
218*4882a593Smuzhiyun 		u32 val;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 		val = mt7615_rf_rr(dev, i, 0x48);
221*4882a593Smuzhiyun 		val &= ~(0x3ff << 20);
222*4882a593Smuzhiyun 		if (td->tx_antenna_mask & BIT(i))
223*4882a593Smuzhiyun 			val |= 3 << 20;
224*4882a593Smuzhiyun 		else
225*4882a593Smuzhiyun 			val |= (2 << 28) | (2 << 26) | (8 << 20);
226*4882a593Smuzhiyun 		mt7615_rf_wr(dev, i, 0x48, val);
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun static void
mt7615_tm_set_tx_frames(struct mt7615_dev * dev,bool en)231*4882a593Smuzhiyun mt7615_tm_set_tx_frames(struct mt7615_dev *dev, bool en)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	struct ieee80211_tx_info *info;
234*4882a593Smuzhiyun 	struct sk_buff *skb = dev->mt76.test.tx_skb;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	mt7615_mcu_set_chan_info(&dev->phy, MCU_EXT_CMD_SET_RX_PATH);
237*4882a593Smuzhiyun 	mt7615_tm_set_tx_antenna(dev, en);
238*4882a593Smuzhiyun 	mt7615_tm_set_rx_enable(dev, !en);
239*4882a593Smuzhiyun 	if (!en || !skb)
240*4882a593Smuzhiyun 		return;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	info = IEEE80211_SKB_CB(skb);
243*4882a593Smuzhiyun 	info->control.vif = dev->phy.monitor_vif;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static void
mt7615_tm_update_params(struct mt7615_dev * dev,u32 changed)247*4882a593Smuzhiyun mt7615_tm_update_params(struct mt7615_dev *dev, u32 changed)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	struct mt76_testmode_data *td = &dev->mt76.test;
250*4882a593Smuzhiyun 	bool en = dev->mt76.test.state != MT76_TM_STATE_OFF;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	if (changed & BIT(TM_CHANGED_TXPOWER_CTRL))
253*4882a593Smuzhiyun 		mt7615_mcu_set_test_param(dev, MCU_ATE_SET_TX_POWER_CONTROL,
254*4882a593Smuzhiyun 					  en, en && td->tx_power_control);
255*4882a593Smuzhiyun 	if (changed & BIT(TM_CHANGED_FREQ_OFFSET))
256*4882a593Smuzhiyun 		mt7615_mcu_set_test_param(dev, MCU_ATE_SET_FREQ_OFFSET,
257*4882a593Smuzhiyun 					  en, en ? td->freq_offset : 0);
258*4882a593Smuzhiyun 	if (changed & BIT(TM_CHANGED_TXPOWER))
259*4882a593Smuzhiyun 		mt7615_tm_set_tx_power(&dev->phy);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun static int
mt7615_tm_set_state(struct mt76_dev * mdev,enum mt76_testmode_state state)263*4882a593Smuzhiyun mt7615_tm_set_state(struct mt76_dev *mdev, enum mt76_testmode_state state)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
266*4882a593Smuzhiyun 	struct mt76_testmode_data *td = &mdev->test;
267*4882a593Smuzhiyun 	enum mt76_testmode_state prev_state = td->state;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	mdev->test.state = state;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (prev_state == MT76_TM_STATE_TX_FRAMES)
272*4882a593Smuzhiyun 		mt7615_tm_set_tx_frames(dev, false);
273*4882a593Smuzhiyun 	else if (state == MT76_TM_STATE_TX_FRAMES)
274*4882a593Smuzhiyun 		mt7615_tm_set_tx_frames(dev, true);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	if (state <= MT76_TM_STATE_IDLE)
277*4882a593Smuzhiyun 		mt7615_tm_init(dev);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	if ((state == MT76_TM_STATE_IDLE &&
280*4882a593Smuzhiyun 	     prev_state == MT76_TM_STATE_OFF) ||
281*4882a593Smuzhiyun 	    (state == MT76_TM_STATE_OFF &&
282*4882a593Smuzhiyun 	     prev_state == MT76_TM_STATE_IDLE)) {
283*4882a593Smuzhiyun 		u32 changed = 0;
284*4882a593Smuzhiyun 		int i;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
287*4882a593Smuzhiyun 			u16 cur = tm_change_map[i];
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 			if (td->param_set[cur / 32] & BIT(cur % 32))
290*4882a593Smuzhiyun 				changed |= BIT(i);
291*4882a593Smuzhiyun 		}
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 		mt7615_tm_update_params(dev, changed);
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	return 0;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun static int
mt7615_tm_set_params(struct mt76_dev * mdev,struct nlattr ** tb,enum mt76_testmode_state new_state)300*4882a593Smuzhiyun mt7615_tm_set_params(struct mt76_dev *mdev, struct nlattr **tb,
301*4882a593Smuzhiyun 		     enum mt76_testmode_state new_state)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
304*4882a593Smuzhiyun 	struct mt76_testmode_data *td = &dev->mt76.test;
305*4882a593Smuzhiyun 	u32 changed = 0;
306*4882a593Smuzhiyun 	int i;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	BUILD_BUG_ON(NUM_TM_CHANGED >= 32);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if (new_state == MT76_TM_STATE_OFF ||
311*4882a593Smuzhiyun 	    td->state == MT76_TM_STATE_OFF)
312*4882a593Smuzhiyun 		return 0;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	if (td->tx_antenna_mask & ~dev->phy.chainmask)
315*4882a593Smuzhiyun 		return -EINVAL;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
318*4882a593Smuzhiyun 		if (tb[tm_change_map[i]])
319*4882a593Smuzhiyun 			changed |= BIT(i);
320*4882a593Smuzhiyun 	}
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	mt7615_tm_update_params(dev, changed);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	return 0;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun static int
mt7615_tm_dump_stats(struct mt76_dev * mdev,struct sk_buff * msg)328*4882a593Smuzhiyun mt7615_tm_dump_stats(struct mt76_dev *mdev, struct sk_buff *msg)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun 	struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
331*4882a593Smuzhiyun 	void *rx, *rssi;
332*4882a593Smuzhiyun 	int i;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
335*4882a593Smuzhiyun 	if (!rx)
336*4882a593Smuzhiyun 		return -ENOMEM;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, dev->test.last_freq_offset) ||
339*4882a593Smuzhiyun 	    nla_put_s32(msg, MT76_TM_RX_ATTR_IB_RSSI, dev->test.last_ib_rssi) ||
340*4882a593Smuzhiyun 	    nla_put_s32(msg, MT76_TM_RX_ATTR_WB_RSSI, dev->test.last_wb_rssi))
341*4882a593Smuzhiyun 		return -ENOMEM;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI);
344*4882a593Smuzhiyun 	if (!rssi)
345*4882a593Smuzhiyun 		return -ENOMEM;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(dev->test.last_rcpi); i++)
348*4882a593Smuzhiyun 		if (nla_put_u8(msg, i, dev->test.last_rcpi[i]))
349*4882a593Smuzhiyun 			return -ENOMEM;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	nla_nest_end(msg, rssi);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	nla_nest_end(msg, rx);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun const struct mt76_testmode_ops mt7615_testmode_ops = {
359*4882a593Smuzhiyun 	.set_state = mt7615_tm_set_state,
360*4882a593Smuzhiyun 	.set_params = mt7615_tm_set_params,
361*4882a593Smuzhiyun 	.dump_stats = mt7615_tm_dump_stats,
362*4882a593Smuzhiyun };
363